Scan time reduction of PLCs by dedicated parallel-execution multiple PID controllers using an FPGA

Ci a ion: Dhanabalan, G.; Tamil Sel i, S.; Mahdal, M. Scan Time Reduc ion o PLCs by Dedica ed Pa allel-Execu ion Mul iple PID Con olle s Using an FPGA. Senso s 2022,22, 4584. h ps://doi.o g/ 10.3390/s22124584 Academic Edi o : Mehme Rasi Yuce Recei ed: 18 May 2022 Accep ed: 15 June 2022 Published: 17 June 2022 Publishe ’s No e: MDPI s ays neu al wi h ega d o ju isdic ional claims in published maps and ins i u ional a il- ia ions. Copy igh : © 2022 by he au ho s. Licensee MDPI, Basel, Swi ze land. This a icle is an open access a icle dis ibu ed unde he e ms and condi ions o he C ea i e Commons A ibu ion (CC BY) license (h ps:// c ea i ecommons.o g/licenses/by/ 4.0/). senso s A icle Scan Time Reduc ion o PLCs by Dedica ed Pa allel-Execu ion Mul iple PID Con olle s Using an FPGA Gnanaseka an Dhanabalan 1, Sanka Tamil Sel i 1and Mi osla Mahdal 2,* 1Depa men o Elec onics and Communica ion Enginee ing, AAA College o Enginee ing and Technology, Si akasi 626123, India; [email p o ec ed] (G.D.); [email p o ec ed] (S.T.S.) 2Depa men o Con ol Sys ems and Ins umen a ion, Facul y o Mechanical Enginee ing, VSB-Technical Uni e si y o Os a a, 17. Lis opadu 2172/15, 708 00 Os a a, Czech Republic *Co espondence: mi osla [email p o ec ed] Abs ac : A p og ammable logic con olle (PLC) execu es a ladde diag am (LD) using inpu and ou pu modules. An LD also has PID con olle unc ion blocks. I con ains as many PID unc ion blocks as he numbe o p ocess pa ame e s o be con olled. Adding mo e p ocess pa ame e s slows down PLC scan ime. P ocess pa ame e s a e measu ed as analog signals. The analog inpu module in he PLC con e s hese analog signals in o digi al signals and o wa ds hem o he PID con olle as inpu s. In his esea ch wo k, a ield-p og ammable ga e a ay (FPGA)-based mul iple PID con olle is p oposed o e ain PLC scan ime a a lowe alue. Concu en execu ion o mul iple PID con olle s was assu ed by assigning sepa a e FPGA ha dwa e esou ces o e e y PID con olle . Digi al inpu o he PID con olle is ou ed by he no el idea o analog o digi al con e sion (ADC), pe o med using a digi al o analog con e e (DAC), compa a o , and FPGA. ADC combined wi h dedica ed PID con olle logic in an FPGA o e e y closed-loop con ol sys em con i ms concu en execu ion o mul iple PID con olle s. The ime equi ed o execu e wo closed-loop con ols was iden i ied as 18.96000004 ms. This design can be used ei he wi h o wi hou a PLC. Keywo ds: analog o digi al con e sion; da a acquisi ion; ield p og ammable ga e a ays; PI con ol; p og ammable logic con olle ; scan ime 1. In oduc ion The con ibu ion o a p og ammable logic con olle (PLC) in an au oma ion sys em is signi ican . I ac s as a con olle o closed-loop sys em(s) and execu es combina ional o sequen ial logic epea edly h ough he ladde diag am (LD). I is capable o handling a su icien numbe o analog and digi al signals. Howe e , adding mo e and mo e signals o i is a bu den. The PLC needs an analog inpu module (AIM), an analog ou pu module (AOM), and a p opo ional, in eg al, and de i a i e (PID) unc ion block in he LD o ealize a closed-loop con ol sys em. This ensu es ha he ou pu o he closed-loop con ol sys em is always a he desi ed alue. Whene e he PLC eads he PID unc ion block in i s LD, i e e s o he AIM o ead he analog alue conce ned wi h ha unc ion block. I gene a es a digi al ou pu a e comple ing he execu ion o he PID unc ion block and o wa ds i o he AOM. A digi al o analog con e e (DAC) in he AOM con e s his digi al ou pu in o an analog signal and ac i a es he inal con ol elemen . Adding mo e PID unc ion blocks delays he execu ion o he emaining ungs in he LD and inc eases he scan ime o he PLC. The basic eason behind his is ha he PLC, AIM, and AOM ha e p ocesso s o pe o m hei unc ions. An elabo a e li e a u e e iew was ca ied ou o unde s and how esea che s ocus on he mul iple closed-loop con ol sys ems. A model o composi ion and in en o y con ol o a con inuous e hanol–wa e nonlinea pilo dis illa ion column has been de eloped in [ 1 ]. A compu e ac s as a con olle , and he con ol ac ion is es ablished using a neu al ne wo k combined wi h he gene ic algo i hm. A no el echnique o moni o he condi ion Senso s 2022,22, 4584. h ps://doi.o g/10.3390/s22124584 h ps://www.mdpi.com/jou nal/senso s Senso s 2022,22, 4584 2 o 17 o a wind u bine gea box using an NI da a acquisi ion ca d and LabVIEW is explained in [ 2 ]. The design in oduced a new signal p ocessing echnique o moni o he condi ion o he gea box. A digi al signal p ocesso (DSP)-based speed con ol ac ion o a h ee-phase induc ion mo o using he ec o -con olled me hod has been implemen ed in [ 3 ]. The DSP p ocesso modi ies he alue o he phase cu en o a y he mo o speed. A wa e pumping sys em has been de eloped in [ 4 ]. I used a PLC and an indus ial wide a ea ne wo k (WAN) o con ol he wa e le el in he ank. The digi al implemen a ion o a as , disc e e S ockwell ans o m (FDST) o accu a e powe quali y (PQ) e en de ec ion and ene gy me e ing is discussed in [ 5 ]. The FDST algo i hm was implemen ed in an FPGA, and he PQ e en s we e analyzed using LabVIEW. The design used a 12-bi analog o digi al con e e (ADC), a ailable in he FPGA boa d, o con e he es analog signal in o digi al. A PLC-SCADA-based con ol sys em o a wa e s o age ank is discussed in [ 6 ]. I used an RSLOGIX 5000 PLC in i s design. The speed con ol o a h ee-phase induc ion mo o using a PLC has been implemen ed by [ 7 ]. The PLC main ains he speed o he induc ion mo o a he desi ed alue. An idea o de ec ing induc ion mo o aul s using FPGAs is discussed in [ 8 ]. I used a 16-bi se ial ou pu ADC o con e he acqui ed cu en signal in o a digi al signal. The design o a pa allelized mul i-PID con olle using a ield p og ammable ga e a ay (FPGA)-based mul ip ocesso is discussed in [ 9 ]. I used an enhanced PicoBlaze mic ocon olle (EPM). The design was es ed wi h ou PID con olle s ha an simul ane- ously. Howe e , his wo k did no discuss how his mul iple PID con olle handles analog signals. An example ci ed in he wo k does no equi e he con e sion o analog signals in o digi al. The e o e, i is no clea whe he his design can pe o m he concu en execu ion o mul iple PID con olle s when an analog signal is o be main ained a he desi ed se poin . Thus, he e iew indica es ha single o mul iple closed-loop con ol sys ems ha e been de eloped using a PLC, compu e , DSP, o FPGA, o a combina ion o hese pieces o equipmen . The FPGA has being iden i ied as a be e al e na i e ha can pe o m he unc ion o a p ocesso [ 10 ] in an imp o ed way. One such example is he design o he FPGA-based loa ing-poin p ocesso discussed in [ 11 ]. FPGAs can also be used in he implemen a ion o PID con olle s [ 12 , 13 ]. The design o an ul asonic local posi ioning sys em using an FPGA o obo applica ions is discussed in [ 14 ]. I used a PID con olle so ha he obo could ack he line accu a ely. Resea che s a e eage o ind an op imized solu ion o PLCs in e ms o FPGAs [ 15 ]. Resea che s ha e also s a ed o ealize PID con olle s using FPGAs, as discussed in [ 16 ]. This wo k p oposed a me hod in which mo e han one closed-loop con ol sys em will be concu en ly p ocessed by he dedica ed ha dwa e esou ces o he FPGA wi hou comp omising he scan ime o he PLC. 2. O e iew o Closed-Loop Con ol Sys em wi h PLC In he ea ly 1990s, esea che s de eloped a dedica ed ha dwa e con olle ha did no demand any so wa e. The ASIC design o a PI con olle is discussed in [ 17 ]. Realiza ion o a mul iple PID con olle using a low powe single chip has been discussed in [ 18 ]. Con en ionally, a closed-loop con ol sys em has a con olle , inal con ol elemen , and ansmi e . The con olle compa es he desi ed alue wi h he ansmi e ou pu and ac ua es he inal con ol elemen o main ain he p ocess a iable a he desi ed alue. The con olle employs a mic op ocesso /mic ocon olle [ 19 ] o ealize con olle algo i hms such as P/PI/PID. I has an inbuil ADC o con e he analog ou pu o he ansmi e signal in o digi al. A single closed-loop con ol sys em needs an ADC, a mic op ocesso as a con olle , and a DAC. This coun inc eases along wi h he numbe o closed-loop con ol sys ems. Howe e , a single mic op ocesso shall be de ined as a con olle . In a p ac ical scena io, all he ADCs and DACs a e de eloped as AIMs and AOMs, espec i ely. The p ocesso in he PLC is used o execu e he con ol algo i hm, as shown in Figu e 1. Senso s 2022,22, 4584 3 o 17 Senso s 2022, 22, x FOR PEER REVIEW 3 o 15 Figu e 1. O ganiza ion o closed-loop con ol sys em using a PLC. Bo h he AIM and he AOM mus ha e a p ocesso o ensu e p ope signal con e - sion. Thus, he AIM, AOM, and PLC ha e p ocesso s in hei a chi ec u e [20]. Because he p ocesso execu es only one ins uc ion a a ime, he PLC has o wai o he AIM o comple e i s ope a ion. The PID unc ion block in he LD is o de ed as las in he execu ion o a ladde diag am. Including PID unc ion blocks in he LD c ea es an unnecessa y delay in he execu ion o digi al signals. I he e is a de ice ha akes ca e o PID unc ion blocks, hen he bu den o he PLC can be g ea ly educed. This wo k has p oposed a solu ion o mul iple PID con olle s de eloped using an FPGA ha can be con igu ed as a mix u e o AIM, DIM, AOM, and DOM. The p esen con igu a ion o a PLC-based au oma ion sys em does no ha e he con igu a ion o AIM/AOM/DIM/DOM in a single module. 3. Design o Single and Mul iple PID Con olle s Sec ions 3.1. and 3.2. elabo a e he design o single and mul iple PID con olle s de- eloped using an FPGA. Sec ion 3.1.1 explains he design o an ADC ha ensu es concu - en con e sion o mo e han one analog signal in o digi al. As a whole, his chap e p o- ides a no el solu ion o he simul aneous p ocessing o all PID con olle s. 3.1. FPGA Design o PID Con olle A PID con olle helps o main ain he alue o a p ocess pa ame e a he desi ed alue. I equi es h ee pa ame e s, p opo ional gain, in eg al ime, and de i a i e ime, o be adjus ed o achie e be e pe o mance. In his wo k, Ve ilogHDL code has been de eloped o he PID con olle . I equi ed, he PID con olle can be easily changed in o a PI con olle by assigning he de i a i e ime as ze o in HDL (Ha dwa e Desc ip ion Language) code [21]. The s anda d equa ion o a PID con olle is gi en as: ()= ()+ () + ()  (1) In Equa ion (1), () is he e o signal, () is he con olle ou pu ,  is he p o- po ional gain,  is he in eg al ime, and  is he de i a i e ime. Because he equa ion mus be ealized by an FPGA, i is con e ed in o he o m o a di e ence equa ion [22,23], as men ioned in Equa ion (2). 󰇟󰇠= 󰇟−1 󰇠+ 󰇟󰇠+ 󰇟−1 󰇠+ 󰇟−2 󰇠 (2) whe e, = + +  Figu e 1. O ganiza ion o closed-loop con ol sys em using a PLC. Bo h he AIM and he AOM mus ha e a p ocesso o ensu e p ope signal con e sion. Thus, he AIM, AOM, and PLC ha e p ocesso s in hei a chi ec u e [ 20 ]. Because he p ocesso execu es only one ins uc ion a a ime, he PLC has o wai o he AIM o comple e i s ope a ion. The PID unc ion block in he LD is o de ed as las in he execu ion o a ladde diag am. Including PID unc ion blocks in he LD c ea es an unnecessa y delay in he execu ion o digi al signals. I he e is a de ice ha akes ca e o PID unc ion blocks, hen he bu den o he PLC can be g ea ly educed. This wo k has p oposed a solu ion o mul iple PID con olle s de eloped using an FPGA ha can be con igu ed as a mix u e o AIM, DIM, AOM, and DOM. The p esen con igu a ion o a PLC-based au oma ion sys em does no ha e he con igu a ion o AIM/AOM/DIM/DOM in a single module. 3. Design o Single and Mul iple PID Con olle s Sec ion 3.1. and Sec ion 3.2. elabo a e he design o single and mul iple PID con olle s de eloped using an FPGA. Sec ion 3.1.1 explains he design o an ADC ha ensu es concu en con e sion o mo e han one analog signal in o digi al. As a whole, his chap e p o ides a no el solu ion o he simul aneous p ocessing o all PID con olle s. 3.1. FPGA Design o PID Con olle A PID con olle helps o main ain he alue o a p ocess pa ame e a he desi ed alue. I equi es h ee pa ame e s, p opo ional gain, in eg al ime, and de i a i e ime, o be adjus ed o achie e be e pe o mance. In his wo k, Ve ilogHDL code has been de eloped o he PID con olle . I equi ed, he PID con olle can be easily changed in o a PI con olle by assigning he de i a i e ime as ze o in HDL (Ha dwa e Desc ip ion Language) code [21]. The s anda d equa ion o a PID con olle is gi en as: u( ) = kP e( ) + 1 TI Z 0 e( )d +TD de( ) d  (1) In Equa ion (1), e( ) is he e o signal, u( ) is he con olle ou pu , kP is he p opo - ional gain, TI is he in eg al ime, and TD is he de i a i e ime. Because he equa ion mus be ealized by an FPGA, i is con e ed in o he o m o a di e ence equa ion [ 22 , 23 ], as men ioned in Equa ion (2). u[k] = u[k−1]+k1e[k] + k2e[k−1]+k3e[k−2](2) Senso s 2022,22, 4584 4 o 17 whe e, k1=kp(1+ki+kd) k2=−kp(1+2kd) k3=kpkd Inpu s and ou pu s o and om he mul iple closed-loop con ol sys em a e mul iple. The execu ion becomes concu en when sepa a e ha dwa e is assigned o execu e Equa ion (2) o e e y inpu . Hence, mul iple closed-loop con ol sys ems designed using FPGAs can be isualized as eal mul iple inpu and mul iple ou pu sys ems. 3.1.1. Single Closed-Loop Con ol Sys em—P oposed In a closed-loop con ol sys em, inpu s o a PID con olle a e se o poin o he ansmi e ’s ou pu , whe ein he calcula ion o he con ol e o (di e ence o hese inpu s) is ealized in-side he con olle . The ansmi e ecei es inpu om a senso . An indus ial s anda d ansmi e gene a es ou pu in he ange o 0–5 V. The ou pu o he ansmi e is an analog signal. The in e ace ci cui ha comp ises a DAC, compa a o , and analog o digi al con e sion logic in he FPGA, as in Figu e 2, con e s he ansmi e ’s analog signal in o digi al. The wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC is p e e ed in many applica ions, as men ioned in [24]. Senso s 2022, 22, x FOR PEER REVIEW 4 o 15 =− −2  =  Inpu s and ou pu s o and om he mul iple closed-loop con ol sys em a e mul iple. The execu ion becomes concu en when sepa a e ha dwa e is assigned o execu e Equa- ion (2) o e e y inpu . Hence, mul iple closed-loop con ol sys ems designed using FPGAs can be isualized as eal mul iple inpu and mul iple ou pu sys ems. 3.1.1. Single Closed-Loop Con ol Sys em—P oposed In a closed-loop con ol sys em, inpu s o a PID con olle a e se o poin o he ans- mi e ’s ou pu . The ansmi e ecei es inpu om a senso . An indus ial s anda d ansmi e gene a es ou pu in he ange o 0–5 . The ou pu o he ansmi e is an analog signal. The in e ace ci cui ha comp ises a DAC, compa a o , and analog o dig- i al con e sion logic in he FPGA, as in Figu e 2, con e s he ansmi e ’s analog signal in o digi al. The wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC is p e e ed in many applica ions, as men ioned in [24] Figu e 2. FPGA design o single closed-loop con ol sys em. This wo k has p oposed a no el con e sion p ocess o analog signals in o digi al, which can be seen in Figu e 3. I was de eloped, simula ed, and e i ied using Mul isim [25]. Figu e 3. FPGA design o analog inpu module o a single channel. I unc ions on he wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC. The mos signi ican bi (MSB) o he SAR egis e will be se , and he emaining bi s will be in ese condi ion. A egis e in an FPGA is decla ed as a SAR egis e . The Figu e 2. FPGA design o single closed-loop con ol sys em. This wo k has p oposed a no el con e sion p ocess o analog signals in o digi- al, which can be seen in Figu e 3. I was de eloped, simula ed, and e i ied using Mul isim [25]. Senso s 2022,22, 4584 5 o 17 Senso s 2022, 22, x FOR PEER REVIEW 4 o 15 =− −2  =  Inpu s and ou pu s o and om he mul iple closed-loop con ol sys em a e mul iple. The execu ion becomes concu en when sepa a e ha dwa e is assigned o execu e Equa- ion (2) o e e y inpu . Hence, mul iple closed-loop con ol sys ems designed using FPGAs can be isualized as eal mul iple inpu and mul iple ou pu sys ems. 3.1.1. Single Closed-Loop Con ol Sys em—P oposed In a closed-loop con ol sys em, inpu s o a PID con olle a e se o poin o he ans- mi e ’s ou pu . The ansmi e ecei es inpu om a senso . An indus ial s anda d ansmi e gene a es ou pu in he ange o 0–5 . The ou pu o he ansmi e is an analog signal. The in e ace ci cui ha comp ises a DAC, compa a o , and analog o dig- i al con e sion logic in he FPGA, as in Figu e 2, con e s he ansmi e ’s analog signal in o digi al. The wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC is p e e ed in many applica ions, as men ioned in [24] Figu e 2. FPGA design o single closed-loop con ol sys em. This wo k has p oposed a no el con e sion p ocess o analog signals in o digi al, which can be seen in Figu e 3. I was de eloped, simula ed, and e i ied using Mul isim [25]. Figu e 3. FPGA design o analog inpu module o a single channel. I unc ions on he wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC. The mos signi ican bi (MSB) o he SAR egis e will be se , and he emaining bi s will be in ese condi ion. A egis e in an FPGA is decla ed as a SAR egis e . The Figu e 3. FPGA design o analog inpu module o a single channel. I unc ions on he wo king p inciple o successi e app oxima ion egis e (SAR) ype ADC. The mos signi ican bi (MSB) o he SAR egis e will be se , and he emaining bi s will be in ese condi ion. A egis e in an FPGA is decla ed as a SAR egis e . The DAC con e s his SAR con en in o analog, and a compa a o compa es i wi h he analog signal ha is o be con e ed in o digi al. Because he DAC ou pu is connec ed o he non-in e ing inpu o he compa a o , he MSB will be e ained as such, p o ided he DAC ou pu is g ea e han he analog inpu signal. O he wise, i will be ese . Se ing o ese ing he SAR con en will be comple ed by he FPGA. The FPGA hen se s he consecu i e MSB bi leading owa ds he leas signi ican bi (LSB) and epea s he abo e p ocedu e. Because all he bi s ha e o be e i ied in his manne , an 8-bi ADC will equi e eigh clock pulses. The equi alen digi al ou pu o he analog signal can be iden i ied by eading he con en o he SAR egis e a he eigh h clock pulse. I can also be ead by a compu e h ough RS232 se ial da a communica ion. This helps o es ablish a da a acquisi ion sys em (DAS). The con e sion ime, τ c, o he p oposed design is compu ed based on he se ling ime o DAC0808 ( τ s), he delay ime o he compa a o ( τ cd), and he delay ime o he FPGA logic ( τ d). The digi al ou pu o he ADC in his wo k is 8-bi . Hence, τ cis calcula ed om he ollowing Equa ion (3): τc=8×(τs+τcd +τ d)(3) In gene al, o an nbi ADC, Equa ion (2) is modi ied o: τc=n×(τs+τcd +τ d)(4) whe e nindica es he numbe o clock cycles equi ed o comple e he con e sion. Thus, he gene a ed digi al ou pu is s o ed in he FPGA egis e . The PID con ol logic shown in Figu e 2accep s his egis e con en as i s p ocess a iable. The e o e, e( ) is gene a ed by sub ac ing he se poin om he alue o he p ocess a iable. PID con ol logic gene a es u( ) and o wa ds i o he inal con ol elemen (FCE). Usually, he FCE accep s analog signals. Hence, he digi al ou pu o he PID con olle is con e ed in o analog using DAC. Real- ime implemen a ion o a closed-loop con ol sys em has used DAC0808, IC741, and XC3S200 FPGA chips. The compa a o was designed using IC741. The clock signal applied o he Xilinx XC3S200 FPGA chip was 50 MHz. 3.1.2. Mul iple Closed-Loop Con ol Sys em—P oposed Con en ionally, he mic op ocesso p ocesses mul iple closed-loop con ol sys ems. Howe e , i sequen ially execu es all he closed-loop sys ems, as men ioned in Figu e 4. Senso s 2022,22, 4584 6 o 17 Senso s 2022, 22, x FOR PEER REVIEW 5 o 15 DAC con e s his SAR con en in o analog, and a compa a o compa es i wi h he analog signal ha is o be con e ed in o digi al. Because he DAC ou pu is connec ed o he non- in e ing inpu o he compa a o , he MSB will be e ained as such, p o ided he DAC ou pu is g ea e han he analog inpu signal. O he wise, i will be ese . Se ing o ese ing he SAR con en will be comple ed by he FPGA. The FPGA hen se s he consecu i e MSB bi leading owa ds he leas signi ican bi (LSB) and epea s he abo e p ocedu e. Because all he bi s ha e o be e i ied in his manne , an 8-bi ADC will equi e eigh clock pulses. The equi alen digi al ou pu o he analog signal can be iden i ied by eading he con en o he SAR egis e a he eigh h clock pulse. I can also be ead by a compu e h ough RS232 se ial da a communica ion. This helps o es ablish a da a acquisi ion sys- em (DAS). Th econ e sion ime, τc, o he p oposed design is compu ed based on he se ling ime o DAC0808 (τs), he delay ime o he compa a o (τcd), and he delay ime o he FPGA logic (τ d). The digi al ou pu o he ADC in his wo k is 8-bi . Hence, τc is calcu- la ed om he ollowing Equa ion (3):  = 8 ×  +  +  d (3) In gene al, o an  bi ADC, Equa ion (2) is modi ied o:  =  ×  +  +  d (4) whe e  indica es he numbe o clock cycles equi ed o comple e he con e sion. Thus, he gene a ed digi al ou pu is s o ed in he FPGA egis e . The PID con ol logic shown in Figu e 2 accep s his egis e con en as i s p ocess a iable. The e o e, e( ) is gene a ed by sub ac ing he se poin om he alue o he p ocess a iable. PID con ol logic gene a es u( ) and o wa ds i o he inal con ol elemen (FCE). Usually, he FCE accep s analog signals. Hence, he digi al ou pu o he PID con olle is con e ed in o analog using DAC. Real- ime implemen a ion o a closed-loop con ol sys em has used DAC0808, IC741, and XC3S200 FPGA chips. The compa a o was designed using IC741. The clock signal applied o he Xilinx XC3S200 FPGA chip was 50MHz. 3.1.2. Mul iple Closed-Loop Con ol Sys em—P oposed Con en ionally, he mic op ocesso p ocesses mul iple closed-loop con ol sys ems. Howe e , i sequen ially execu es all he closed-loop sys ems, as men ioned in Figu e 4. Figu e 4. Mul iple PID con olle equa ion o mic op ocesso . One o he majo d awbacks o his sys em is ha he p ocesso will be able o execu e i s  PID con olle equa ion a  μs, assuming he ime equi ed o execu e one PID con olle is 1 μ. The p oposed sys em was used o de eloped a mul iple PID con olle by which all PID con olle equa ions will be execu ed simul aneously, as in Figu e 5. The Figu e 4. Mul iple PID con olle equa ion o mic op ocesso . One o he majo d awbacks o his sys em is ha he p ocesso will be able o execu e i s n h PID con olle equa ion a n h µs , assuming he ime equi ed o execu e one PID con olle is 1 µs . The p oposed sys em was used o de eloped a mul iple PID con olle by which all PID con olle equa ions will be execu ed simul aneously, as in Figu e 5. The pa allel p ocessing capaci y o an FPGA discussed in [ 26 ] indica es he possibili y o ealizing mul iple PID con olle s using FPGAs. Senso s 2022, 22, x FOR PEER REVIEW 6 o 15 pa allel p ocessing capaci y o an FPGA discussed in [26] indica es he possibili y o eal- izing mul iple PID con olle s using FPGAs. Figu e 5. Mul iple PID con olle equa ion o FPGA. This is achie ed by assigning sepa a e PID con olle logic and hence sepa a e FPGA ha dwa e esou ces o each closed-loop con ol sys em. Assigning ha dwa e o each PID con olle does no demand any no el y. A pe ec mul iple closed-loop con ol sys em can be es ablished when all he PID con olle s can simul aneously access i s desi ed alue in he o m o a digi al signal. This wo k has esol ed he issue by in eg a ing he ADC con e sion p ocess wi h he PID con olle , as in Figu e 6. By compa ing Figu e 6 wi h Figu e 2, one can unde s and ha a mul iple PID closed-loop con ol sys em is es ablished wi h a compa a o , wo DACs, and PID con olle logic o e e y closed-loop con ol sys- em. Figu e 6. Closed-loop con ol sys em o wo analog signals. Figu e 6 shows he design ha can concu en ly main ain wo p ocess pa ame e s a hei desi ed alues. The concep o AIMs e ol ed when a se o DAC0808 and a compa - a o is included o e e y closed-loop con ol sys em. Simila ly, he concep o AOMs e ol ed when a DAC0808 is included in e e y closed-loop con ol sys em. In he same way, indi idual PID con ol logic is adop ed in FPGAs o e e y closed-loop con ol sys- em. Thus, he FPGA plays he ole o he PLC. I should be no ed ha Figu e 6 is e ol ed om Figu es 2 and 3. Thus, he no el y o his wo k is iden i ied in Figu e 6. I has an AIM, an AOM, and a PID con olle . The maximum numbe o closed-loop con ol sys- ems ha can be ealized in an FPGA is based on i s ha dwa e esou ces. This wo k has de eloped Ve ilogHDL code o eigh closed-loop con ol sys ems, which ha e used app oxima ely 55% o he FPGA ha dwa e esou ces. Figu e 5. Mul iple PID con olle equa ion o FPGA. This is achie ed by assigning sepa a e PID con olle logic and hence sepa a e FPGA ha dwa e esou ces o each closed-loop con ol sys em. Assigning ha dwa e o each PID con olle does no demand any no el y. A pe ec mul iple closed-loop con ol sys em can be es ablished when all he PID con olle s can simul aneously access i s desi ed alue in he o m o a digi al signal. This wo k has esol ed he issue by in eg a ing he ADC con e sion p ocess wi h he PID con olle , as in Figu e 6. By compa ing Figu e 6 wi h Figu e 2, one can unde s and ha a mul iple PID closed-loop con ol sys em is es ablished wi h a compa a o , wo DACs, and PID con olle logic o e e y closed-loop con ol sys em. Senso s 2022,22, 4584 7 o 17 Senso s 2022, 22, x FOR PEER REVIEW 6 o 15 pa allel p ocessing capaci y o an FPGA discussed in [26] indica es he possibili y o eal- izing mul iple PID con olle s using FPGAs. Figu e 5. Mul iple PID con olle equa ion o FPGA. This is achie ed by assigning sepa a e PID con olle logic and hence sepa a e FPGA ha dwa e esou ces o each closed-loop con ol sys em. Assigning ha dwa e o each PID con olle does no demand any no el y. A pe ec mul iple closed-loop con ol sys em can be es ablished when all he PID con olle s can simul aneously access i s desi ed alue in he o m o a digi al signal. This wo k has esol ed he issue by in eg a ing he ADC con e sion p ocess wi h he PID con olle , as in Figu e 6. By compa ing Figu e 6 wi h Figu e 2, one can unde s and ha a mul iple PID closed-loop con ol sys em is es ablished wi h a compa a o , wo DACs, and PID con olle logic o e e y closed-loop con ol sys- em. Figu e 6. Closed-loop con ol sys em o wo analog signals. Figu e 6 shows he design ha can concu en ly main ain wo p ocess pa ame e s a hei desi ed alues. The concep o AIMs e ol ed when a se o DAC0808 and a compa - a o is included o e e y closed-loop con ol sys em. Simila ly, he concep o AOMs e ol ed when a DAC0808 is included in e e y closed-loop con ol sys em. In he same way, indi idual PID con ol logic is adop ed in FPGAs o e e y closed-loop con ol sys- em. Thus, he FPGA plays he ole o he PLC. I should be no ed ha Figu e 6 is e ol ed om Figu es 2 and 3. Thus, he no el y o his wo k is iden i ied in Figu e 6. I has an AIM, an AOM, and a PID con olle . The maximum numbe o closed-loop con ol sys- ems ha can be ealized in an FPGA is based on i s ha dwa e esou ces. This wo k has de eloped Ve ilogHDL code o eigh closed-loop con ol sys ems, which ha e used app oxima ely 55% o he FPGA ha dwa e esou ces. Figu e 6. Closed-loop con ol sys em o wo analog signals. Figu e 6shows he design ha can concu en ly main ain wo p ocess pa ame e s a hei desi ed alues. The concep o AIMs e ol ed when a se o DAC0808 and a compa a o is included o e e y closed-loop con ol sys em. Simila ly, he concep o AOMs e ol ed when a DAC0808 is included in e e y closed-loop con ol sys em. In he same way, indi idual PID con ol logic is adop ed in FPGAs o e e y closed-loop con ol sys em. Thus, he FPGA plays he ole o he PLC. I should be no ed ha Figu e 6is e ol ed om Figu es 2and 3. Thus, he no el y o his wo k is iden i ied in Figu e 6. I has an AIM, an AOM, and a PID con olle . The maximum numbe o closed-loop con ol sys ems ha can be ealized in an FPGA is based on i s ha dwa e esou ces. This wo k has de eloped Ve ilogHDL code o eigh closed-loop con ol sys ems, which ha e used app oxima ely 55% o he FPGA ha dwa e esou ces. 3.2. Case S udy o Mul iple PID Con olle —Le el and P essu e P ocess S a ion The design o mul iple closed-loop con ol sys ems was es ed and e i ied o wo closed-loop con ol sys ems. The design depic ed in Figu e 5was used o main ain he desi ed alue o le el and p essu e o he le el and p essu e p ocess s a ions, espec i ely. 3.2.1. Le el P ocess S a ion The Labo a o y se -up o he le el and p essu e p ocess s a ion used o es he closed- loop con ol sys em is shown in Figu e 7. A pump loca ed below he s o age ank pumps wa e om he ese oi ank. I has wo ou le s. One is connec ed o a s o age ank and he o he o he ese oi . Senso s 2022,22, 4584 8 o 17 Senso s 2022, 22, x FOR PEER REVIEW 7 o 15 3.2. Case S udy o Mul iple PID Con olle —Le el and P essu e P ocess S a ion The design o mul iple closed-loop con ol sys ems was es ed and e i ied o wo closed-loop con ol sys ems. The design depic ed in Figu e 5 was used o main ain he desi ed alue o le el and p essu e o he le el and p essu e p ocess s a ions, espec i ely. 3.2.1. Le el P ocess S a ion The Labo a o y se -up o he le el and p essu e p ocess s a ion used o es he closed-loop con ol sys em is shown in Figu e 7. A pump loca ed below he s o age ank pumps wa e om he ese oi ank. I has wo ou le s. One is connec ed o a s o age ank and he o he o he ese oi . Figu e 7. Le el p ocess s a ion. The con ol al e is ins alled in be ween he pipeline o he pump and he s o age ank. A capaci ance p obe senso is used o sense he wa e le el. I s ou pu is con e ed in o 4 o 20 mA cu en signal by a le el ansmi e . The connec ion be ween he ans- mi e and he non-in e ing e minal o he compa a o is shown in Figu e 8. An indus- ial s anda d ansmi e gene a es an ou pu o 4 o 20 mA cu en signal (Suni a Sinha [27]). A esis o is connec ed in se ies wi h he 24 V DC powe supply o con e he 4 o 20 mA cu en signal in o a 1 V o 5 V ol age signal. An equi alen esis o ha adop s he con e sion o cu en signal in o ol age was iden i ied as 240 Ω. The ou pu o he FPGA is connec ed o he I/P con e e . Figu e 8. Con e sion o he ou pu cu en o he ansmi e in o ol age. A esis o connec ed in se ies wi h he DAC and I/P con e e ensu es ha he cu en lowing in he loop is in he ange o 4 o 20 mA. DAC ou pu is se as 5 V. The esis o alue is adjus ed and ound o be 130 Ω when he cu en low in he ci cui is 20 mA [28]. 3.2.2. P essu e P ocess S a ion The labo a o y se up o he p essu e p ocess s a ion in Figu e 7 has wo s o age anks o s o e comp essed ai . I is possible o s o e comp essed ai , ei he in bo h he anks o only in one ank, by ope a ing he hand al e in e linked be ween he wo anks. The maximum p essu e ha can be s o ed in he ank is 2 Kg/cm. As discussed in he le el Figu e 7. Le el p ocess s a ion. The con ol al e is ins alled in be ween he pipeline o he pump and he s o age ank. A capaci ance p obe senso is used o sense he wa e le el. I s ou pu is con e ed in o 4 o 20 mA cu en signal by a le el ansmi e . The connec ion be ween he ansmi e and he non-in e ing e minal o he compa a o is shown in Figu e 8. An indus ial s anda d ansmi e gene a es an ou pu o 4 o 20 mA cu en signal (Suni a Sinha [ 27 ]). A esis o is connec ed in se ies wi h he 24 V DC powe supply o con e he 4 o 20 mA cu en signal in o a 1 V o 5 V ol age signal. An equi alen esis o ha adop s he con e sion o cu en signal in o ol age was iden i ied as 240 Ω . The ou pu o he FPGA is connec ed o he I/P con e e . Senso s 2022, 22, x FOR PEER REVIEW 7 o 15 3.2. Case S udy o Mul iple PID Con olle —Le el and P essu e P ocess S a ion The design o mul iple closed-loop con ol sys ems was es ed and e i ied o wo closed-loop con ol sys ems. The design depic ed in Figu e 5 was used o main ain he desi ed alue o le el and p essu e o he le el and p essu e p ocess s a ions, espec i ely. 3.2.1. Le el P ocess S a ion The Labo a o y se -up o he le el and p essu e p ocess s a ion used o es he closed-loop con ol sys em is shown in Figu e 7. A pump loca ed below he s o age ank pumps wa e om he ese oi ank. I has wo ou le s. One is connec ed o a s o age ank and he o he o he ese oi . Figu e 7. Le el p ocess s a ion. The con ol al e is ins alled in be ween he pipeline o he pump and he s o age ank. A capaci ance p obe senso is used o sense he wa e le el. I s ou pu is con e ed in o 4 o 20 mA cu en signal by a le el ansmi e . The connec ion be ween he ans- mi e and he non-in e ing e minal o he compa a o is shown in Figu e 8. An indus- ial s anda d ansmi e gene a es an ou pu o 4 o 20 mA cu en signal (Suni a Sinha [27]). A esis o is connec ed in se ies wi h he 24 V DC powe supply o con e he 4 o 20 mA cu en signal in o a 1 V o 5 V ol age signal. An equi alen esis o ha adop s he con e sion o cu en signal in o ol age was iden i ied as 240 Ω. The ou pu o he FPGA is connec ed o he I/P con e e . Figu e 8. Con e sion o he ou pu cu en o he ansmi e in o ol age. A esis o connec ed in se ies wi h he DAC and I/P con e e ensu es ha he cu en lowing in he loop is in he ange o 4 o 20 mA. DAC ou pu is se as 5 V. The esis o alue is adjus ed and ound o be 130 Ω when he cu en low in he ci cui is 20 mA [28]. 3.2.2. P essu e P ocess S a ion The labo a o y se up o he p essu e p ocess s a ion in Figu e 7 has wo s o age anks o s o e comp essed ai . I is possible o s o e comp essed ai , ei he in bo h he anks o only in one ank, by ope a ing he hand al e in e linked be ween he wo anks. The maximum p essu e ha can be s o ed in he ank is 2 Kg/cm. As discussed in he le el Figu e 8. Con e sion o he ou pu cu en o he ansmi e in o ol age. A esis o connec ed in se ies wi h he DAC and I/P con e e ensu es ha he cu en lowing in he loop is in he ange o 4 o 20 mA. DAC ou pu is se as 5 V. The esis o alue is adjus ed and ound o be 130 Ω when he cu en low in he ci cui is 20 mA [ 28 ]. 3.2.2. P essu e P ocess S a ion The labo a o y se up o he p essu e p ocess s a ion in Figu e 7has wo s o age anks o s o e comp essed ai . I is possible o s o e comp essed ai , ei he in bo h he anks o only in one ank, by ope a ing he hand al e in e linked be ween he wo anks. The maximum p essu e ha can be s o ed in he ank is 2 Kg/cm2 . As discussed in he le el p ocess s a ion, esis o alues connec ed o he p essu e ansmi e and I/P con e e we e iden i ied as 240 Ωand 130 Ω, espec i ely. Senso s 2022,22, 4584 9 o 17 3.2.3. FPGA In e acing Boa d An FPGA in e ace boa d is designed o p ocess wo p ocess pa ame e s: le el and p essu e. Each pa ame e equi es wo DACs and one compa a o . One DAC and a compa a o a e used o con e he analog signal o he ansmi e ou pu in o digi al. A second DAC is used o ac i a e he I/P con e e o which he ou pu is ini ia ed om he FPGA as a con olle ou pu . Hence, he in e ace boa d has ou DAC0808 chips and wo compa a o s, which we e designed using IC741, as shown in Figu e 9. Senso s 2022, 22, x FOR PEER REVIEW 8 o 15 p ocess s a ion, esis o alues connec ed o he p essu e ansmi e and I/P con e e we e iden i ied as 240 Ω and 130 Ω, espec i ely. 3.2.3. FPGA In e acing Boa d An FPGA in e ace boa d is designed o p ocess wo p ocess pa ame e s: le el and p essu e. Each pa ame e equi es wo DACs and one compa a o . One DAC and a com- pa a o a e used o con e he analog signal o he ansmi e ou pu in o digi al. A sec- ond DAC is used o ac i a e he I/P con e e o which he ou pu is ini ia ed om he FPGA as a con olle ou pu . Hence, he in e ace boa d has ou DAC0808 chips and wo compa a o s, which we e designed using IC741, as shown in Figu e 9. Figu e 9. In e ace boa d o ADC con e sion, DAC ou pu o I/P con e e . DAC1 and DAC2 a e used o he p essu e p ocess s a ion, and DAC3 and DAC4 a e used o he le el p ocess s a ion. The ou pu s o compa a o s and inpu s o he DACs a e in eg a ed in o a single 50-pin connec o so ha he o he end o he connec o can be connec ed o he FPGA boa d (XC3S200). This boa d has one 40 pin connec o , h ee 25 pin connec o s, and one uni e sal asynch onous ecei e ansmi e (UART) connec o . Addi ionally, i has eigh swi ches and eigh ligh emi ing diodes (LEDs). 3.3. Ve ilogHDL Code—Acquisi ion, Con ol, UART The con ibu ion o FPGAs in he design o closed-loop con ol sys ems is c ucial. They a e used o con e an analog signal o ansmi e ou pu in o digi al, ini ia e con ol ac ions based on he ansmi e ou pu , and ans e necessa y da a o he compu e o moni o ing. 3.3.1. Ve ilogHDL Code—Single PID Con olle , UART FPGA implemen a ion o any design can be ca ied ou by ep esen ing a p oblem in HDL code. This is e i ied o i s p ope unc ionali y du ing simula ion. Thus, e i ied code is con e ed in o a bi ile a e syn hesis o FPGA implemen a ion. This wo k has used Ve ilogHDL code o de elop he en i e logic o he FPGA implemen a ion o mul i- ple closed-loop con ol sys ems. The essen ial elemen s o Ve ilogHDL code o a PID con olle is lis ed below. The main module  in okes he modules  and . The  module is esponsible o con e ing he analog signal in o a digi al signal based on he logic discussed in Sec ion 3.1.1. This digi al ou pu is applied as an inpu o he PID con- olle . Hence, he logic o gene a e con olle ou pu has also been included in his mod- ule. Thus, gene a ed con olle ou pu (  ) and digi al ou pu (), combined in o , a e ansmi ed o he compu e by execu ing he mod- ule . This pe o ms he unc ion o UART da a ansmission. Clock pulse ime, Figu e 9. In e ace boa d o ADC con e sion, DAC ou pu o I/P con e e . DAC1 and DAC2 a e used o he p essu e p ocess s a ion, and DAC3 and DAC4 a e used o he le el p ocess s a ion. The ou pu s o compa a o s and inpu s o he DACs a e in eg a ed in o a single 50-pin connec o so ha he o he end o he connec o can be connec ed o he FPGA boa d (XC3S200). This boa d has one 40 pin connec o , h ee 25 pin connec o s, and one uni e sal asynch onous ecei e ansmi e (UART) connec o . Addi ionally, i has eigh swi ches and eigh ligh emi ing diodes (LEDs). 3.3. Ve ilogHDL Code—Acquisi ion, Con ol, UART The con ibu ion o FPGAs in he design o closed-loop con ol sys ems is c ucial. They a e used o con e an analog signal o ansmi e ou pu in o digi al, ini ia e con ol ac ions based on he ansmi e ou pu , and ans e necessa y da a o he compu e o moni o ing. 3.3.1. Ve ilogHDL Code—Single PID Con olle , UART FPGA implemen a ion o any design can be ca ied ou by ep esen ing a p oblem in HDL code. This is e i ied o i s p ope unc ionali y du ing simula ion. Thus, e i ied code is con e ed in o a bi ile a e syn hesis o FPGA implemen a ion. This wo k has used Ve ilogHDL code o de elop he en i e logic o he FPGA implemen a ion o mul iple closed-loop con ol sys ems. The essen ial elemen s o Ve ilogHDL code o a PID con olle is lis ed below. The main module con olle in okes he modules con e and ansmi . The con e module is esponsible o con e ing he analog signal in o a digi al signal based on he logic discussed in Sec ion 3.1.1. This digi al ou pu is applied as an inpu o he PID con olle . Hence, he logic o gene a e con olle ou pu has also been included in his module. Thus, gene a ed con olle ou pu ( ou pu ocon olle ) and digi al ou pu ( da a odac ), combined in o da a , a e ansmi ed o he compu e by execu ing he module ansmi . This pe o ms he unc ion o UART da a ansmission. Clock pulse ime, clk , o he FPGA is educed o ‘clkdi ided’, which is he equi ed clock pulse o ADC con e sion. Simila ly, FPGA speed is Senso s 2022,22, 4584 16 o 17 highe execu ion speed when hese componen s a e eplaced by high-speed de ices. This p oposed design can be used independen ly o in combina ion wi h PLCs. The o al numbe o PID con olle s equi ed in an applica ion decides he numbe o FPGAs used in he design o mul iple PID con olle s. When he design is o be used wi h a PLC, he concep o ne wo king mus be included in he FPGA. This is also applicable when he e is a si ua ion in which he con en o one FPGA is o be sha ed wi h o he FPGAs. Hence, he au ho s ha e aimed o de elop mul iple PID con olle s ha suppo ne wo k communica ions in he u u e. Au ho Con ibu ions: Concep ualiza ion, G.D. and M.M.; da a cu a ion, G.D. and S.T.S.; o mal analysis, G.D. and S.T.S.; in es iga ion S.T.S.; me hodology, M.M.; so wa e, G.D. and M.M.; supe i- sion, M.M.; w i ing—o iginal d a , G.D. and S.T.S.; w i ing— e iew and edi ing, M.M. All au ho s ha e ead and ag eed o he published e sion o he manusc ip . Funding: This esea ch ecei ed no ex e nal unding. Ins i u ional Re iew Boa d S a emen : No applicable. In o med Consen S a emen : No applicable. Da a A ailabili y S a emen : No applicable. Con lic s o In e es : The au ho s decla e no con lic o in e es . Re e ences 1. De Cane e, J.F.; del Saz-O ozco, P.; Gonzalez, S.; Ga cia-Mo al, I. Dual composi ion con ol and so es ima ion o a pilo dis illa ion column using a neu ogene ic design. Compu . Chem. Eng. 2012,40, 157–170. [C ossRe ] 2. Salem, A.; Abu-Siada, A.; Islam, S. Imp o ed condi ion moni o ing echnique o wind u bine gea box and sha s ess de ec ion. IET Sci. Meas. Technol. 2017,11, 431–437. [C ossRe ] 3. Ca los, G.G.; Ju enal, R.R.; Geo gina, M.V.; Edga , R.A.; Jo ge, M.S.; Rica do, L.R. A PC-based a chi ec u e o pa ame e analysis o ec o -con olled induc ion mo o d i e. Compu . Elec . Eng. 2011,37, 858–868. 4. Bayindi , R.; Ce ince iz, Y. A wa e pumping con ol sys em wi h a p og ammable logic con olle (PLC) and indus ial wi eless modules o indus ial plan s—An expe imen al se up. ISA T ans. 2011,50, 321–328. [C ossRe ] [PubMed] 5. Jaiswal, S.; Ballal, M.S. FDST-based PQ e en de ec ion and ene gy me e ing implemen a ion on FPGA-in- he-loop and NI- LabVIEW. IET Sci. Meas. Technol. 2017,11, 453–463. [C ossRe ] 6. Chak abo y, K.; Choudhu y, M.; Das, S.; Paul, S. De elopmen o PLC-SCADA based con ol s a egy o wa e s o age in a ank o a semi-au oma ed plan . J. Ins um. 2020,15, T04007. [C ossRe ] 7. Ioannides, M. Design and Implemen a ion o PLC-Based Moni o ing Con ol Sys em o Induc ion Mo o . IEEE T ans. Ene gy Con e s. 2004,19, 469–476. [C ossRe ] 8. Liza aga-Mo ales, R.A.; Rod iguez-Dona e, C.; Cabal-Yepez, E.; Lopez-Rami ez, M.; Ledesma-Ca illo, L.M.; Fe ucho-Al a ez, E.R. No el FPGA-based Me hodology o Ea ly B oken Ro o Ba De ec ion and Classi ica ion Th ough Homogenei y Es ima ion. IEEE T ans. Ins um. Meas. 2017,66, 1760–1769. [C ossRe ] 9. Youness, H.; Moness, M.; Khaled, M. MPSoCs and Mul ico e Mic ocon olle s o Embedded PID Con ol: A De ailed S udy. IEEE T ans. Ind. In o m. 2014,10, 2122–2134. [C ossRe ] 10. Sapona a, S.; Ne i, B. Rada Senso Signal Acquisi ion and Mul idimensional FFT P ocessing o Su eillance Applica ions in T anspo Sys ems. IEEE T ans. Ins um. Meas. 2017,66, 604–615. [C ossRe ] 11. Dong, J.; Wang, T.; Li, B.; Liu, Z.; Yu, Z. An FPGA-based low-cos VLIW loa ing-poin p ocesso o CNC applica ions. Mic op ocess. Mic osys . 2017,50, 14–25. [C ossRe ] 12. Sen hilna han, A.; Palani el, P. A new app oach o commu a ion o que ipple educ ion o FPGA based b ushless DC mo o wi h ou going phase cu en con ol. Mic op ocess. Mic osys . 2020,75, 103043. [C ossRe ] 13. Roy, A.; Sha ma, L.; Chak abo y, I.; Panja, S.; Ojha, V.N.; De, S. An FPGA based all-in-one unc ion gene a o , lock-in ampli ie and au o- elockable PID sys em. J. Ins um. 2019,14, P05012. [C ossRe ] 14. He nandez, A.; Ga cia, E.; Gualda, D.; Villadangos, J.M.; Nombela, F.; U ena, J. FPGA-Based A chi ec u e o Managing Ul asonic Beacons in a Local Posi ioning Sys em. IEEE T ans. Ins um. Meas. 2017,66, 1954–1964. [C ossRe ] 15. Tasca, L.C.; de F ei as, E.P.; Wagne , F.R. Enhanced a chi ec u e o p og ammable logic con olle s a ge ing pe o mance imp o emen s. Mic op ocess. Mic osys . 2018,61, 306–315. [C ossRe ] 16. Aboelaze, M.; Sheha a, M.G. Implemen a ion o mul iple PID con olle s on FPGA. In P oceedings o he 2015 IEEE In e na ional Con e ence on Elec onics, Ci cui s, and Sys ems (ICECS), Cai o, Egyp , 6–9 Decembe 2015; pp. 446–449. [C ossRe ] 17. G ou , I.A.; Bu ge, S.E.; Do ey, A.P. Design and es ing o a PI con olle ASIC. Mic op ocess. Mic osys . 1995 ,19, 15–22. [C ossRe ] Senso s 2022,22, 4584 17 o 17 18. Bhanda i, A.S.; Chaudhu i, A.; Roy, S.; Negi, S.; Sha ad, M. Single chip sel - unable N-inpu N-ou pu PID con ol sys em wi h in eg a ed analog on -end o minia u e obo ics. In P oceedings o he 2017 IEEE 14 h In e na ional Con e ence on Ne wo king, Sensing and Con ol (ICNSC), Calab ia, I aly, 16–18 May 2017; pp. 109–114. [C ossRe ] 19. Neelamegam, P.; Kuma a el, S.; Raghuna han, R. Mic ocon olle Based Dis ibu ed Moni o ing Sys em o F esh Wa e Fish Aquacul u e. Ins um. Sci. Technol. 2008,36, 515–524. [C ossRe ] 20. Dhanabalan, G.; Tamil Sel i, S. Design o pa allel con e sion mul ichannel analog o digi al con e e o scan ime educ ion o p og ammable logic con olle using FPGA. Compu . S and. In e aces 2015,39, 12–21. [C ossRe ] 21. Milano ic, M.; T un ic, M.; Sliba , P.; Dolina , D. Recon igu able digi al con olle o a buck con e e based on FPGA. Mic oelec- on. Reliab. 2006,47, 150–154. [C ossRe ] 22. Chan, Y.F.; Moallem, M.; Wang, W. Design and Implemen a ion o Modula FPGA-Based PID Con olle s. IEEE T ans. Ind. Elec on. 2007,54, 1898–1906. [C ossRe ] 23. As om, K.J.; Hagglund, T. The u u e o PID con ol. Con ol. Eng. P ac . 2011,9, 1163–1175. [C ossRe ] 24. Chen, D.G.; Tang, F.; Law, M.-K.; Zhong, X.; Be mak, A. A 64 J/s ep 9-bi SAR ADC A ay wi h Fo wa d E o Co ec ion and Mixed-Signal CDS o CMOS Image Senso s. IEEE T ans. Ci cui s Sys . I Regul. Pap. 2014,61, 3085–3093. [C ossRe ] 25. Dhanabalan, G.; Mu ugan, T. FPGA design o SAR ype ADC based analog inpu module o indus ial applica ions. In Ad ances in VLSI and Embedded Sys ems, Lec u e No es in Elec ical Enginee ing; Pa el, Z., Gup a, S., Kuma , Y.B.N., Eds.; Sp inge : Singapo e, 2020; Volume 676. 26. Alabdo, A.; Pé ez, J.; Ga cia, G.J.; Poma es, J.; To es, F. FPGA-based a chi ec u e o di ec isual con ol obo ic sys ems. Mecha onics 2016,39, 204–216. [C ossRe ] 27. Sinha, S.; Kachhap, R.V.; Mandal, N. Design and de elopmen o a capaci ance-based wi eless p essu e ansmi e . IET Sci. Meas. Technol. 2018,12, 858–864. [C ossRe ] 28. Da a, J.; Chowdhu i, S.; Be a, J.; Sa ka , G. Remo e moni o ing o di e en elec ical pa ame e s o mul i-machine sys em using PC. Measu emen 2012,45, 118–125. [C ossRe ] 29. Ionel, R.; Vasiu, G.; Mischie, S. GPRS based da a acquisi ion and analysis sys em wi h mobile phone con ol. Measu emen 2012 , 45, 1462–1470. [C ossRe ] 30. Riege , R.; Huang, Y.-R. A Cus om-Design Da a Logge Co e o Physiological Signal Reco ding. IEEE T ans. Ins um. Meas. 2010 , 60, 532–538. [C ossRe ] 31. Con olLogix I/O Speci ica ions. 2019. A ailable online: h ps://li e a u e. ockwellau oma ion.com/idc/g oups/li e a u e/ documen s/ d/1756- d002_-en-e.pd (accessed on 1 July 2019). 32. Es ima ed Execu ion Time and Memo y Use o Logix5000 Con olle Ins uc ions. 2019. A ailable online: h ps://li e a u e. ockwellau oma ion.com/idc/g oups/li e a u e/documen s/ m/logix- m002_-en-p.pd (accessed on 1 July 2019). 33. Se ies 90 TM -30/20/Mic o PLC CPU Ins uc ion Se . 2002. A ailable online: h p://www.cim ecau oma ion.com/documen s/ echsuppo /Se ies9030/Manuals/g k-0467lSe ies90-30-20-Mic oPLCCPUIns uc ionSe Re e enceManual.pd (accessed on 1 July 2019).