OTRA Based Piece-Wise Linear VTC Generators and Their Application in High-Frequency Sinusoid Generation

THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER OTRA Based Piece-Wise Linea VTC Gene a o s and Thei Applica ion in High-F equency Sinusoid Gene a ion Si ish ORUGANTI, Ya in GILHOTRA, Nee a PANDEY, Rajeshwa i PANDEY Depa men o Elec onics and Communica ion Enginee ing, Delhi Technological Uni e si y, Main Bawana Road, Shahbad Daula pu Village, Rohini, 110042 New Delhi, India si isho ugan[email p o ec ed], y[email p o ec ed],[email p o ec ed],[email p o ec ed] DOI: 10.15598/aeee. 15i5.2426 Abs ac . This pape p oposes me hods o gene a e a ious ypes o Linea Vol age T ans e Cu es (VTC) using Ope a ional T ans-Resis ance Ampli ie (OTRA) as he ac i e block. I u he goes on o p opose me h- ods o mul iplex a ious indi idual Linea VTCs o ob- ain any o m o Piece-Wise Linea Vol age T ans e Cu es (PWL), which ind many applica ions in he wo ld o ci cui y. One pa icula applica ion has been highligh ed, i.e. gene a ion o High-F equency Sinu- soids. Simula ions o he Ci cui s p oposed ia Cadence Vi uoso, using Towe Jazz’s 180 nm Technology Node ha e been epo ed, which sa is y he aim behind i s de- elopmen . Keywo ds High- equency, linea , OTRA, PWL, sinusoid, VTC. 1. In oduc ion Vol age ans e cu es a e essen ial in any o m o ana- log signal p ocessing. They p o ide an app op ia e ou - pu wa e o m based on he need. Wa e shaping inds many uses in elec onics, om ol age limi a ion, o signal p ocessing, and wa e o m gene a ion. Sinusoidal signals a e an in eg al pa o many elec onic appa a- us, om communica ion sys ems, o powe con e sion, con ol sys ems, da a p ocessing, and ins umen s [1] and [2]. The usual choice o ac i e block o such implemen- a ions is he Ope a ional Ampli ie (Op-Amp). How- e e , his comes wi h many disad an ages. Op-Amp based ci cui s a e limi ed by hei low slew a e, and low bandwid h o ope a ion, which makes hem unde- si able o high- equency and high-speed ope a ions. Cu en -mode p ocessing is a leading choice o oday’s enginee s, which gi es us many ad an ages like high slew a e. As such, i is mo e linea , mo e dynamic, and as e in ope a ion as de ailed in [3]. This has made cu en -mode ac i e blocks inc easingly popula . The OTRA block used in his wo k o e s a much highe pole (co ne equency) han he gene ic Op-Amp, and a highe bandwid h o ope a ion. Many applica ions o he OTRA ha e eme ged in ecen imes, which in- dica e he use ulness o OTRA [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19] and [20]. Se e al PWL VTC and sinusoidal oscilla o s using cu en -mode ac i e blocks exis in li e a u e. Cu en Limi e s based on he ac i e block CDTA, and hei p ac icali y a e de ailed in [21]. Me hods o syn hesise PWL VTCs ha e been discussed in [22], which can be modi ied o ou use. CDTA [23] and [24], and OTRA [25], [26] and [27] based oscilla o s show he applica- ion o cu en -mode ac i e blocks in gene a ion o si- nusoids. Howe e , hey use ha monic me hods, which usually ail in high equencies. Also, he solu ion in [24] has cu en inpu s, making i imp ac ical. None o he ci ed wo ks use cu en -mode ac i e blocks in PWL VTC gene a ion o p oduce a sinusoid, which shows he gap in esea ch, and he mo i a ion behind his wo k. In his wo k, we p opose me hods o gene a e any desi ed PWL VTC using OTRA ac i e block, which gi es us bene i s o cu en -mode p ocessing [3]. One speci ic use case o ol age con olled high- equency sinusoid gene a ion is de ailed, whe e ol age-mode ac- i e blocks and ha monic me hods ail. All he ci cui s p oposed ha e been simula ed success ully, and he e- sul s a e included. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 806 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER 2. The OTRA The Ope a ional T ans-Resis ance Ampli ie (OTRA) is a h ee- e minal de ice as shown in Fig. 1. + _Rm Ip In Vo Fig. 1: OTRA block diag am. The OTRA ampli ies he di e ence o he cu en s Ip and Inand he ou pu is he ol age Voin acco dance o po cha ac e is ics as exp essed by Eq. (1). The Rmis known as he ans- esis ance gain, and i s alue app oaches in ini y o an ideal OTRA, which in u n o ces he inpu cu en s o be equal. Fo ideal ope - a ion, Vpand Vnshould be ze o. Also, Voshould no depend on he cu en d awn om he ou pu e minal, i.e. Io.   Vp Vn Vo  =  0 0 0 0 0 0 Rm−Rm0  ·  Ip In Io  .(1) The ou pu o an ideal OTRA eaches posi i e o nega i e sa u a ion le els (VDD o VSS) i used in an open loop con igu a ion as he Rmis in ini e. Thus, o linea applica ions he OTRA mus be used in a nega i e eedback con igu a ion. The OTRA used in his wo k [28] is shown in Fig. 2. The alues o an- sis o W/L a ios, VB1and IBmay be e e enced om [28]. The OTRA gi es us a Gain-Bandwid h P od- uc o 600 GHz Ω, which makes i sui able o High- F equency Applica ions. VDD VSS Vo Ip In M1M2M3 M4M5M6M7 M8M9M10 M11 M12 M13 M14 VB1 Fig. 2: OTRA CMOS ci cui [14]. 3. P oposed VTC Gene a o s Posi i e and nega i e slope VTC gene a o s based on OTRA a e p oposed in his sec ion. The schema ic o he posi i e gene a o is shown in Fig. 3, whe e he OTRA is used in he non-in e ing ampli ie con igu a ion [28]. The ou pu ol age Vou is ela ed o he inpu ol age Vin by Eq. (2). Vou =R Rin Vin +R Rb Vbias.(2) The i s e m in he RHS o Eq. (2) p o ides he desi ed slope, and he second e m in oduces he e- qui ed DC o se . Figu e 4 depic s he nega i e slope VTC gene a o . He e, he OTRA is used in in e ing ampli ie con ig- u a ion [29]. The ou pu ol age Vou is ela ed o he inpu ol age Vin by Eq. (3). Vou =−R Rin Vin +R Rb Vbias.(3) Vbias OTRA 1 Vin Rin Rb R + - Fig. 3: Schema ic o posi i e slope linea VTC gene a o . OTRA 1 Rb Rin R + - Vin Vbias Fig. 4: Schema ic o nega i e slope linea VTC gene a o . 4. P oposed PWL VTC Gene a o s The indi idual VTC gene a o s as p oposed in Sec. 3. can be mul iplexed o gene a e a complex piece-wise linea ol age ans e cu e (PWL VTC). To swi ch c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 807 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER τTG =CL 2   1 Kp(|VDD +VX|−|VTp|)2    −VSS − Kn(VX−VTn)3−(VX−VTn −VSS)3 3Kp(VDD −VX−VTp)2    + +1 Kn(VX−VSS −VTn)2    −VDD − Kp(Vx− |VTp|)3−(|VDD +VX| − VTp)3 3Kn(VX−VSS −VTn)2     . (4) be ween app op ia e VTCs a b eakpoin s, compa a- o s need o be used, which compa e he inpu ol age wi h he b eakpoin ol age. The compa a o s eed a digi al logic ci cui , which needs o be syn hesised o each use case. The logic ga es will ope a e be ween VDD and VSS . The digi al logic should be designed such ha one and exac ly one channel o he mul i- plexe is ac i e o each and e e y piece o he PWL VTC, i.e. o all alues o inpu ol age, exac ly one o (S0, S0’), (S1, S1’), o (S2, S2’) a e ac i e, and he es inac i e. The digi al logic con ols he ou pu o he analog mul iplexe o med by ansmission. The mul iplexe le s he ou pu om he desi ed VTC Gene a o pass based on he digi al con ol logic. S anda d CMOS design echniques may be used o design he ga es [30]. Figu e 5 and Fig. 6 show he implemen a ion o he analog mul iplexe and he OTRA based compa a o espec i ely. Inpu 1 Inpu 0 Inpu 2 S0 S0' S1 S1' S2 S2' Ou pu Fig. 5: Analog mul iplexe made wi h ansmission ga es. OTRA 1 + - Vin Vc Vo Fig. 6: OTRA wo king as a compa a o in open-loop con igu- a ion. Using he blocks o Fig. 3, Fig. 4, Fig. 5 and Fig. 6, and he p ocedu e ou lined abo e, any desi ed PWL VTC can be gene a ed. A simple use case o his has been illus a ed in Sec. 5. , which uses a PWL VTC o con e a iangula wa e in o a sinusoid. 5. Applica ion: High-F equency Sinusoid Gene a ion A iangula wa e, when passed h ough an app op i- a e PWL VTC, can p oduce an app oxima e sinusoid, as de ailed in [1]. This concep has been used o il- lus a e he use ulness o he PWL VTC gene a o s p oposed in his wo k. The iangula wa e is gene a ed om a ol age- con olled ing oscilla o (dema ca ed by dashed line in Fig. 7) as de ailed in [30], wi h ansmission ga es o con ol he delays, connec ed o an in eg a o ci cui based on OTRA [29]. Figu e 7 shows he iangula wa e gene a o used. All he ansis o s in he Vol - age Con olled Ring Oscilla o ha e he W/L a io as 1µ/0.5µ. Assuming he ipping ol age o an in e e is (VDD +Vss)/2, we ge he equa ion o he p opaga- ion delay h ough he ansmission ga e as de ailed in Eq. (4). Whe e he CLis he inpu capaci ance o in- e e , and VX he DC con ol ol age. Equa ion (5) gi es he delay o one in e e , as explained in [30]. τin =τphl +τplh 2.(5) Thus, he equency o he oscilla o can be gi en by Eq. (6). =1 10(τTG +τin ).(6) OTRA 1 is a compa a o which compa es his ec - angula wa e o g ound, and ou pu s a sha pe ec an- gula wa e. OTRA 2 is a lossy in eg a o [29]. I in eg a es he ec angula wa e in o a iangula wa e. OTRA 3 is used o boos he ou pu o OTRA 2 o a ail o ail c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 808 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER alue. This ou pu s a iangula wa e, which is passed on o he PWL VTC gene a o o ou pu a sinusoid. Rii Ri OTRA 2 Rc Rc OTRA 1 Rbi Rb OTRA 3 + - + - + - Ci VDD VSS +Vx -Vx Con ol Vol age Vol age Con olled Ring Oscilla o T iangula Wa e Fig. 7: T iangula wa e gene a o . Rb2 Rb3 OTRA 4 OTRA 1 OTRA 2 OTRA 3 Ri2 Ri1 Rc Rc R 2 OTRA 5 Rc Rc R 1 R 3 OTRA 6 Roi Ro Digi al Logic Analog Mul iplexe Sinusoid Ou pu +0.8V -0.8V +1V -1V T iangula Wa e Ri3 Fig. 8: PWL VTC gene a o o iangula o sinusoid con e - sion. The PWL VTC gene a o o iangula o sinusoidal con e sion is as shown in Fig. 8 OTRAs 1, 2 and 3 a e used o gene a e he indi idual PWLs as ollows: •OTRA 1 gene a es a VTC wi h slope =−1and Vbias = 0 V. •OTRA 2 gene a es a VTC wi h slope =−0.4and Vbias = +0.6V. •OTRA 3 gene a es a VTC wi h slope =−0.4and Vbias =−0.6V. OTRAs 4 and 5 a e connec ed as compa a o s wi h e e ence ol ages +1 V and −1V espec i ely. OTRA 6 is he ou pu s age ha con e s he PWL VTC ou pu o a ail o ail sinusoid. The ou pu o an OTRA based ampli ie nea he ails is na u ally slewed, and his can be used o ou ad an age o ob ain a cu a u e in he ansien wa e o m nea he ails. 6. Simula ion Resul s The unc ional e i ica ion o p oposed ci cui s is ca - ied ou on Cadence Vi uoso ADE using Towe Jazz’s 180 nm echnology node. VDD is aken as +2 V and VSS is aken o be −2V globally o simula ions. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -2 -1 0 1 2 Ou pu Vol age (V) Simula ed VTC Theo e ical VTC (a) Posi i e VTC wi hou bias. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -4 -2 0 2 4 Ou pu Vol age (V) Simula ed VTC Theo e ical VTC (b) Posi i e VTC wi h bias. Fig. 9: Posi i e VTC. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -2 -1 0 1 2 Ou pu Vol age (V) Simula ed VTC Theo e ical VTC (a) Nega i e VTC wi hou Bias. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -0.5 0 0.5 1 Ou pu Vol age (V) Simula ed VTC Theo e ical VTC (b) Nega i e VTC wi h bias. Fig. 10: Nega i e VTC. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 809 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 10-5 -2 Vol age (V) (ii) 400mV 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 10-5 -2 0 2 Vol age (V) (iii) 600mV 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 10-5 -2 0 2 Vol age (V) (i ) 800mV 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s) 10-5 -2 0 2 Vol age (V) ( ) 1V 0 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 10-5 -2 0 2 Vol age (V) (i) 200mV 0 0 0 0 Fig. 11: F equency a ia ion o iangula wa e ou pu o Vbias alues as (i) 200 mV, (ii) 400 mV, (iii) 600 mV, (i ) 800 mV and ( ) 1 V. The simula ed and heo e ical ou pu o he posi- i e VTC gene a o wi hou and wi h bias ha e been epo ed in Fig. 9(a) and Fig. 9(b) espec i ely. Sim- ila ou pu s o nega i e VTC gene a o s a e placed in Fig. 10(a) and Fig. 10(b). Fo hese simula ions, he alues o Rband Rin we e aken o be 10 kΩ, Vbias and R we e a ied acco dingly. The ope a ion o he p oposed VTC gene a o s is es ed agains p ocess co ne a ia ions, o ypical, as - as , as -slow, slow- as and slow-slow co ne s. Simula ion esul s a e shown in Fig. 12, which p o e ha he ou pu s a e insensi i e o p ocess a ia ions. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -0.5 0 0.5 1 Ou pu Vol age (V) Typical Slow-Slow Slow-Fas Fas -Slow Fas -Fas Fig. 12: P ocess co ne a ia ion. Fu he , o es he e ec o empe a u e a ia ions, simula ions we e ca ied ou by a ying he empe a- u e o he simula ion en i onmen , om −20 ◦C o +60 ◦C, in s eps o 20 ◦C. The simula ed ou pu is shown in Fig. 13. The plo shows ha he ci cui s a e esilien o any o ms o empe a u e a ia ions. T ansien esponse o he iangula wa e gene a o is shown in Fig. 11, which also shows a ia ion in e- quency wi h espec o con ol ol age VX. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -0.5 0 0.5 1 Ou pu Vol age (V) -20 0 20 40 60 Fig. 13: Tempe a u e a ia ion. To e i y he unc ionali y o he sinusoid gene a o , he di e en VTCs chosen a e as ollows: •OTRA 1 is gene a ing a VTC wi h slope =−1 and Vbias = 0 V. The alues o Ri1and R 1a e bo h aken o be 100 KΩ. •OTRA 2 is gene a ing a VTC wi h slope =−0.4 and Vbias = +0.6V. The alues o Ri2and R 2 a e aken o be 100 KΩand 40 KΩ espec i ely. •OTRA 3 is gene a ing a VTC wi h slope =−0.4 and Vbias =−0.6V. The alues o Ri3and R 3 a e aken o be 100 KΩand 40 KΩ espec i ely. Rcwas aken o be 10 KΩ, and s anda d CMOS logic ga es we e used o he digi al logic, as de ailed in [30]. Theo e ically, by Eq. (6), he equency o he VCO a VX= 180 mV was ound o be 1.13 MHz. On simu- la ion, we ound i was equal o 1MHz. I can hus be calcula ed ha he equency de ia ion be ween heo- e ical and expe imen al equencies is 13 % o he case implemen ed. The expe imen al alue o equency is lowe han heo e ical as he heo y does no accoun c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 810 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER o delays caused by he pa asi ic esis ances and ca- paci ances, which inc ease he ime, and hus educe he equency. The h ee indi idual VTCs a e shown in Fig. 14, and he ansien esponse ou pu o he PWL VTC Gene a o is shown in Fig. 15. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Inpu Vol age (V) -2 -1 0 1 2 Ou pu Vol age (V) PWL VTC DC Inpu VTC 1 VTC 2 VTC 3 Fig. 14: The indi idual VTCs and combined PWL VTC. 0 0.2 0.4 0.6 0.8 1 Time (s) 10-5 -2 -1 0 1 2 Vol age (V) PWL VTC T ansien Ou pu Fig. 15: T ansien esponse o he PWL VTC gene a o . In he ou pu s age, Roi and Ro we e aken o be 10 KΩand 25 KΩ espec i ely. The ansien ou pu o he ou pu s age is shown in Fig. 16, in compa ison wi h a s anda d sine wa e. The ob ained wa e o m sligh ly de ia es om he ideal wa e o m, as we ha e used only h ee VTC sec ions. Howe e , on inc eas- ing he numbe o VTC sec ions, his de ia ion can be educed. 1.02 1.04 1.06 1.08 1.1 1.12 1.14 Time (s) 10-5 -2 -1 0 1 2 Vol age (V) Fig. 16: T ansien esponse o he ou pu s age. Figu e 17 shows he equency spec um o he ou - pu in compa ison wi h ha o an ac ual sine wa e o 1 MHz equency. As can be clea ly obse ed, he e is a good le el o accu acy achie ed in deli e ing a sinu- soid ou pu . To al Ha monic Dis o ion was calcula ed o he gene a ed sinusoid, up o i e ha monics, and he alue was ound o be 9.3776 %. The THD can be u he imp o ed by inc easing he numbe o VTC sec ions. 104105106 -60 -40 -20 0 20 Magni ude (dB) (V) Ac ual Sine Wa e Gene a ed Sinusoid Fig. 17: F equency spec um o he sinusoid gene a ed. Mon e-Ca lo Analysis was done o es he pe o - mance o he ci cui agains componen alue a ia- ions. The esis o s we e a ied wi h 10 % ole ance om he nominal alue. The es was pe o med o 500 samples. I was ound ha o a <5 % misma ch wi h espec o he nominal wa e o m, o e 83 %o he samples passed he Mon e-Ca lo Simula ion, which illus a es he low sensi i i y o passi e componen pa- ame e a ia ions ha ou ci cui exhibi s. Mon e- Ca lo Analysis was also pe o med on he MOSFET Wid h pa ame e (W) wi h 5 % ole ance, <5 % mis- ma ch pass ma k, and 500 samples yielded a pass o o e 70 %o he samples. As on changing he W, he equency o he VCO changes, he wa e o m is no a ma ch o he nominal alue, and shows a ia ion. Also, he OTRA Gain is also changed, hus causing he misma ch. Analyses o es ing he beha io o he ci cui agains pa asi ic elemen s we e pe o med. The in- pu capaci ance o he In e e was 83 F, and o he NOR Ga e was 104 F. The Ou pu Capaci ance o he OTRA was ound o be 3.04 pF, which is much la ge han ha o he Digi al Logic, and hence, he OTRA will domina e in he pa asi ic e ec s. I can be no ed om [28] ha o he low gain case as used in his wo k, he OTRA will unc ion well o equencies much highe han he ones a which we a e gene a ing he sinusoid. Hence, he e ec o pa asi ics is negligible in ou wo k. 7. Conclusion In his wo k, posi i e and nega i e slope linea VTC gene a o s using OTRA ha e been p oposed, which can be designed o gene a e any linea cu e as pe he de- sign ules men ioned in Eq. (2) and Eq. (3). They can be mul iplexed o gene a e any desi ed PWL VTC as de ailed in Sec. 4. As a pa icula applica ion, c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 811 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER h ee di e en VTCs ha e been mul iplexed o gene - a e a PWL VTC ha con e s a iangula wa e in o a sinusoid. This is use ul in gene a ing high- equency sinusoids whe e ha monic oscilla o me hods and o he ol age mode ac i e block based ci cui s ail. Simula ion esul s on Cadence Vi uoso using Tow- e Jazz’s 180 nm echnology node ha e been epo ed o all he ci cui s p oposed. The VTC gene a o s we e es ed o p ocess co ne and empe a u e a ia- ions, and we e ound o be ex emely esilien o hei changes. The equency spec um o he gene a ed si- nusoid is ound o be e y close o ha o an o iginal sine wa e. Acknowledgmen The au ho s wish o hank M . Ni ish, G adua e S u- den , Dep . o Elec ical Enginee ing and Compu e Science, Uni e si y o Michigan, Ann A bo , USA, and M . T. R. Aashish, Resea ch Schola , Depa men o Elec ical Enginee ing, Indian Ins i u e o Technology, Delhi, o hei suppo du ing simula ions. Re e ences [1] SEDRA, A. S. and K. C. SMITH. Mic oelec onic Ci cui s. 7 h ed. New Yo k: Ox o d Uni e si y P ess, 2015. ISBN 978–0–19–933913–6. [2] RAZAVI, B. Fundamen als o Mic oelec onics. 2nd ed. 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Digi al In eg a ed Ci cui s: A Design Pe spec i e. 1s ed. Saddle Ri e : P en ice Hall, 1996. ISBN 978-0-131-78609-7. Abou Au ho s Si ish ORUGANTI was bo n in Visakhapa nam, Andh a P adesh, India. He is cu en ly an unde g ad- ua e s uden , pu suing his Bachelo o Technology in Elec onics and Communica ion Enginee ing om Delhi Technological Uni e si y. His esea ch in e es s include Analog and Mixed-Signal VLSI Design and Low-Powe VLSI Design. Ya in GILHOTRA was bo n in Ambala, Ha yana, India. He is cu en ly an unde g adua e s uden , c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 813 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER pu suing his Bachelo o Technology in Elec onics and Communica ion Enginee ing om Delhi Tech- nological Uni e si y. His esea ch in e es s include Low-Powe VLSI Design, Mixed-Signal VLSI Design, Analog Design, Neu al De ec o s and B ain Machine In e aces. Nee a PANDEY is cu en ly a P o esso in Depa men o Elec onics and Communica ion En- ginee ing, Delhi Technological Uni e si y. She did he M.E. in Mic oelec onics om Bi la Ins i u e o Technology and Sciences, Pilani and Ph.D. om Gu u Gobind Singh Ind ap as ha Uni e si y Delhi. She is a li e membe o ISTE, and Senio Membe o IEEE, USA. He esea ch in e es s a e in Analog and Digi al VLSI Design. Rajeshwa i PANDEY is cu en ly a P o esso in Depa men o Elec onics and Communica ion Enginee ing, Delhi Technological Uni e si y. She did he M.E in Elec onics and Con ol om BITS, Pilani, Rajas han, India and Ph.D. om Facul y o Technol- ogy, Delhi Uni e si y, India. She is a li e membe o IETE, ISTE and membe o IEEE, and IEEE WIE o o e 12 yea s. He esea ch in e es s include Analog In eg a ed Ci cui s, and Mic oelec onics. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 814