Theory and original design of resistive-inductive network high-pass negative group delay integrated circuit in 130-nm CMOS technology

Recei ed Feb ua y 21, 2022, accep ed Ma ch 3, 2022, da e o publica ion Ma ch 8, 2022, da e o cu en e sion Ma ch 15, 2022. Digi al Objec Iden i ie 10.1109/ACCESS.2022.3157381 Theo y and O iginal Design o Resis i e-Induc i e Ne wo k High-Pass Nega i e G oup Delay In eg a ed Ci cui in 130-nm CMOS Technology MATHIEU GUERIN 1,2, (Membe , IEEE), WENCESLAS RAHAJANDRAIBE 1,2, (Membe , IEEE), GLAUCO FONTGALLAND 3, (Senio Membe , IEEE), HUGERLES S. SILVA 4,5, (Membe , IEEE), GEORGE CHAN 6, (Senio Membe , IEEE), FAYU WAN 7, (Membe , IEEE), PREETI THAKUR 8, ATUL THAKUR 8, JAROSLAV FRNDA 9,10, (Senio Membe , IEEE), AND BLAISE RAVELO 7, (Membe , IEEE) 1CNRS, Aix-Ma seille Uni e si y, 13007 Ma seille, F ance 2IM2NP UMR7334, Uni e si y o Toulon, 83130 Toulon, F ance 3Applied Elec omagne ic and Mic owa e Labo a o y, Fede al Uni e si y o Campina G ande, Campina G ande 58429, B azil 4Depa amen o de Ele ónica, Telecomunicações e In o má ica, Ins i u o de Telecomunicações, Uni e sidade de A ei o, Campus Uni e si á io de San iago, 3810-193 A ei o, Po ugal 5Depa men o Elec ical Enginee ing, Uni e si y o B asília, B asília 70910-900, B azil 6ASM Paci ic Technology L d., Hong Kong 7School o Elec onic and In o ma ion Enginee ing, Nanjing Uni e si y o In o ma ion Science and Technology, Nanjing 210044, China 8Depa men o Science Enginee ing and Technology, Ami y Uni e si y Ha yana, Gu gaon 122413, India 9Depa men o Quan i a i e Me hods and Economic In o ma ics, Facul y o Ope a ion and Economics o T anspo and Communica ions, Uni e si y o Zilina, 010 26 Žilina, Slo akia 10Depa men o Telecommunica ions, Facul y o Elec ical Enginee ing and Compu e Science, VŠB–Technical Uni e si y o Os a a, 708 00 Os a a, Czech Republic Co esponding au ho : Blaise Ra elo (blaise. a [email p o ec ed]) This wo k was suppo ed in pa by he NSFC unde G an 61971230; in pa by he Jiangsu Specially Appoin ed P o esso P og am and Six Majo Talen s Summi o Jiangsu P o ince unde G an 2019-DZXX-022; in pa by he S a up Founda ion o In oducing Talen o he Nanjing Uni e si y o In o ma ion Science and Technology (NUIST); in pa by he Fundaçao pa a a Ciencia e Tecnologia (FCT)/Minis é io da Ciência, Tecnologia e Ensino Supe io (MCTES) h ough na ional unds and, when applicable, co- unded by EU Funds unde P ojec UIDB/50008/2020-UIDP/50008/2020; and in pa by he Minis y o Educa ion, You h and Spo s o he Czech Republic conduc ed by he VSB—Technical Uni e si y o Os a a, Czechia, unde G an SP2021/25 and G an SP2022/5. ABSTRACT This pape de elops an o iginal design me hod o high-pass (HP) nega i e g oup delay (NGD) in eg a ed ci cui (IC). The conside ed HP-NGD IC is based on a passi e opology which is essen ially composed o esis o -induc o (RL) ne wo k. The pape p esen s he i s ime ha an un amilia HP- opology is designed in minia u ized ci cui implemen ed in 130-nm CMOS echnology. The heo y o un amilia HP-NGD opology based on he ol age ans e unc ion (VTF) analysis is elabo a ed. The design equa ions wi h syn hesis o mulas o he esis o and induc o a e es ablished. The HP-NGD IC CMOS design me hodology is in oduced. The easibili y o he minia u e NGD IC implemen a ion is app o ed by design ule check (DRC) and layou e sus schema ic (LVS) app oaches. The HP-NGD passi e IC is designed in 130-nm CMOS echnology. The HP-NGD opology is cons i u ed by RL-ne wo k based on CMOS high Ohmic unsalicided N +poly esis o and symme ical high cu en spi al induc o . Then, he schema ic and layou simula ions a e p esen ed. The alidi y o he 130-nm CMOS HP-NGD design is e i ied by he in es iga ion o 225 µm×215 µm chip wo di e en minia u e ci cui p oo s-o -concep (POC). The HP-NGD beha io is alida ed by compa ison be ween he calcula ed, and schema ic and pos -layou simula ions o he HP-NGD POCs ca ied ou by a comme cial ool. As expec ed, he g oup delay and VTF magni ude diag ams a e in e y good co ela ion. HP-NGD op imal alue, NGD cu -o equency and a enua ion, o abou (−31 ps, 141 MHz, −3 dB) and (−47 ps, 204 MHz, −5 dB) a e ob ained om he minia u e POCs. INDEX TERMS 130-nm CMOS echnology, design me hod, nega i e g oup delay (NGD), high-pass (HP) NGD unc ion, HP-NGD heo y, in eg a ed ci cui (IC) design, syn hesis equa ion, RL-ne wo k passi e opology, minia u e ci cui . The associa e edi o coo dina ing he e iew o his manusc ip and app o ing i o publica ion was Sai-Weng Sin . I. INTRODUCTION The mode n communica ion sys em e olu ion depends un- damen ally on he esea ch p og ess in e m o elec onic VOLUME 10, 2022 This wo k is licensed unde a C ea i e Commons A ibu ion 4.0 License. Fo mo e in o ma ion, see h ps://c ea i ecommons.o g/licenses/by/4.0/ 27147 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology unc ion design. Among he exis ing elec onic unc ion, he nega i e g oup delay (NGD) is he less amilia o mos o enginee s. The e o e, academic esea ch on NGD ci cui enginee ing is necessa y. A. OVERVIEW ON NGD CIRCUIT APPLICATION IN ELECTRONIC ENGINEERING Recen s udies epo po en ial applica ions o un amilia nega i e g oup delay (NGD) ci cui s o he imp o emen o pe o mance o di e se elec onic and communica ion de ices [1], [2]. Among he NGD po en ial applica ions, an inno a i e design me hod o an enna sys em o mul iband wi eless applica ions [2] was de eloped. An inno a i e syn- hesis me hod o RF and mic owa e phase shi e s ope a ing independen ly o he equency was in oduced [3], [4]. No el design o uncon en ional high Q se ies nega i e capaci o as non-Fos e componen s was also p esen ed in [5], [6]. The mos na u al applica ions o NGD ci cui s a e he delay equaliza ion o me ely he delay cancella ion in he elec onic sys ems [7], [8]. P omising imp o emen he a ea o elec onic communica ion enginee ing is pa icula ly expec ed wi h he NGD equaliza ion echnique. Fo example, i enables o co ec and o educe he undesi able e ec s o signal dis o ion [7], [8]. Fu he mo e, he NGD equaliza ion echnique allows o cancel ou as he delays induced by elec onic in e connec s [9], [10]. Mo eo e , we can inse NGD ci cui s in cascaded ups eam o downs eam o educe he g oup delay (GD) induced by elec onic communica ion sys ems [11], [12]. The di e si y o po en ial applica ions no ably in he a ea o elec onics and communica ion enginee ing cons i u es he main mo i a ion ac o o pu sue he esea ch wo k on he NGD enginee ing. B. STATE OF THE ART ON NGD CIRCUIT ENGINEERING Ne e heless, because o i s coun e in ui i e p ope y, so a , ew elec onic design and ab ica ion enginee s a e amilia o he NGD ci cui designing. Fo his eason, u he academic and mo e didac ical esea ch mus be de eloped o he non-specialis enginee s o open wo ld widely he NGD enginee ing. The NGD unc ion was ini ially expe imen ed wi h op ical sys em ope a ing wi h nega i e g oup eloci y (NGV) [13], [14]. Then, he exis ence o he NGD unc ion was an a ac i e opic o some cu ious RF and mic owa e design esea che s. I was ound ha he nega i e e ac- i e index (NRI) me ama e ials a e suscep ible o ope a e wi h NGD e ec [15]–[17]. Some ema kable mic os ip mic owa e passi e ci cui s wi h le -handed me ama e ial s uc u es we e designed and expe imen ed in he mic owa e equency ange [15]–[20]. The NRI me ama e ials based NRI ci cui s we e ini ially implemen ed wi h pe iodical passi e cells [16], [17]. To o e come o such echnical bo leneck, deepe design s udy o lumped ci cui s was pe o med based on he equi alen esonan ci cui app oach. The opology o spli ing esona o based mic os ip s uc u e [18] was iden i ied as one o he mos elemen a y NGD cells. Howe e , i was emphasized ha he me ama e ial based NGD passi e ci cui s [15]–[18] a e ei he signi ican ly lossy o implemen ed wi h la ge size p in ed ci cui boa ds (PCBs). Then, mo e complex mic owa e unc ion was inno a i ely imagined wi h unable me ama e ial esona o using a ac o diodes [15]. Ano he a ian o me ama e ial NGD ci cui wi h esis i e lossy le -handed ansmission lines (TLs) was p oposed [20]. To o e come he challenge in e m o size educ ion, NGD compac ci cui designs based on TL elemen s we e aised las decade [21]–[23]. Despi e he p og ess o he mic owa e NGD ci cui design me hods and iden i ied passi e ci cui opologies, he e is a lack o unde s anding abou he basic physical meaning o he NGD unc ion. C. NGD CIRCUIT TYPE CLASSIFICATION To answe o such a cu ious ques ion, an inno a i e peda- gogical heo y enabling o classi y he di e en ca ego ies o NGD opologies was ini ia ed [24]. This undamen al NGD ci cui heo y was inspi ed om he simili ude wi h he il e heo y [24]. In di e en wi h he il e , he NGD ci cui classi- ica ion depends on he g oup delay (GD) diag am. The NGD unc ion class can be easily unde s ood wi h he equency band whe e he GD is nega i e. Fo example, he class o low- pass (HP) NGD unc ion was iden i ied [25], [26]. Howe e , because he magni ude beha io o HP-NGD ci cui , some con usions maybe aised by elec onics design enginee s. Some cu ious ema ks maybe s a ed on he con usion be ween he HP-NGD unc ion and high-pass (HP) il e . To cla i y he di e ence be ween hese wo elec onic unc ions in he p esen pape , we s udy he design o HP-NGD ci cui . D. NOVELTY OF THE PAPER The main o iginali y o he esea ch wo k is ocused on he minia u iza ion o he HP-NGD ci cui based on he esis i e-induc i e (RL) passi e ne wo k. In he bes o he au ho s knowledge, despi e he de elopmen o in eg a ed ci cui (IC) mic oelec onic design [27]–[31], no esea ch wo k is a ailable in he li e a u e on he HP-NGD ci cui . A lo o s udy was conduc ed on he CMOS design o elec onic de ices as equency syn hesize [27], wi eless anscei e [29], induc o s and ans o me s [30] and ac i e induc o s [31]. The p esen pape de elops, he i s ime, he design s udy o minia u e HP-NGD IC in 130-nm CMOS echnology. E. OUTLINE OF THE PAPER The p esen esea ch wo k is o ganized in i e main sec ions desc ibed as ollows: •Sec ion II in oduces he heo y o un amilia HP-NGD ci cui . The conside ed passi e opology is based on RL-ne wo k. The heo e ical s udy is based on he ol age ans e unc ion (VTF) elabo a ion. •The syn hesis o mulas allowing o de e mine he esis- o and induc o componen s in unc ion o he desi ed HP-NGD speci ica ions a e es ablished in Sec ion III. 27148 VOLUME 10, 2022 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology FIGURE 1. Scheme o he HP-NGD opology unde s udy. •Sec ion IV de elops he design me hod o he HP-NGD IC in 130-nm CMOS echnology. The design me hod- ology including he schema ic and layou implemen a- ion in he CADENCE-VIRTUOUSO en i onmen is desc ibed. •Sec ion V discusses he alida ion o he HP-NGD heo y and he 130-nm CMOS design in he equency domain. The easibili y s udy is based on he compa ison o esul s om he heo e ical model, schema ic ci cui simula ion and pos -layou simula ion (PLS). •Finally, he pape conclusion is d awn in Sec ion VI. II. THEORETICAL STUDY OF THE RL-NETWORK BASED HP-NGD PASSIVE TOPOLOGY The p esen sec ion in oduces he HP-NGD passi e ci cui heo y including he associa ed basic speci ica ions. A e he VTF conside a ion, he design and syn hesis equa ions a e de eloped in he ollowing subsec ions. A. TOPOLOGICAL DESCRIPTION Fig. 1 depic s he opology o HP-NGD passi e cell unde s udy. The p oposed opology is an L-shape passi e cell. I is composed by a se ies esis o Raassocia ed o pa allel RL-ne wo k cons i u ed by esis o Rand induc o L. The ini ial s ep o he VTF calcula ion is based on he Laplace a iable s=jω, in unc ion o angula equency ωand complex numbe j2= −1. Simila o all classical RL-ne wo k based elec onic ci cui , he HP-NGD analysis is elabo a ed by conside ing he inpu and ou pu ol ages Vin(s) and Vou (s), espec i ely. By de ini ion, he VTF model is ob ained by: N(s)=Vou (s) Vin(s).(1) The associa ed ansmi ance is a complex numbe N(jω) which can be exp essed as: N(jω)= <e[N(jω)]+j=m[N(jω)](2) wi h he eal pa exp essed by <e[N(jω)]and he imagina y exp essed by =m[N(jω)]. The associa ed magni ude is ma hema ically gi en by: N(ω)=|N(jω)|=q<e[N(jω)]2+=m[N(jω)]2.(3) The phase is de ined by: ϕ(ω)=a c an=m[N(jω)] <e[N(jω)].(4) Then, he less amilia pa ame e o he HP-NGD analysis is he GD exp essed as: GD(ω)=−∂ϕ(ω) ∂ω .(5) These basic pa ame e s se e o de elop he HP-NGD speci ica ions. B. IDEAL SPECIFICATIONS OF HP-NGD FUNCTION The NGD analysis depends essen ially on he esponses o he equency dependen GD exp ession de ined by equa ion (5). The amilia iza ion o he NGD analysis consis s in he in e p e a ion o sign o he GD in unc ion o he equency band. 1) EXISTENCE CONDITION OF HP-NGD FUNCTION An elec onic ci cui can be assumed as a HP-NGD unc ion i i s VTF sa is ies he ollowing h ee condi ions: •Condi ion 1: The GD mus be posi i e a e y low- equencies (VLFs) whe e he equency is app oxi- ma ely equal o ze o. The condi ion in unc ion o GD a VLFs deno ed GD0can be w i en as: GD0=GD(ω≈0) >0.(6) •Condi ion 2: The GD mus p esen a cu -o angula equency deno ed by ωn=2π n. This equency pa ame e is he oo o equa ion: GD(ωn)=0.(7) •Condi ion 3: The wo p e ious condi ion implies ha he GD a he highe equency mus be ideally always nega i e. The e o e, in he NGD equency band indica ed by Fig. 2(a), we mus sa is y he ollowing inequa ion: GD(ω≥ωn)≤0.(8) The g aphical illus a ion o hese condi ions is ep- esen ed by he GD diag am depic ed by Fig. 2(a). In addi ion o he GD esponse, he VTF magni ude esponse beha e gene ally as shown in Fig. 2(b). This diag am (NdB(ω)=20log[N(ω)]≤0) is associa ed o ypical passi e opology as in oduced by Fig. 1. 2) PARTICULAR CHARACTERISTIC FREQUENCIES OF HP-NGD FUNCTION Simila o he ypical LP-NGD one, he HP-NGD unc ion is cha ac e ized by ce ain equencies associa ed o pa icula alues o he GD de ined by equa ion (5). In he ollowing pa ag aph, we ake he eal posi i e a iables N0and Na, and angula equency ωa. The ollowing h ee pa icula equencies a e conside ed o cha ac e ize an HP-NGD ci cui : •VLFs (ω≈0): We can ema k om he diag am o Fig. 2(b) ha he magni ude a VLFs can be speci ied by: N(ω≈0) =N0≤1.(9) VOLUME 10, 2022 27149 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology FIGURE 2. Typical (a) GD and (b) magni ude esponses o HP-NGD unc ion. •Cu -o equency (ω≈ωn): The magni ude can be de ined by: N(ω≈ωn)=Nn<N0.(10) •Op imal equency (ω≈ωa): This equency is he oo o equa ion:∂GD(ω=ωa) ∂ω =0.(11) A his op imal equency, he GD eaches i s minimal nega i e alue: GD(ωa)=min[GD(ω)]<0.(12) Then, he op imal magni ude can be de ined by: N(ωa)=Na<Nn.(13) The conc e e applica ion o hese speci ica ions o ou RL-ne wo k based opology is elabo a ed in he ollowing subsec ion. C. FREQUENCY-DEPENDENT RESPONSES The NGD analysis is based on he RL-ci cui VTF model de ined by equa ion (1). F om whe e, we de e mine he ansmi ance: N(jω)=Ra(R+jωL) RaR+jωL(R+Ra).(14) As de ined by equa ion (3), he associa ed magni ude is equal o: N(ω)=RasR2+(ωL)2 (RaR)2+[ωL(Ra+R)]2.(15) Empha ically, he associa ed phase, which is de ined by equa ion (4), is w i en as: ϕ(ω)=a c anωL R−a c anωL(Ra+R) RaR.(16) Then, i yields he GD o he RL-ne wo k opology unde s udy is gi en by: GD(ω)=R2LR2Ra−L2ω2(R+Ra) (R2+L2ω2)R2R2 a+L2ω2(R+Ra)2.(17) The explo a ion o each o hese exp essions lead o he syn hesis me hod o he HP-NGD ci cui in he ollowing sec ion. III. HP-NGD NGD ANALYSIS AND SYNTHESIS EQUATIONS The heo e ical app oach including he HP-NGD analysis and syn hesis o he ci cui opology unde s udy is de eloped in he p esen sec ion. A. ANALYTICAL VERIFICATION OF HP-NGD EXISTENCE CONDITION The h ee condi ions ci ed in p e ious Subsec ion II-B can be explo ed in mo e de ails as ollows: •Ve i ica ion o Condi ion 1: A VLFs, we can demon- s a e ha he GD es ablished p e iously becomes: GD(ω≈0) =L Ra .(18) We can ema k ha condi ion o inequa ion (6) is uncondi ionally e i ied o any alues o R,Raand L. •Ve i ica ion o Condi ion 2: By means o GD w i en in ela ion (17), he NGD cu -o equency de ined by equa ion (7) implies he equa ion: R2Ra−L2ω2 n(R+Ra)=0 (19) The posi i e eal solu ion o he p e ious polynomial equa ion is: ωn=R LsRa R+Ra .(20) We unde line ha he VTF magni ude a he cu -o equency de ined by equa ion (10) is equal o: Nn=sRa Ra+R.(21) •Ve i ica ion o Condi ion 3: Le us deno e a>1 a eal posi i e de ined by: ωa=aωn.(22) Fo he op imal equency de e mined om equa ion (11), his coe icien is equal o: a=s1+R+2Ra √R(R+Ra).(23) We can demons a e ha by means o GD exp essed in ela ion (17), he op imal GD can be exp essed as: GD(ωa)=√R(√R−√R+Ra) √R(R+Ra)+2R+Ra ωa(2R+Ra)(√R+√R+Ra) √R+Ra.(24) 27150 VOLUME 10, 2022 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology We ema k ha his GD, GDa=GD(ωa)<0, is always nega i e wha e e he alues o esis o s, Rand Ra, and induc o L. A he same equency, he magni ude exp essed in equa ion (15) becomes: N(ωa)=sR3 a (R+Ra)3.(25) We can analy ically demons a e ha Naand Nna e linked by he ela ion: Na=N3 n(26) which implies: Nn=N1/3 a.(27) In in e ence, he RL-ne wo k opology is heo e ically classi ied as an HP-NGD opology. B. INPUT AND OUTPUT IMPEDANCE ANALYTICAL EXPRESSIONS The access impedances can play a signi ican ole on he pe o mance o elec onic ci cui ma ching in unc ion o he su ounding in e ace componen s. The p esen sec ion in es iga es analy ically on he access impedance o ou HP- NGD cell. The inpu impedance o he ci cui in oduced by Fig. 1 can be exp essed as: Zin(jω)=Ra+jωRL R+jωL.(28) F om his exp ession, we can unde line ha : •A VLFs which co esponds o ω≈0: ZLF in =Ra(29) •A e y high equencies (VHFs) which co esponds o ω≈ ∞: ZHF in =Ra+R.(30) I is wo h o emind also ha he ou pu impedance is equal o: Zou (jω)=Ra.(31) We emphasize ha he ou pu impedance is independen o he equency. Mo eo e , a low equencies, we ha e he ela ion ZLF in =Zou and a high equencies ZHF in =Zou +R. C. HP-NGD SPECIFICATION OBJECTIVES The HP-NGD ci cui pa ame e s can be es ablished in unc ion o : •The a ge ed alue o NGD cu -o equency n, •The op imal equency a, •The GD op imal alue GDa<0. •And he ol age ampli ude Vmax and maximal powe P0 which a e linked by ela ion: P0=V2 max min[|Zin(jω)|].(32) By aking in o accoun he inpu impedance, his powe can be e o mula ed by: P0=V2 max Ra .(33) In addi ion o he p e ious ela ion, he o he esis o and induc o alues can be de e mined om equa ion sys em: (GD(ωa)=GDa N(ωa)=Na.(34) The ollowing subsec ion ea s he syn hesis equa ions o he HP-NGD opology. The syn hesis o mulas consis ing in calcula ing he alues o componen s R,Raand Las componen s o he RL-ne wo k opology unde s udy will be es ablished in he nex subsec ion. D. ELABORATION OF THE HP-NGD SYNTHESIS EQUATIONS The esis o Racan be de e mined knowing he inpu ol age ampli ude and IC maximal powe by means o equa ion (28): Ra=V2 max P0.(35) Empha ically, subs i u ing he p e ious exp ession in o he a enua ion gi en by equa ion (21), we ha e he ollowing esis o syn hesis o mula: R=V2 max P0 1 N2/3 a−1!.(36) Du ing he syn hesis, he NGD op imal a enua ion Na<1 is linked o he op imal equency and GD by he ela ion: Na=(9ξ2/3+3ζ1ξ1/3−3ζ2+ζ2 1)3 729ξ3(37) wi h:         ζ1=2π nGDa−1 2π nGDa ζ2=1+2π nGDa 2π nGDa (38) and: ξ=ζ1ζ2 6−ζ3 1 27 −1 2+ u u u u u u u u ζ3 1 27 −ζ1ζ2 6+1 2!2 +ζ2−ζ2 1 33 81 .(39) Mo eo e , by in e ing he equa ion o he NGD cu -o equency es ablished in equa ion (20), we ha e he syn hesis o mula o he induc o : L=R√Ra 2π n√R+Ra .(40) VOLUME 10, 2022 27151 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology E. ANALYTICAL RELATIONS BETWEEN THE HP-NGD PARAMETERS Knowing he p e ious o mulas o esis o s, we can demon- s a e ha he op imal and cu -o equencies gi en by he coe icien exp essed by equa ion (23) a e linked by ela ionship: a=sNn+1+1 Nn .(41) Fu he mo e, he HP-NGD opology p esen s a p ope y linked o he di e en pa ame e s, Na,GDa, and ωa. Subs i u ing he o mulas o esis o s es ablished by equa ion (35) and equa ion (36) in o he GD exp ession p oposed by equa ion (24), we ha e: GDa=Nn(Nn−1) ωn(1 +Nn)(1 +N2 n).(42) By using he coe icien o equa ion (36), he p e ious exp ession ans o ms as: GDa=N1/3 a(N1/3 a−1)q1+N1/3 a+N2/3 a ωaN1/6 a(1 +N1/3 a)(1 +N2/3 a).(43) Wi h hese exp essions, a HP-NGD IC in 130-nm CMOS echnology can be designed wi h he ollowing me hod. IV. HP-NGD CMOS IC POC DESIGN METHOD AND PROCESS The p esen sec ion deals wi h he HP-NGD IC design me hodology. The di e en s eps o be ul illed allowing o design he HP-NGD chips a e desc ibed. The HP-NGD POC is aimed o be designed in 130-nm CMOS echnology. A. DESIGN METHODOLOGY Simila o classical CMOS ICs o classical elec onic unc ions ( il e , ampli ie , oscilla o and many o he de ices) [27]–[31], he HP-NGD unc ion design mus s a om he ci cui speci ica ions o he inal layou design. In mo e clea iew, he me hodology o HP-NGD ICs can be illus a ed by he design low summa ized by he successi e s eps o Fig. 3. This HP-NGD CMOS IC design low can be desc ibed as ollows. In S ep 1, he design p ocess mus begin wi h he choice o he HP-NGD cu -o equency and NGD op imal alue which will imply he op imal a enua ion. The designe can e e o he speci ica ions o Figs. 2. In S ep 2, knowing he HP-NGD speci ica ions, he cons i u ing esis o and induc o alues can be calcula ed in he p esen s ep. The ideal componen alues can be calcula ed ia o mulas (35), (36) and (40). In S ep 3, he ange o he calcula ed componen alue mus be e i ied in he lib a y o he simula ion so wa e ( o he p esen s udy, Cadence-VURTUOSO). Then, he easibili y o he HP-NGD can be e i ied by he compa ison be ween he calcula ed esul s om he VTF model gi en in equa ion (14) and he schema ic simula ion. FIGURE 3. Design low o HP-NGD CMOS IC. In S ep 4, a e schema ic ideal simula ion, he layou can be d awn acco ding o he schema ic. The IC is implemen ed wi h espec o he design ule check (DRC) wi h high Ohmic unsalicided N +poly esis o and symme ical high cu en spi al induc o . The DRC is a p og am ha uses layou da abase o check e e y design ule in ol ed in layou . A e he p elimina y d awing o he layou , he DRC is needed o ensu e he ideal schema ic and layou IC consis ency. Fo example, he wid h and spacing o each wi e cons i u ing he layou mus be co ec ly implemen ed and should no iola e he speci ied minimum alue. The DRC ensu es ha he design can be manu ac u ed wi hin he limi s o p oduc ion p ocess. The layou e sus schema ic (LVS) s ep hen makes i possible o compa e he diag am o a ci cui wi h i s layou in o de o check whe he hey a e compa able, and lis any di e ences be ween hem In S ep 5, his s ep consis s o analyzing he con en o he HP-NGD ci cui layou in o de o ex ac he ac i e elemen s ( ansis o s, diodes) bu also he pa asi ic capaci ances and esis o s. An ex ac ed iew is hus ob ained, pe mi ing o simula e he ci cui while conside ing he pa asi ic componen s. In S ep 6, he esul s o he PLSs a e compa ed wi h he speci ica ions o he HP-NGD ci cui . Any modi ica ions a e hen made, in pa icula a he layou le el, o imp o e he esul s. Following he p e ious design low, HP-NGD IC POC esul is in es iga ed in he ollowing subsec ion. 27152 VOLUME 10, 2022 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology FIGURE 4. ADS schema ic o HP-NGD ci cui . B. DESCRIPTION OF THE SCHEMATIC DESIGN OF HP-NGD LUMPED CIRCUIT The i s s age o he p e-simula ion was ca ied by he lumped HP-NGD POC design om wo di e en so wa e s anda d ools o elec onic and mic owa e ci cui s. The p esen s udy is pe o med in he equency band om 1 MHz o 1 GHz. The design o he passi e ci cui POCs we e pe o med in he schema ic en i onmen o : •The ADS so wa e om Keysigh Technologies: The ADS schema ic o he designed RL-ne wo k based HP-NGD POC is p esen ed in Fig. 4. Two ci cui s wi h di e en pa ame e s we e conside ed. The main pa ame e s o he RL lumped elemen s cons i u ing he ci cui a e R,Raand L. The schema ic ci cui design includes he AC ol age sou ce. The inpu and ou pu accesses a e ep esen ed by Po 1and Po 2, espec i ely. •And he CADENCE -VIRTUOSO so wa e: The co esponding chip design was designed by aking in o accoun he 130-nm BiCMOS pa ame e s. The schema ic displayed in Fig. 5 ep esen he wo di e en ICs o he HP-NGD POCs. The HP-NGD IC schema ic pa ame e s we e calcula ed om syn hesis o mulas (35), (36) and (40) wi h espec o he desi ed speci ica ions. The chosen ci cui pa ame e s a e indica ed by Table 1. F om he chosen lumped componen s, we can design he co esponding layou . The CMOS componen s a e designed ollowing he lib a y o 130-nm echnology CADENCE-VURTUOSO. The ollowing subsec ion desc ibes he DRC based on he HP-NGD IC layou designs. C. DESCRIPTION OF THE LAYOUT DESIGN The STMic oelec onics BiCMOS-130 nm manu ac u ing p ocess was chosen o his s udy because o i s componen in eg a ion po en ial in he ange o HP-NGD desi ed speci ica ion alues. Due o he ela i ely la ge size o he componen s, expensi e manu ac u ing p ocesses such as 28 nm-FDSOI a e no needed. Figs. 6 display he wo layou s o he designed CMOS IC chipse s. Each layou is designed wi h 225 µm×215 µm size. The ci cui is expec ed o ope a e wi h Vmax =5 V. The FIGURE 5. Schema ic o HP-NGD ci cui POCs ep esen ing chip1and chip2designed in VIRTUOSO en i onmen . TABLE 1. P oposed speci ica ions and calcula ed pa ame e s o he HP-NGD POCs. esis o s and induc o we e expec ed o be implemen ed unde he manu ac u ing p ocess minimum squa e a ea. The SISO ci cui whole layou a ea is occupied by he wo esis o s in le and he la ge spi al induc o . The 100 µm×4.9 µm size esis o s a e implemen ed in 100-nm hickness poly-Si on 4.5- ela i e pe mi i i y dielec ic insu- la o . Each esis o is gua d- ing su ounded in o de o ensu e hei pola iza ion and he g ound plane connec ion h ough he dielec ic subs a e. The induc o is imple- men ed in Al-me al spi al oc agon wi h 0.0145 mm2su ace o e 1 µm hickness. All he layou componen in e connec- ions a e Cu-based in e connec me alliza ion wi h 0.1 µm hickness. The ange o he geome ical pa ame e s (wid h, leng h, numbe o u ns, diame e , Silicium a ea) o he conside ed VOLUME 10, 2022 27153 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology TABLE 2. Ranges o geome ical pa ame e s o he used designed 130-nm CMOS esis o s. FIGURE 6. (a) Chip1and (b) chip2Cadence-VIRTUOSO layou (DRC check s eps and esul s. 225 µm×215 µm=0.04837 mm2) o HP-NGD ci cui chipse s. esis o and induc o layou s in unc ion o he cons i u ing ma e ials a e add essed in Table 2 and Table 3, espec i ely. The minimal esonance equency is also indica ed. The easibili y s udy based on he HP-NGD unc ion alida ion will be examined in he ollowing subsec ion. V. FEASIBILITY STUDY OF THE HP-NGD THEORY AND THE DEVELOPED CMOS IC POC DESIGN To alida e he HP-NGD unc ion o he designed CMOS IC, equency (AC) and ansien Cadence-VIRTUOSO simula ions we e pe o med. The p esen sec ion deals wi h he easibili y s udy o he HP-NGD 130-nm CMOS IC. Then, he calcula ed and Cadence simula ed esul s a e discussed. Compa isons be ween he calcula ed (‘‘Calc.’’), schema ic (‘‘Schem.’’) and pos -layou simula ion (‘‘PLS’’) FIGURE 7. GD esul s o he HP-NGD ci cui chip1: (a) la ge and (b) na ow band plo s. simula ed VTFs we e ca ied ou . The calcula ed esul s we e gene a ed om MATLAB p og am o VTF modeled by equa ion (1). The ollowing subsec ions discuss he ob ained alida ion esul s. A. HP-NGD VALIDATION OF CMOS CHIP1 The esul s discussed in he p esen subsec ion co espond o VIRTUOSO AC schema ic and PLS esul s om CMOS chip1shown in Fig. 5 and Fig. 6(a), espec i ely. Figs. 7, Figs. 8 and Figs. 9 e eal he GDs, magni udes and phases o POC ep esen ed by CMOS chip1, espec i ely. The plo o Fig. 7(a) p esen s he la ge equency band ep esen a ion. Then, na owe equency band esul o GD om 100 MHz o 900 MHz is in oduced by Fig. 7(b) o highligh he HP-NGD cha ac e is ics as expec ed om diag am o Fig. 2(a). These plo s highligh he HP-NGD unc ion alidi y by means o he compa isons o he calcula ed, schema ic- based and PLS esul s. Figs. 7 alida e he HP-NGD beha io wi h a good co ela ion be ween he calcula ion, schema ic simula ion and PLS. Table 4 add esses he associa ed HP-NGD pa ame e s. The no able di e ences o he magni udes displayed by Figs. 8 be ween he schema ic and pos -layou simula ions a e mainly due o ia e ec o he in e connec due o layou 27154 VOLUME 10, 2022 M. Gue in e al.: Theo y and O iginal Design o Resis i e-Induc i e Ne wo k HP NGD IC in 130-nm CMOS Technology TABLE 3. Ranges o geome ical pa ame e s o he used designed induc o . FIGURE 8. VTF magni ude esul s o he HP-NGD ci cui chip1: (a) la ge and (b) na ow band plo s. TABLE 4. Compa ison o HP-NGD chip1cha ac e is ics. s ep which in ol es he c ea ion o pa asi ic esis ances and capaci o s. Because o he CMOS induc ance pa asi ic and design impe ec ion, i can be ound ha he NGD op imal alue and a enua ion om CMOS IC p esen a di e ence o abou GDa≈ −31 ps and Na≈ −1.45 dB a a≈246 MHz. Fo mo e con enien illus a ion o he alida ion, he ollowing subsec ion examines he AC esponses o he o he POC. B. HP-NGD VALIDATION OF CMOS CHIP2 Figs. 10, Figs. 11 and Figs. 12 p esen he equency domain compa ison esul s o GDs, magni udes and phase esul s FIGURE 9. VTF phase esul s o he HP-NGD ci cui chip1: (a) la ge and (b) na ow band plo s. TABLE 5. Compa ison o HP-NGD chip2cha ac e is ics. om chip2. The designed schema ic and layou a e shown in Fig. 6(a) and Fig. 6(b). Once again, Figs. 10 con i m he HP-NGD beha io . In addi ion, a good co ela ion be ween he calcula ed model, and schema ic simula ion and PLS o GDs p oposed by Figs. 10 and he associa ed phases o Figs. 12 is obse ed. in he equency domain. Table 5 add esses he associa ed HP-NGD pa ame e s. In his case o s udy, he calcula ed op imal GD and a enua ion a e o abou GDa≈ −47 ps and Na≈-3.3 dB a he equency a≈ 357 MHz. I can be poin ed ou ha he magni ude a enua ion o Figs. 11 om CMOS IC p esen s a di e ence o abou 1.7 dB. VOLUME 10, 2022 27155