Design and Implementation of Takagi-Sugeno Fuzzy Tracking Control for a DC-DC Buck Converter

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER Design and Implemen a ion o Takagi-Sugeno Fuzzy T acking Con ol o a DC-DC Buck Con e e Dhaouadi GUIZA1, Youce SOUFI 2, Djamel OUNNAS 2, Abde ezak METATLA1 1Depa men o Mechanical Enginee ing, Facul y o Technology, Uni e si y o Skikda, 26 Rou e El Hadaiek. 21000 Skikda, Alge ia. 2LABGET Labo a o y, Depa men o Elec ical Enginee ing, Facul y o Science and Technology, Uni e si y o Tebessa, Rou e de Cons an ine, 12002 Tebessa, Alge ia d.guiza@uni - ebessa.dz, y_sou i@yahoo. , djamel.ounnas@uni - ebessa.dz, me a la21_abde ezak@yahoo. DOI: 10.15598/aeee. 17i3.3126 Abs ac . This pape p esen s he design and imple- men a ion o a Takagi-Sugeno (T-S) uzzy con olle o a DC-DC buck con e e using A duino boa d. The p oposed uzzy con olle is able o pilo he s a es o he buck con e e o ack a e e ence model. The T-S uzzy model is employed, i s ly, o ep esen exac ly he dynamics o he nonlinea buck con e e sys em, and hen he conside ed con olle is designed on he basis o a concep called Vi ual Desi ed Va iables (VDVs). In his case, a wo-s age design p ocedu e is de eloped: i) de e mine he e e ence model acco ding o he de- si ed ou pu ol age, ii) de e mine he uzzy con olle gains by sol ing a se o Linea Ma ix Inequali- ies (LMIs). A digi al implemen a ion o he p o- posed T-S uzzy con olle is ca ied ou using he ATmega328P-based Mic ocon olle o he A duino Uno boa d. Simula ions and expe imen al esul s demons a e he alidi y and e ec i eness o he p o- posed con ol scheme. Keywo ds A duino boa d, DC-DC buck con e e , T-S uzzy model. 1. In oduc ion DC-DC buck con e e s a e widely used in indus ial and home en i onmen (mobile phone, compu e s, and home appliances). Thanks o hei inc easingly high e - iciency, oge he wi h a educed size, weigh and cos , hey ha e held an impo an place in connec ions o s o age ba e ies, pho o ol aic sys ems, wind u bines, hyb id sys ems [1], [2], [3] and [4]. Howe e , he con- ol o a buck con e e is s ill a challenging ask be- cause such a sys em exhibi s a nonlinea beha io wi h inhe en unce ain ies and dis u bances. Thus, he lin- ea con ol schemes canno ensu e sa is ac o y pe o - mances o e a wide ope a ing ange [5]. To add ess his p oblem, nonlinea and ad anced con ol design me h- ods ha e been p oposed, such as linea iza ion con ol [6] and [7], sliding mode [8] and [9], adap i e con ol [10] and [11], backs epping con ol app oach [12] and exac linea iza ion me hods [13]. The simplici y o design and he obus ness o he sliding mode con olle ha e made i he mos used one [14] and [15]. Bu , hese ad an ages a e neu alized by he p esence o an undesi able phenomenon known as ’cha e ing’ (oscilla ions ha ing ini e equency and ampli ude) which is conside ed as he main obs acle o implemen a ion [16] and [17]. In [18] and [19] an adap- i e backs epping con olle is p oposed o DC-DC buck con e e s. Bu i also su e s om di icul ies and limi a ions du ing he implemen a ion s age. In [20] and [21], a s a e eedback exac linea iza ion me hod is applied o DC-DC buck con e e s. Howe e , in [20], he e ec s o he di e en pa asi ic elemen s a e no aken in o accoun , while in [21] he de eloped con- olle canno be used in a wide ange o a ia ion be- cause o he excessi e ou pu ol age o e shoo . In he ield o uzzy logic, much esea ch has de o ed o he applica ion o uzzy Mamdani con olle s o con- e e s [22] and [23]. These wo ks a e ypically based on a small signal model using he s a e space a e ag- ing me hod; he model ob ained by hese me hods is only use ul o small a ia ions a ound a speci ic ope - a ing poin , whe eas he applica ion o Takagi-Sugeno (T-S) uzzy models on buck con e e s is no su i- cien ly in es iga ed. The T-S uzzy models owe hei popula i y o hei e ec i eness in modeling and con- c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 234 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER olling nonlinea sys ems [24] and [25]. The T-S uzzy model ep esen s a nonlinea sys em by a se o uzzy I - Then ules, which locally ep esen s he inpu -ou pu ela ionships o a sys em exp essing each conclusion wi h a linea subsys em. The ad an age o his ype o uzzy model lies in he s abili y o he uzzy sys em which can be analyzed using he Lyapuno me hod, and hen ea ed in e ms o he easibili y o a se o Linea Ma ix Inequali ies (LMIs). In his case, he p oblem can be sol ed easily by nume ical con ex op- imiza ion echniques [26]. Recen ly, he T-S uzzy acking con ol p oblem has been add essed in many wo ks based on a concep knwon as Vi ual Desi ed Va iables (VDVs) o sim- pli y he de elopmen o he con ol law and e e ence model [27], [28], [29], [30], [31] and [32]. Fu he mo e, he VDVs concep allows con e ing easily he ack- ing p oblem in o a s abiliza ion one. The concep has been analyzed in a numbe o s udies using he Lya- puno app oach and success ully in es iga ed in many con ol applica ions. Fo example, in [28], i was em- ployed o con ol a wind ene gy con e sion sys em. In [29], i was employed o con ol a Pe manen Magne Synch onous Machine (PMSM) while in [30], he same concep was used o con ol a pho o ol aic sys em. In [31], i was used o de elop a uzzy o que obse e o PMSM and in [32], i was combined wi h H in in- i y pe o mance o design a T-S uzzy con olle o a PMSM. In his pape , he pu pose is o de elop a T-S uzzy acking con olle o a buck con e e based on he VDVs concep . In his case, he p oposed con olle can be used o d i e he sys em o ollow he desi ed e e ence. Fi s , he nonlinea buck con e e sys em is ep esen ed by a T-S uzzy model. Then, a uzzy con olle is de eloped based on a se o i ual desi ed a iables o simpli y he design o he e e ence model and con ol law. Nex , he acking pe o mance o he enhanced uzzy sys em is analyzed by he Lyapuno me hod which can be o mula ed in o LMIs p oblems. Simula ion es s a e pe o med on a buck con e e o e i y he con olle ’s e iciency. Finally, he p oposed con olle is implemen ed on an ATmega328P-based mic ocon olle o A duino Uno. The emainde o his pape is composed as ollows: he Sec. 2. is de o ed o de ails on he ma hema ical buck con e e model. In he Sec. 3. he p o- posed uzzy con ol me hod is in oduced. I consis s o h ee main blocks: The i s pa deals wi h he T-S uzzy con olle , he second pa is dedica ed o s abil- i y analysis condi ions and he hi d one deals wi h he de e mina ion o he desi ed e e ence model and he nonlinea acking con olle . The esul s o he sim- ula ion and p ac ical implemen a ion o he p oposed con olle a e gi en in Sec. 4. and Sec. 5. ollowed by a conclusion a he end o his wo k. 2. Ma hema ical Buck Con e e Model The buck con e e can be ep esen ed by he ollowing nonlinea s a e space sys em o m: (˙x( ) = (x( )) + g(x( ))u( ) + η y( ) = ϕ(x( )) ,(1) x( ) = iL( ) o( ), η =−VD L 0,(2) (x( )) = =  −1 LRL+RRC R+RciL( )−R L(R+RC) o( ) R C(R+RC)iL( )−1 C(R+RC) o( ) ,(3) g(x( )) = 1 LVin +VD−RMiL( )u( ) 0,(4) ϕ(x( )) = RRC R+RciL( ) + R R+Rc o( ),(5) whe e RMis he esis ance o he ansis o (MOS- FET), RLis he winding esis ance o he induc o , VDis he h eshold ol age o he diode, RCis he equi alen se ies esis ance o he il e capaci o and Vin is he inpu ol age. iL, oand u ep esen , e- spec i ely, he induc ance cu en , he ou pu ol age and he du y cycle o he buck con e e , as shown in Fig. 1. I should be men ioned ha he in e nal esis- Vin D RL L RC R Rm M D L o + - + - + - o iL C - c Fig. 1: Equi alen ci cui o DC-DC buck con e e . ance Rm, he diode’s o wa d ol age VD, he equi - alen se ies esis ance o he il e capaci o RCand he winding esis ance o induc o RLha e no been aken in o accoun in many p e ious esea ches, which can pe u b he con ol o he buck con e e sys em. Consequen ly, his pape conside s a mo e gene al case. 3. Fuzzy Con ol Design The goal o his pape is o de elop a uzzy con- olle ha pe mi s o pilo he s a es o a buck con- e e x=iL oT o ack a desi ed ajec o y xd=iLd od T. Fi s ly, we design a uzzy con- olle based on he T-S uzzy model o a buck con- e e sys em and hen de elop a i ual e e ence c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 235 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER model and nonlinea con olle acco ding o he de- si ed ou pu ol age. Thus, he uzzy acking con ol scheme shown in Fig. 2 is p oposed. Nonlinea T acking Con olle TS-Fuzzy Con olle Re e ence Model + - Vin D RL L RC R Rm M D L o + - + - + - o iL C - c c iL e x τ u T-S uzzy con ol 0 0 Fig. 2: P oposed uzzy con ol scheme. 3.1. T-S Fuzzy Model o Buck Con e e The de elopmen o he p oposed T-S uzzy con olle goes h ough he ans o ma ion o nonlinea model Eq. (1) in o a uzzy model by using he a iable o he induc ance cu en iLas decision a iable. The nonlinea s a e space o buck con e e is gi en by he ollowing o m: (˙x( ) = Ax( ) + B(iL)u( ) + E y( ) = o=Cx( )) ,(6) whe e: A="−1 LRL+RRC R+Rc−R L(R+RC) R C(R+RC)−1 C(R+RC)#,(7) B(iL) = 1 L(Vin +VD−RMiL( )) 0,(8) E=−VD L 0, C =hRRc R+RC R R+RCi.(9) Assuming ha he p emiss a iable z( ) = iL( )is bounded as: iL≤iL( )≤iLand using sec o nonlin- ea i y ans o ma ion [33], he nonlinea sys em Eq. (6) can be exac ly ep esen ed by a T-S uzzy model using he ollowing wo I -Then ules: Rule1: I iLis F11 Then ˙x( ) = A1x( ) + B1u( ) + E1, Rule2: I iLis F12 Then ˙x( ) = A2x( ) + B2u( ) + E2, whe e F11 and F12 a e he membe ship unc ions gi en by: F11(iL) = iL( )−iL iL−iL , F12(iL)=1−F11(iL).(10) The sub-ma ices a e de ined as: A1=A2="−1 LRL+RRC R+Rc−R L(R+RC) R C(R+RC)−1 C(R+RC)#, (11) B1=1 LVin +VD−RMiL 0,(12) B2=1 L(Vin +VD−RMiL) 0, E1=E2=−VD L 0. (13) The inal ou pu o uzzy model is in e ed as ollows: ˙x( ) = X i=1 hi(z( )) (Aix( ) + Biu( ) + E),(14) whe e hi(z) = ωi(z)/P i=1 ωi(z),ωi(z) = Qn j=1 Fij(zj) o all > 0,hi(z)≥0and P i=1 hi(z)=1. 3.2. Con ol Design and S abili y Analysis The T-S uzzy con ol is necessa y o sa is y he ol- lowing condi ion: x( )−xd( )→0as → ∞,(15) whe e xd( ) ep esen s he desi ed ajec o y a iable. Le us de ine he acking e o as ˜x( ) = x( )−xd( ). Then, i s ime de i a i e can be gi en by: ˙ ˜x( ) = ˙x( )−˙xd( ).(16) By subs i u ing Eq. (14) in o Eq. (16) and adding he e m P i=1 hi(z)Ai(xd( )−xd( )), Eq. (16) becomes: ˙ ˜x( ) = X i=1 hi(z) (Ai˜x+Biu+Aixd( ) + Ei)−˙xd. (17) In Eq. (17), le us choose a new con ol a iable τ( ) ha sa is ies he ollowing condi ion: X i=1 hiBiτ= X i=1 hi(z) (Aixd+Biu+E)−˙xd.(18) By using Eq. (18), he acking e o de i a i e Eq. (17) can be ew i en as ollows: ˙ ˜x( ) = X i=1 hi(iL( ))(Ai˜x( ) + Biτ( )).(19) c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 236 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER The new con olle s a e de eloped o deal wi h he uzzy acking con ol p oblem as: Con olle ule 1: I iL( )is F11 Then τ( ) = −K1˜x( ), Con olle ule 2: I iL( )is F12 Then τ( ) = −K2˜x( ). The inal uzzy con olle ou pu is gi en by: τ( ) = − X i=1 hi(z( ))Ki˜x( ).(20) By subs i u ing Eq. (20) in o Eq. (19), he inal closed- loop sys em akes he ollowing o m: ˙ ˜x( ) = X i=1 X j=1 hi(z( ))hj(z( ))(Ai−BiKj)˜x( ).(21) By le ing Gij = (Ai−BiKj), Eq. (21) can be ew i en as ollows: ˙ ˜x( ) = X i=1 X j=1 hi(z( ))hj(z( ))Gij ˜x( ).(22) S abili y Analysis. Ob aining he uzzy con olle consis s in de e mining he gains Kisa is ying he con- di ions o he ollowing heo em [28] and [29]: Theo em 1 The con inuous model Eq. (22) is asymp o ically s able ia he uzzy con olle Eq. (20), i he e exis s a diagonal ma ix D, ma ices Qij wi h: Qii =QT ii and Qji =QT ij o i6=j, and a common posi i e de ini e ma ix P > 0such ha : GT iiP+PGii +Qii +DPD < 0, i = 1, ..., , (23) Gij +Gji 2T P+PGij +Gji 2+Qij ≤0, i<j≤ , (24)      Q11 Q12 . . . Q1 Q12 Q22 . . . Q2 . . ..... . . Q1 Q2 . . . Q      ≡˜ Q > 0,(25) o i,j= 1, . . . , , s. . he pai s (i,j)such ha : hi(z)hj(z)=0,∀ . The de e mina ion o he uzzy con ol gains equi es changing he condi ions o he p e ious heo em in o an equi alen p oblem o linea ma ix inequali ies. This ans o ma ion co esponds o simple objec i e changes o a iables X=P−1,Ki=MiX−1and he use o a cong uence in inequali ies Eq. (23), Eq. (24) and Eq. (25). Then, he ollowing LMIs can be ob- ained. ∃X=XT>0,∃Yii =YT ii ,∃Yij =YT ji ,∃Mi: XAT i+AiX−BiMi−MT iBT i+Yii XDT DX −X<0, (26) XAT i+AiX+XAT j+AjX−BiMj−MT jBT i −BjMi−MT iBT j+ 2Yij ≤0, i<i≤ , (27)      Y11 Y12 . . . Y1 Y12 Y22 . . . Y2 . . ..... . . Y1 Y2 . . . Y      ≡˜ Y > 0.(28) 3.3. Desi ed Re e ence Model and Nonlinea Con olle In o de o de e mine he desi ed e e ence model xd and nonlinea con olle u( ), we use Eq. (18) which can be ew i en as ollows: X i=1 hiBi(u−τ) = − X i=1 hiAixd− X i=1 hiE+ ˙xd.(29) No ing ha : A= X i=1 hiAi, B = X i=1 hiBi, E = X i=1 hiEi.(30) Then, Eq. (29) can be ew i en in he ollowing o m: B(u( )−τ( )) = −Axd( )−E+ ˙xd( ).(31) Eq. (31) can be ew i en as ollows: 1 L[Vin +VD+RMiL( )] 0(u( )−τ( )) = =−"1 L[RL+RRC R+Rc]−R L(R+RC) R C(R+RC)−1 C(R+RC)#iLd cd + −−VD L 0+˙ iLd ˙ cd .(32) I should be men ioned ha he nonlinea con ol law and he desi ed e e ence model will be calcula ed ac- co ding o he desi ed ou pu ol age. F om he second equa ion o Eq. 32, we ob ain −R C(R+RC)x1d+1 C(R+RC)x2d= 0 ⇒x1d=x2d R.(33) F om he i s equa ion o Eq. 32, we can de i e he nonlinea con ol law u( ), as ollows: u( ) = (RL R+RC R+RC+R R+RC)x2d+VD Vin +VD+RMiL( ).(34) c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 237 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER 0 0.005 0.01 0.015 0.02 0 0.5 1 1.5 2 2.5 3 3.5 Times (s) Cu en (A) 5 6 7 8 9 10 x 10−3 0.15 0.16 0.17 0.18 iL iLd (a) Induc ance cu en . 0 0.005 0.01 0.015 0.02 0 2 4 6 8 Vol age (V) o od Times (s) (b) Ou pu ol age. 0 0.5 1 1.5 2 2.5 3 3.5 x 10−3 0 0.2 0.4 0.6 0.8 1 Times (s) PWM Signal (c) PWM signal. 0 0.005 0.01 0.015 0.02 0 0.2 0.4 0.6 0.8 1 Times (s) Du y cycle u( ) 5 6 7 8 9 10 x 10−3 0.68 0.69 0.7 (d) Du y a io. Fig. 3: Simula ion esul s o ol age e e ence od = 8 V. Time (s) 0 0.02 0.04 0.06 0.08 0.1 Ou pu Vol age (V) 0 1 2 3 4 5 6 7Desi ed Vol age TS Con olle PI Con olle 0 0.01 0.02 0.03 0.04 0 1 2 3 4 5 Fig. 4: Compa ison be ween PI and T-S uzzy con olle s. 4. Simula ion Resul s In o de o e i y he pe o mance o he p oposed uzzy acking con ol, simula ion es was ca ied ou on a DC-DC buck con e e . The con olle gains a e ob ained by sol ing he LMIs Eq. (26), Eq. (27) and Eq. (28), as ollows: K1=0.4829 0.1582 ,(35) K2=0.4537 0.1345 .(36) The i s simula ion is ca ied ou in ou pu ol - age e e ence od = 8 V. The esponses o he induc- Ma lab/Simulink model Ha dwa e Communica ion ia USB po Fig. 5: Communica ion wi h an A duino boa d using Ma lab inpu /ou pu package. Tab. 1: Pe o mances compa ison be ween PI and T-S con- olle s. Me hod PI con olle T-S con olle Rise ime (s) 0.0187 6.6211 ·10−4 Se ling ime (s) 0.0327 0.0012 O e shoo (%) 0.0264 0 ance cu en , ou pu ol age, PWM signal and du y cycle a e depic ed in Fig. 3(a), Fig. 3(b), Fig. 3(c) and Fig. 3(d), espec i ely. The esul s indica e ha he s eady s a es ack he desi ed ajec o ies pe ec ly. I is also shown ha he ime esponse equi ed o ol- low he e e ence model is e y sho (0.0012 s). I can be concluded ha he p oposed T-S uzzy con ol has a good acking pe o mance. In he second simula- ion es , he T-S uzzy con olle is compa ed wi h he base-line PI (P opo ional In eg a o ) con olle due o i s popula i y. The PI pa ame e s (Kpand Ki) a e cal- cula ed based on he ollowing buck ans e unc ion c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 238 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER Induc o Cu en senso Vol age senso Load A duino Uno MOSFET Diode Capaci o (a) Ha dwa e se up. V e G oup 1 Vol age Re e ence 10/1023 Con e sion o V e Real-Time Pace Speedup = 1 Real-Time Pace A duino1 Analog Read Pin 2 Po en iome e Se up A duino1 COM12 A duino IO Se up Sa u a ion A duino1 Analog W i e Pin 11 A duino Analog W i e A duino1 Analog Read Pin 0 Cu en Senso V e xd VDVs xd x iL Tho T-S Fuzzy Con olle xd iL Tho u Nonlinea Con olle Manual Swi ch 254 Con e o PWM A duino1 Analog Read Pin 1 Vol age Senso (b) Simulink model using Ma lab inpu /ou pu package. Fig. 6: Ha dwa e implemen a ion using A duino Uno and Simulink model. [36] and [37]: G(s) = Vo u=Vin R R+RL   s ωZERO + 1 Ω(s)  ,(37) whe e Ω(s) = s2 ω2 0 +s Qω0 + 1,(38) ω0=1 LC R+Rc R+RL , ωZERO =1 CRc ,(39) Q=1 ω0L R+RL +RRLC R+RL +RcC.(40) The PI pa ame e s (Kpand Ki) a e ob ained by us- ing he known compensa ion me hod, as ollows: Kp= 0.195, Ki= 9.88.(41) The esponse o he ou pu ol age o od = 5 V ise ime, he se ling ime and he o e shoo o he wo me hods. F om Fig. 4 and Tab. 1, i can be con i med ha he T-S con olle o e s supe io pe o mance and as dynamic esponse in e ms o apidi y and limi a ion o o e shoo . 5. Expe imen al Ve i ica ion To e i y he simula ion esul s, a special package known as inpu /ou pu (I/O) suppo package is used wi h Ma lab en i onmen , which has been designed by Ma hWo ks o mic ocon olle -based A duino boa d 10/1023 Con e sion o V e Sa u a ion V e xd VDVs xd x iL Tho T-S Fuzzy Con olle xd iL Tho u Nonlinea Con olle 254 Con e o PWM Pin 2 ARDUINO Po en iome e Pin 5 ARDUINO PWM Pin 0 ARDUINO Cu en Senso Pin 1 ARDUINO Vol age Senso Fig. 7: Simulink model using Ma lab suppo package. o in e ace he Ma lab/ Simulink wi h he ha dwa e se up wi hou any p og amming language [34]. This package is p ima ily used o eal- ime communica- ion be ween A duino boa d and Simulink, as shown in Fig. 5. The ha dwa e consis s o a buck con e e , an A duino Uno, a ol age senso and a cu en senso . The ha dwa e and Simulink model used in his imple- men a ion s age a e shown in Fig. 6(a) and Fig. 6(b), espec i ely. No e ha he pa ame e s gi en in Ap- pendix A a e conside ed o he de elopmen o a buck con e e p o o ype. The expe imen is conduc ed wi h a mul i-s ep ol - age e e ence. The expe imen al wa e o m and sim- ula ion esponse o ou pu ol age a e illus a ed in Fig. 8(a) and Fig. 8(b). I is ob ious ha he ob ained esul s in bo h he simula ion and he implemen a ion a e in good ag eemen . A e he p e ious e i ica ion and alida ion o he simula ion esul s, he p oposed sys em should be c e- a ed as a s andalone p ojec ha does no need o be c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 239 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 3 |2019 |SEPTEMBER 0 5 10 15 20 25 30 35 40 0 1 2 3 4 5 6 7 8 Time (s) Vol age (V) od o (a) Simula ion esul s o ou pu ol age. (b) Expe imen al wa e o m o ou pu ol age. Fig. 8: Simula ion and expe imen al esul s o mul i-s ep ol age e e ence. connec ed o he Simulink (hos compu e ) [35]. In his espec , i is necessa y o deploy he p oposed acking con ol algo i hm o he A duino boa d. To achie e his, an A duino suppo package is used, as shown in Fig. 7. The expe imen al wa e o ms o he ou pu ol - age and he du y cycle o a e e ence ol age od = 5 V a e shown in Fig. 9. These p ac ical esul s demons a e ha buck con- e e can be con olled by he p oposed me hod o low exac ly he desi ed ou pu ol age. Fig. 9: Expe imen al esul s o desi ed ol age od = 5 V. 6. Conclusion A T-S uzzy acking con olle is p oposed o a DC- DC buck con e e which is able o pilo he sys em o ollow a desi ed e e ence model. The con olle gains a e ob ained based on su icien condi ions o - mula ed in o LMIs o m and sol ed using op imiza ion ools. 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