Fuzzy controlled parallel AC-DC converter for PFC

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 70 FUZZY CONTROLLED PARALLEL AC-DC CONVERTER FOR PFC SUBBARAO.M1, Sai BABU.Ch2, SATYANARAYANA.S3, SOBHAN.P.V.S1 1Depa men o Elec ical and Elec onics Enginee ing, Vignan’s Enginee ing College, Vadlamudi, 522 213, India 2Depa men o Elec ical and Elec onics Enginee ing, College o Enginee ing JNTUK, Kakinada, 533 003, India 3VRS& YRN Eng. College, Chi ala, 523 157, India subbu.mopide [email protected], [email p o ec ed], [email p o ec ed], [email p o ec ed] Abs ac . Pa alleling o con e e modules is a well- known echnique ha is o en used in medium-powe applica ions o achie e he desi ed ou pu powe by using smalle size o high equency ans o me s and induc o s. In his pape , a pa allel-connec ed single- phase PFC opology using lyback and o wa d con e e s is p oposed o imp o e he ou pu ol age egula ion wi h simul aneous inpu powe ac o co ec ion (PFC) and con ol. The goal o he con ol is o s abilize he ou pu ol age o he con e e agains he load a ia ions. The pape p esen s he de i a ion o uzzy con ol ules o he dc/dc con e e ci cui and con ol algo i hm o egula ing he dc/dc con e e . This pape p esen s a design example and ci cui analysis o 200 W powe supply. The p oposed app oach o e s cos e ec i e, compac and e icien AC/DC con e e by he use o pa allel powe p ocessing. MATLAB/SIMULINK is used o implemen a ion and simula ion esul s show he pe o mance imp o emen . Keywo ds Flyback con e e , PFC, powe con e sion, uzzy con ol. 1. In oduc ion A numbe o powe ac o co ec ion ci cui s ha e been de eloped ecen ly [1], [2], [3], [4] and [5]. No mally a boos con e e is employed o PFC wi h DC/DC s age o imp o e pe o mance o a lyback con e e is used o educe he cos . Al hough bo h boos con e e and lyback con e e a e capable o PFC applica ions [6], he main di icul y in wo-s age scheme employing a PFC boos and a DC/DC con e e is he high cos and lowe e iciency. Howe e , single-s age me hod using he simples lyback con e e is no able o igh ly egula e he ou pu ol age. Pa alleling o con e e powe modules [7] is a well-known echnique ha is o en used in high-powe applica ions o achie e he desi ed ou pu powe wi h smalle size powe ans o me s and induc o s [10]. Since magne ics a e c i ical componen s in powe con e e s because gene ally hey a e he size-limi ing ac o s in achie ing high-densi y and/o low-p o ile powe supplies, he design o magne ics becomes e en mo e challenging o high-powe applica ions ha call o high powe -densi y and low-p o ile packaging. Ins ead o designing la ge-size cen alized magne ics ha handle he en i e powe , low-powe dis ibu ed high densi y low- p o ile magne ics can be u ilized o handle he high p ocessing powe , while only pa ial load powe low h ough each indi idual magne ics [10], [11]. In addi ion o physically dis ibu ing he magne ics and hei powe losses and he mal s esses, pa alleling also dis ibu es powe losses and he mal s esses o he semiconduc o s due o a smalle powe p ocessed h ough he indi idual pa alleled powe s ages. As a esul , pa alleling is a popula app oach o elimina ing "ho spo s" in powe supplies. In addi ion, he swi ching equencies o pa alleled, lowe -powe powe s ages may be highe han he swi ching equencies o he co esponding single, high-powe p ocessing s ages because lowe -powe , as e semiconduc o swi ches can be used in implemen ing he pa alleled powe s ages. Consequen ly, pa alleling o e s an oppo uni y o educe he size o he magne ic componen s and o achie e a low-p o ile design o high powe applica ions. Wi hou inc easing he numbe o powe s ages and con ol-ci cui componen s, he ans o me magne ics can be dis ibu ed by di ec ans o me pa alleling. No only ha ans o me pa alleling dis ibu es he p ocessed powe in each magne ics componen s, bu also hei powe losses and he mal s esses a e dis ibu ed a he same ime. Howe e , cu en sha ing among he pa alleled ans o me s needs o be main ained o ensu e powe balance. In i s basic o m, he in e lea ing echnique can be iewed as a a ia ion o he pa alleling echnique, whe e he swi ching ins an s a e phase-shi ed wi hin a swi ching pe iod [12]. By in oducing an equal phase shi be ween he pa alleled powe s ages, he o al induc o cu en ipple o he powe s age seen by he POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 71 ou pu il e capaci o is lowe ed due o he ipple Cancella ion e ec [12]. The goal o he p oposed PFC scheme is o educe he passi e componen size, o employ lowe a ed semiconduc o , and o imp o e o al e iciency. Simula ion esul s show ha he p oposed opology is capable o o e ing good powe ac o co ec ion and as dynamic esponse. 2. PFC Cells 2.1 Two S age PFC App oach A wo-s age scheme shown in Fig. 1 is mainly employed o he swi ching powe supplies since he boos s age can o e good inpu powe ac o wi h low o al ha monic dis o ion (THD) and egula e he dc-link ol age and he DC/DC s age is able o ob ain as ou pu egula ion wi hou low equency ipple due o he egula ed dc-link ol age [13]. These wo powe con e sion s ages a e con olled sepa a ely. Howe e , wo-s age scheme su e s om highe cos , complica ed con ol, low-powe densi y, and lowe e iciency. 2.2 Single S age PFC App oach Fo low powe applica ions, whe e cos is a dominan issue, a single-s age scheme using he lyback con e e Fig. 2 is mo e a ac i e han a wo-s age scheme. 2.3 Pa allel PFC App oach A highe powe le els, since i may be bene icial o pa allel wo o mo e DC/DC con e e s a he han using a single highe powe uni , a pa allel-connec ed scheme is p oposed as shown in Fig. 3. This app oach can o e as ou pu ol age egula ion and high e iciency. The o wa d con e e wi h DC/DC s age can o e good ou pu ol age egula ion due o he p e y dc inpu ol age and he lyback con e e wi h AC/DC PFC s age ul ills inpu cu en egula ion o ob ain highly e icien powe ac o . Fig. 1: Two-S age PFC. Fig. 2: Single s age PFC. Fig. 3: P oposed pa allel-connec ed single-phase PFC scheme. POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 72 Fig. 4: Pa allel-connec ed single-phase PFC scheme. 3. P oposed Pa allel PFC Scheme Figu e 4 shows he p oposed pa allel-connec ed PFC scheme which employs a diode ec i ie , dc-link capaci o , o wa d con e e and lyback con e e . The unc ion o a o wa d con e e wi h an elec oly ic capaci o is o suppo ou pu ol age egula ion. A lyback con e e ul ills he unc ion o powe ac o co ec ion by making inpu cu en sinusoidal and egula ing dc-link ol age. The ope a ion o he lyback con e e is gi en in his pa ag aph conside ing ha he o wa d con e e ope a es ideally. The PFC Cell ( o wa d con e e ) ope a es wi h con inuous conduc ion mode in bo h an inpu induc o and a lyback ans o me . The dc-link ol age in his scheme: sdc VV  2. (1) The ans e unc ion o he lyback con e e is exp essed by de ining a con e sion a io as he a io o he dc ou pu ol age o he inpu ol age: )1( nD D V V Md o   , (2) whe e, D is he du y a io o he swi ch Qh, n (=Np/Ns), is de ined as he a io o Np o Ns, and Np and Ns deno e he numbe o u ns o p ima y and seconda y side, espec i ely. To analyze he ci cui pa ame e s, basic equa ions o ol ages and cu en s a e gi en by: hpd iii  , (3) d di LV d d L, (4) d Ld hi VVV  , (5) Qhhih VVV   1, (6) whe e id , ip, and ih a e he ec i ied, DC/DC Cell, and PFC Cell inpu cu en s on dc side. VLd , Vhi, Vhi, Vd ,Vh1, VQh, and Vo and a e he inpu induc o , lyback con e e inpu , ec i ied inpu , ans o me p ima y winding, swi ch, and ou pu ol ages, espec i ely. Since he wo inpu cu en s, ip and ih, a e in e lea ed, inpu cu en , id , ipple can be signi ican ly educed. The ope a ional sequences a e as ollows:  0- 1: As shown in Fig. 5(a) The cu en o lyback ans o me does no low simul aneously in bo h windings. When he swi ch Qh is u ned ON a o, VQ becomes ze o and diode Doh is u ned OFF wi h a e e se bias. The ol age ac oss he diode Doh equals o Vo + Vhi/n. Ene gy, LmhI2, is cha ged in he magne ic ield in he p ima y winding o he lyback ans o me . P ima y cu en , ih, amps up om he emaining magne izing cu en and eaches Id wi h he slope, (Vhi /Lmh), ip dec eases wi h a slow cu en ail, and slowly dec eases un il ip eaches ze o. A he same ime he o wa d con e e swi ch Qp is OFF because, as he swi ch Qh is ON he po en ial a he junc ion o diode Dp and inpu induc o Ld i.e. VLd >Vhi, he diode Dp is e e se biased. The diode Dop is also e e se biassed due o he pola i y o he o wa d ans o me and a nega i e ol age o -nVo. The ol age ac oss he ou pu induc o is VL= -Vo and he induc o cu en iL dec eases and iL along wi h ioh, ci cula es h ough diode D , and supplied o load. POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 73 Fig. 5(a): Fo wa d con e e swi ch Qp is OFF and lyback con e e swi ch Qh is ON.  1- 2: The p ima y cu en o lyback con e e inc eases by Vd /(Lmh + Ld ). The ol age ac oss swi ch Qp dec eases om 2Vd o Vd . The inpu induc o cu en amps up o ill swi ch Qh is OFF. Fig. 5(b): Fo wa d con e e swi ch Qp is ON and lyback con e e swi ch Qh is OFF.  2- 3: As shown i Fig. 5(b), when he swi ch Qh is u ned OFF, Doh is u ned ON wi h o wa d bias. The cu en in he p ima y winding ceases o low. The s o ed ene gy is ans e ed o he seconda y winding. A his ime, he swi ch ol age, VQh, becomes Vhi+nVo, ip becomes id and dec eases depending on inpu ol age, and he seconda y cu en dec eases wi h he slope (n2Vo/Lmh). When he swi ch Qp is ON, he diode Dp is o wa d biassed because he po en ial a junc ion be ween he diode and induc o is VLd <Vhi+nVo. The p ima y cu en o o wa d ans o me amps up and he ene gy s o ed in he p ima y winding is ins an aneously ans e ed o seconda y, because o he same pola i y o he o wa d ans o me . The diode Dop is o wa d biassed and diode D is e e sed biassed. The ou pu induc o cu en iL inc eases along wi h ioh which is deli e ed o load. The cu en slope h ough he magne izing induc o when he swi ch Qh is u ned o is gi en as: o mh o mh T L nV i , (7) whe e, To is he u n-o ime. Simila ly, he change o he lyback con e e inpu cu en ip h ough a diode is: o d d pT L VVdc i  . (8) Based on wo slopes o imh and ip, he ailed diode cu en mode in which he diode cu en has cu en ail, when he slope o imh is g ea e han ha o ip: mh d odcmh d L LnVVL  . (9) In con inuous conduc ion inpu induc o cu en mode, when he MOSFET is swi ched on, he diode Dp is o ced in o e e se eco e y a a high a e o change in he diode cu en ip. In his ailed mode ope a ion, howe e , he diode cu en slowly dec eases so ha he e e se eco e y e ec can be minimized. To analyze he lyback con e e ope a ion, an open loop du y a io is ob ained om (2) as: od o hopen nV nV D  ,, (10) whe e, inpu ol age SinV sd  2: d s ond hiD T Ti i. , (11) d p iDi ).1(  , (12) whe e, inpu cu en SinIi sd  2. The e o e, wo cu en s can be ob ained: os so hnV SinV SinInV i    2 2, (13) hs os o sp i SinI nV SinV nV SinIi                 2 2 12 . (14) The ins an aneous powe s h ough he diode Dp and he ans o me T2 a e calcula ed by using he inpu induc ance and he magne izing induc ance: ].[ 2 ,up LL LL P d mh d mh pup   , (15) ].[ 2 ,up LL L P d mh mh puh  , (16) whe e, Lmh and Ld deno e he magne izing induc ance o T2 and inpu induc ance, espec i ely, and he inpu o al powe ].[1 ,,, upPPP puhpuppuin    . On he o he hand by employing he open loop du y a io Dopen, h, wo ins an aneous powe s can be de i ed by:   hsspdcp i SinIViVP   22. , (17) POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 74 pinh PPP  , (18) whe e }2cos1{ IVP ssin   . The ela ions be ween wo induc ances and wo inpu a e age powe s o wo con e e s a e exp essed as: a eh a ep mh d mh P P L LL , ,  , (19)           1 , , a eh a ep mhd P P LL . (20) The ou pu cu en s o he wo cells a e gi en by u ns a io: hoh op ini ini . .  . (21) Since he ou pu load cu en io may con ain only dc and swi ching equency componen s, he ha monic con en s o he p ima y cu en o he lyback con e e - I is exp essed as: o ss ohopo V IV iii  , (22) xhx ii ,, , (23) whe e, x = (2 , 4, 6, e c.) is ha monic o de . F om (23), he dc-link capaci o cu en can be es ima ed as a second ha monic: .2cos)( 2,2,2, iii hpdc   (24) The e o e, he ol age ipple o he dc-link capaci o is ob ained as: C ii V p hp ippledc   2sin 2 2,2, ,   , (25) whe e, Cp is he capaci ance o he dc-link capaci o . 4. Con e e Con olle s To con ol he p oposed app oach, wo con ol s ages a e equi ed o PFC and ou pu ol age egula ion as shown in Fig. 6. Flyback con e e is egula ed by a con en ional PFC con olle which consis s o inne inpu cu en loop and ou e dc-link ol age [13] o ob ain high powe ac o . DC-link ol age is 1,414*Vs, which is be e o educe he ol age ac oss d ain-sou ce o MOSFET Qp . Based on he PFC con olle , a eed- o wa d con ol block is added o imp o e inpu cu en shape. Since he open loop du y a io Dopen,h o he PFC cell is calcula ed om (10), he inal du y a io o he swi ch ga e inpu is ob ained as pihopenh DDD  ,, (26) whe e Dpi, is he closed loop du y a io ob ained om S- R lip lop cu en con olle . The ou pu Dpi o he S-R lip lop cu en egula o con aining a small amoun o a ia ions p o ides he co ec ion o he inal du y a io. On he o he hand, ou pu ol age Vo con ol is achie ed by o wa d con e e . Figu e 8 shows a Fuzzy ol age con olle wi h a open loop du y a io Dopen,h which is calcula ed simila ly o Dopen,p in e ms o powe a ings o each con e e pupod pupo popen PnV PnV D . . , . (27) Final du y a io Dp is ob ained by adding he du y a io Dpi om con olle wi h Dopen,p. The ou pu ol age con ol esponse is much as e han single s age scheme since wo con e e s a e employed o sepa a e con ol unc ion. Fig. 6: Con e e con olle s. 5. Design Example The p oposed PFC ci cui is designed acco ding o he ollowing pa ame e s:  o al ou pu powe (Po) = 200 [W],  inpu ol age (Vs) = 230 [V],  ou pu ol age (Vo) = 48 [V],  line equency = 50 [Hz],  swi ching equency = 37000 [Hz],  ou pu dc capaci ance (Co) = 1500 [μF],  ans o me u ns a io (n) = 4,41:1. Fo wa d Con e e :  powe a ing = 109,4 [W],  magne izing induc ance (Lmp) = 0,5 [mH], POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 75  DC capaci ance = 660 [µF]. Flyback Con e e :  powe a ing = 90,6 [W],  magne izing induc ance (Lmh) = 1,2 [mH]. The p oposed scheme p o ides small inpu induc o since he induc o cu en depends on, dc-link ol age is smalle so ha he ol age s ess on he swi ch o he o wa d con e e is less, he powe a ing o DC/DC s age is a bi highe han a e age powe due o lowe ha monic componen s, and he diode e e se eco e y loss is minimized because o he ailed diode conduc ion mode. The membe ship unc ions o he inpu s e o , change in e o and ou pu a e iangula as shown in Fig. 7. Fig. 7: Single s age PFC. Tab.1: FIS ule able. E/ce NB NS ZE PS PB PB NS NS NS NS NB PS ZE ZE ZE NS NS ZE ZE ZE ZE ZE ZE NS PS PS ZE ZE ZE NB PB PS PS PS PS In e ence sys em ule able used o he design o uzzy con olle is shown in Fig. 8. Fig. 8: MATLAB/Simulink model o p oposed opology. 6. Simula ion and Resul s The p oposed opology is implemen ed using MATLAB/Simulink is shown in Fig. 8. The esul s o he p oposed opology a e shown in Fig. 9, 10 and 11. Uni y powe ac o and igh ou pu ol age (48 V) egula ion can be achie ed. The dc-link ol age is 1,414*Vs=325 V, and he ol age ipple o he dc-link is 0,4 V which mainly depends on he dc-link capaci ance. Two con ol sys ems a e implemen ed o p o e he p oposed scheme 7. Conclusion A pa allel-connec ed single phase powe ac o co ec ion (PFC) opology using Fuzzy con olle o o wa d con e e and a lyback con e e has been p oposed. I has been shown ha ou pu ol age egula ion is achie ed by DC/DC cell and he inpu powe ac o co ec ion is achie ed by AC/DC PFC cell. The p oposed app oach o e s he ollowing ad an ages: smalle size passi e componen s, lowe ol age-ampe e a ing o DC/DC s age, and highe e iciency. Simula ion esul s demons a e he capabili y o he p oposed scheme. powe gui Con inuous Vol age Measu emen + - Se ies RLC B anch 3 Se ies RLC B anch 2 Se ies RLC B anch 1 Scope7 Scope6 Scope5 Scope4 Scope1 R5 R1 Mos e 1 g m D S Mos e g m D S Linea T ans o me 1 12 Linea T ans o me 12 Fuzzy Logic Con olle Diode 6 Diode 5Diode 4 Diode 3 Diode 2 Diode 1Diode De i a i e du/d i +- Cu en Con olle I e Ia g 100 Cons an 1 70 Add2 Add AC Vol age Sou ce POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 76 Fig. 9: Sou ce ol age & cu en . Fig. 10: Ou pu cu en . Fig. 11: Ou pu ol age. Re e ences [1] RAY, F. W.; DAVIS, M. R. The de ini ion and impo ance o powe ac o o powe elec onic con e e s. P oc. Eu opean con e ence on Powe Elec onics and Applica ions (EPE). 1989, pp. 799-805. [2] HUBER, L.; ZHANG, J.; JOVANOVIC, M. M.; LEE, C. F. Gene alized opologies o Single-s age inpu -cu en -shaping ci cui s. IEEE T ans. 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A single-s age powe - ac o -co ec ed AC/DC con e e . IEEE T ans. Powe Elec on. No embe 1999, ol. 14, pp. 1046–1055. ISSN 0885-8993. [9] JIANG, Y.; LEE, C. F. Single-s age single-phase pa allel powe ac o co ec ion scheme. In: P oc. PESC’94. 1994, pp. 1145– 1151. ISBN 0-7803-1859-5. [10] TABISZ, A. W.; JOVANOVI, M. M.; LEE, C. F. P esen and u u e o dis ibu ed powe sys ems. In: P oc. IEEE Appl. Powe Elec on. Con . 1992, pp. 11-18. ISBN 0-7803-0485-3. [11] SURANYI, G. The alue o dis ibu ed powe . In: P oc. IEEE Appl. Powe Elec on. Con . 1996, pp. 104-110. ISBN 0-7803- 2482-X. [12] MIWA, A. B.; OTTEN, M. D.; SCHLECHT, F. M. High e iciency powe ac o co ec ion using in e lea ing echniques. In: P oc. IEEE Appl. Powe Elec on. Con . 1992, pp. 557- 568. ISBN 0-7803-0485-3. Abou Au ho s SUBBARAO.M was bo n in 1982. He ecei ed B. Tech om JNTUH in 2000. M. Tech om JNTUA in 2007. He is cu en ly pu suing he Ph.D. Deg ee a JNTU college o Enginee ing, Kakinada. His esea ch in e es s include Powe Elec onics and D i es. Sai BABU.Ch ob ained Ph.D. Deg ee in Reliabili y S udies o HVDC Con e e s om JNTU, Hyde abad. Cu en ly he is wo king as a P o esso in Dep . o EEE in Uni e si y College o Enginee ing, JNT Uni e si y, Kakinada. His a eas o in e es a e Powe Elec onics and D i es, Powe Sys em Reliabili y, HVDC Con e e . SATYANARAYANA.S, ob ained Ph.D. Deg ee in Dis ibu ion Au oma ion om JNTU college o Enginee ing, Hyde abad. His esea ch in e es s include Dis ibu ion Au oma ion and Powe Sys ems. SOBHAN.P.V.S was bo n in 1977. He ecei ed M.E Deg ee om AU, Vishakapa nam in 2002. He is cu en ly pu suing he Ph.D. Deg ee a JNTU college o Enginee ing, Kakinada.