RF graphene oscillators for biomedical applications

Universidade do Minho Escola de Engenharia Vitor Filipe Henriques da Silva RF graphene oscillators for biomedical applications Janeiro de 2025 Universidade do Minho Escola de Engenharia Vitor Filipe Henriques da Silva RF graphene oscillators for biomedical applications Tese de Doutoramento Engenharia Biomédica Trabalho efetuado sob a orientação do(a) Professor Doutor Paulo M. Mendes Professor Doutor João Pedro S. H. A. Alpuim Janeiro de 2025 i Direitos de autor e condições de utilização do trabalho por terceiros Este é um trabalho académico que pode ser utilizado por terceiros desde que respeitadas as regras e boas práticas internacionalmente aceites, no que concerne aos direitos de autor e direitos conexos. Assim, o presente trabalho pode ser utilizado nos termos previstos na licença abaixo indicada. Caso o utilizador necessite de permissão para poder fazer um uso do trabalho em condições não previstas no licenciamento indicado, deverá contactar o autor, através do RepositóriUM da Universidade do Minho. Licença concedida aos utilizadores deste trabalho Atribuição-NãoComercial CC BY-NC https://creativecommons.org/licenses/by-nc/4.0/ ii Agradecimentos O alcançar desta etapa é fruto de um longo caminho de aprendizagem, dedicação e superação. No entanto, esse caminho não teria sido possível sem o apoio, a orientação e o incentivo de muitas pessoas que estiveram ao meu lado durante esta jornada. Não podia iniciar estes agradecimentos sem realçar a insubstituível importância da minha família na minha vida. Aos meus pais, Angelina e Henrique, agradeço-vos por todo o amor que me dedicaram e por toda a educação que me proporcionaram. Obrigado por me apoiarem em todas as fases da minha vida. Se sou o que sou hoje, a vocês o devo. Ao meu irmão, agradeço por me ter ajudado e apoiado sempre que precisei. Agradeço também à Inês, por ter caminhado ao meu lado, pela sua paciência, compreensão e apoio nos momentos mais difíceis. O meu percurso até aqui foi conseguido através de todo o vosso suporte. Ao Professor Doutor Paulo Mateus Mendes, orientador desta tese, o meu muito obrigado pelo referencial humano e profissional, por toda a sua disponibilidade, paciência, cuidado e conhecimento transmitido ao longo destes anos. Obrigado por me ter desafiado de forma constante, por me questionar das opções tomadas, por todas as discussões, partilha de conhecimento e experiência, que me ajudaram a evoluir, a refinar o meu pensamento crítico e a desenvolver esta tese. A sua orientação foi essencial para o meu crescimento académico e pessoal. Ao Professor Doutor João Pedro dos Santos Hall Agorreta de Alpuim, co-orientador desta tese, obrigado por ser uma fonte de motivação e incentivo ao longo dos últimos anos. A sua dedicação, orientação, profissionalismo e colaboração fizeram com que todo o trabalho decorresse de forma harmoniosa, o que me permitiu investigar de forma aprofundada a temática deste trabalho e possibilitou a melhoria constante dos resultados. Ao Doutor Jérôme Borme, pela disponibilidade constante em discutir e apoiar nos processos de fabrico de sala limpa, pela sua amizade, profissionalismo e experiência, o meu sincero agradecimento por todas as horas dedicadas de apoio a este trabalho. Aos meus amigos e colegas de laboratório de Gualtar e do INL (Laboratório Ibérico Internacional de Nanotecnologia), agradeço o bom ambiente de trabalho e todos os momentos de partilha, discussão e entreajuda. Agradeço também de forma especial a todos que, de alguma forma, contribuíram com o seu conhecimento para a realização deste trabalho. iii Ao Hugo e Ivo, o meu especial agradecimento por todos os momentos de discussão, pela vossa amizade e companheirismo. Obrigado por terem sido figuras presentes que me incentivaram, encorajaram e apoiaram desde o início. A todos os demais amigos e familiares, que me apoiaram e acompanharam ao longo dos últimos anos, sei que estão muito satisfeitos por me verem chegar à meta e, por serem as pessoas fantásticas que são, expresso aqui também a minha gratidão. À Universidade do Minho e ao INL, por todo o suporte institucional ao desenvolvimento deste trabalho, pela disponibilização de recursos materiais e logísticos, pelo apoio de todos aqueles que fazem parte destas instituições, por me acolherem e proporcionarem todas as condições necessárias ao desenvolvimento e conclusão deste trabalho, o meu profundo e sincero agradecimento. Por fim, agradeço à Fundação para a Ciência e Tecnologia (FCT), pelo financiamento através das bolsas SFRH/BD/137529/2018 e COVID/BD/153232/2023, cofinanciadas pelo FSE através do Programa Operacional Regional. Finalizo este trabalho convicto de que o caminho académico não é apenas sobre a obtenção de um grau académico, mas sobre o crescimento pessoal e intelectual ao longo desse caminho. Que este trabalho seja uma pequena contribuição de conhecimento e que as aprendizagens que me proporcionou continuem a inspirar-me para desafios futuros. iv Statement of integrity I hereby declare having conducted this academic work with integrity. I confirm that I have not used plagiarism or any form of undue use of information or falsification of results along the process leading to its elaboration. I further declare that I have fully acknowledged the Code of Ethical Conduct of the University of Minho. v Resumo O grafeno, um material com estrutura atómica e com propriedades excecionais, tem despertado interesse na comunidade académica. Com uma elevada mobilidade de portadores, excelente condutividade térmica e características eletrónicas notáveis, o grafeno apresenta um enorme potencial para aplicações em eletrónica de radiofrequência (RF). Contudo, a integração deste material em dispositivos eletrónicos apresenta desafios, especialmente na adaptação dos processos convencionais de fabrico CMOS ( Complementary Metal-Oxide-Semiconductor ). Esta tese aborda esses desafios, avançando no desenvolvimento de métodos de desenho, fabrico e caracterização de transístores e osciladores de RF baseados em grafeno, com especial enfoque em aplicações biomédicas. Para melhorar o desempenho dos transístores de RF fabricados, foram implementadas várias estratégias, como a utilização de gates enterradas para reduzir a resistência da gate , a minimização da resistência de acesso através de um processo Damascene adaptado, o uso de substratos de silício de alta resistividade com camadas de SiO2 para mitigar efeitos parasitas e a integração de camadas finas de óxidos com elevada constante dielétrica (alumina) depositados por deposição de camada atómica (ALD). Duas metodologias de fabrico distintas foram desenvolvidas: um processo de gate traseira sem planarização da superfície e um processo de gate enterrada com planarização, utilizando ion milling antes da transferência do grafeno. Estas metodologias foram adaptadas às condições da sala limpa do Laboratório Ibérico Internacional de Nanotecnologia (INL), para aumentar a repetibilidade dos processos, uma vez que são baseados em processos padrão. Adicionalmente, os processos de síntese e transferência do grafeno foram estudados. Nesta tese, fabricaram-se transístores com frequências de corte e frequências máximas de oscilação de 80 GHz e 14 GHz, respetivamente. Estes dispositivos foram modelados através de um modelo semi-empírico. Embora não tenha sido fabricado um oscilador de anel de RF baseado em grafeno totalmente funcional, as simulações realizadas com base no modelo permitiram estudar e otimizar os parâmetros necessários para o desenvolvimento de dispositivos funcionais no futuro, demostrando a efetividade do processo de fabrico para a sua utilização em biossensores de grafeno. Assim, esta tese estabelece um processo de fabrico repetível e adaptável a outros dispositivos baseados em grafeno, lançando as bases para a integração deste material em sensores biomédicos e tecnologias de radiofrequência. Palavras-chave: grafeno, osciladores em anel de grafeno, radiofrequência, transístores de radiofrequência de grafeno vi Abstract Graphene, a single-atom-thick carbon material arranged in a honeycomb lattice, has gained significant attention due to its exceptional electronic, thermal, and mechanical properties. With high carrier mobility, superior thermal conductivity, and remarkable electronic characteristics, graphene has immense potential for electronic and radiofrequency (RF) applications. However, integrating graphene into practical devices presents substantial challenges, particularly in adapting conventional Complementary Metal-Oxide-Semiconductor (CMOS) fabrication processes to accommodate its unique properties. This thesis addresses these challenges by advancing the design, fabrication, and characterization of graphene-based RF transistors and oscillators, with a focus on biomedical applications. Strategies to enhance the performance of the fabricated RF graphene transistors included implementing buried gates to reduce gate resistance, minimizing access resistance using an adapted damascene process, using high-resistivity silicon substrates with SiO2 layers to mitigate parasitic effects, and integrating thin high-k oxide (alumina) layers grown via atomic layer deposition (ALD) for improved gate control. Two distinct fabrication methodologies were developed: a bottom-gate process without surface planarization and a planarized buried bottom-gate process using ion milling prior graphene transfer. These methodologies were adapted to the cleanroom conditions of the Iberian International Nanotechnology Laboratory (INL) to enhance process repeatability, as they are based on standard processes. Additionally, the graphene synthesis and transfer processes were optimized, prioritizing continuous graphene films over large flakes to ensure scalability and uniform device performance. In this work intrinsic cutoff frequencies of up to 80 GHz and maximum oscillation frequencies of 14 GHz using planar buried gate devices with a 5 nm oxide layer were achieved. These fabricated devices were modelled by a semi-empirical model. Although a fully operational graphene-based RF ring oscillator was not fabricated, simulations supported that further optimization of parameters could lead to designs that sustain oscillation in the future, demonstrating the effectiveness of the fabrication process for its application in graphene biosensors. In short, this thesis provides a repeatable fabrication process adaptable to other graphene-based devices, laying the basis for integrating graphene into advanced biomedical sensors and RF technologies. Keywords: graphene, graphene ring oscillators, RF graphene transistors, radiofrequency xiii gate in air to form an Al2O3 layer after the PMMA resist removal. (d) Self-aligned source and drain contacts fabrication by the deposition of Pd. e) Diagram of the final GFET. f) Cross-section of the final device. Figure 26 – a) Silicon wafer with transferred graphene on top. b) Photograph of fabricated graphene devices. c) Artificial color SEM image of a self-aligned graphene transistor with multi-gate configuration. d) SEM image of the transistor channel [53]. Figure 27 – Fabrication flow of a self-aligned graphene FET, reported in [60]. In a) is shown the deposition of gold on top of graphene, b) shows the patterning of the resist for a T-shaped gate, c) shows the etching of the gold under the gate, d) shows the deposition of 2 nm of Al, which is self-oxidized to Al2O3, forming the gate oxide, e) shows the deposition of Al to form the gate contact, and f) shows the cross section of the final device. Figure 28 – Multiple-gated GFET with natural oxide of aluminum [61]. a) 3-D schematic of the fabricated device. b) SEM image of the multi-gated transistor. Figure 29 – SEM image of the fabricated multiple-gate transistor on top, and cross section of the device on the bottom, reported in [62]. Figure 30 – a) Cross section of dual-gate GFET structure. b) Optical microscope image of the fabricated GFET [115]. Figure 31 – Schematic diagram of the fabrication process reported in [63]. a) Etching of the buried gate. b) Ti/Au deposition. c) ALD deposition of Al2O3 and graphene transfer. d) Source and drain contacts definition. e) Growth of the top-gate dielectric by ALD. f) Top-gate fabrication [63]. Figure 32 – Schematic of the fabrication process reported in [64]: a) RIE of bottom part of the T-gate. b) Filling the trenches with Cu and planarization with CMP. c) and d) Similar process of a) and b) to form the top gate. e) Growth of 10 nm of Al2O3 by ALD to form the gate oxide. f) Monolayer graphene transfer. g) Deposition of the metal contacts and graphene patterning. Figure 33 – Images of the graphene transistors reported in [64]: a) SEM image of the cross-section of the embedded T-gate. b) Optical micrograph of the device. Figure 34 – Schematic of the fabrication flow of the fabricated devices: a) 30 nm Au/graphene on Si substrate. b) trilayer photoresist for T-gates patterned by E-beam lithography. c) Gold film under the Tgates etched away. d) Ti/Au deposited on top as the gate metal after the deposition of the gate dielectric by ALD (Al2O3). e) Lift-off to fabricate the final devices. f) Photograph of the transferred graphene with Au. g) photo image of the patterned silicon wafer with the patterned GFETs [65]. Figure 35 – Images of the GFETs reported in [65]: a) SEM image of a dual-gate GFET. b) FIB (Focused Ion Beam) image of the cross-section of the GFET. xiv Figure 36 – Back-gated GFET with h-BN gate dielectric: a) Schematic of the atomic structure of the graphene and h-BN. b) optical image of an exfoliated h-BN flake. c) AFM image of h-BN with different layer thickness. d) optical image of GFET. e) Cross-section schematic of the back-gate device structure [90]. Figure 37 – a) to d) Fabrication steps of the BN/graphene/BN FETs. e) Optical image of a bilayer graphene flake exfoliated and transferred on top of the h-BN substrate. f) Optical image of the final device. g) Optical micrograph of the final device. h) SEM image of the final device [66]. Figure 38 – Schematic illustration of the fabrication steps of the top-gated graphene transistor [67]. Figure 39 – Self-aligned graphene transistors reported in [67]. a) Optical image of the assembled nanowire array. b) Optical image of GFETs and c) Zoom in of b) in one GFET. d) SEM image of GFETs showing the channel and the gate nanowire. Figure 40 – Illustration of the fabrication of self-aligned graphene transistors with transferred gate stacks reported in [49]. Figure 41 – The self-aligned GFETs: a) Photo image of the final devices on a glass substrate. b) Optical image of the GFETs. c) SEM image of the channel of the GFET. d) TEM image of the cross section of the final device [49]. Figure 42 – Diagram of the two main processes reported in this thesis with and without planarization, a) and b) respectively. In a) i) HR silicon wafer with chromium + gold and alumina on top; ii) e-beam lithography to define source, drain and gate contacts by ion milling; iii) device after ion milling; iv) e-beam lithography to define the gate oxide after the growth of fresh alumina by ALD (after the resist removal by O2 plasma, and alumina by wet etch); v) result after the patterning of the gate oxide by ion milling; vi) final device with graphene. b) i) device after e-beam lithography and ICP RIE; ii) after the chromium gold deposition; iii) after the lift-off, showing the ears to be removed by ion milling, to planarize the device; iv) after the graphene transfer; v) after the e-beam lithography and copper + gold deposition to define the source/drain electrodes by lift-off; vi) final device Figure 43 – First steps of the fabrication process with a) and b) showing an optical image of the lithography and c) and d) showing the optical micrograph after the ion milling and the resist removal by an O2 plasma. Figure 44 – a) and b) show an optical image of the lithography performed to pattern the gate dielectric (alumina) and c) and d) shows the optical image after the ion milling. To note, since the gate is very thin, some e-beam resist was left to act as anchor of the e-beam resist responsible for the patterning of the gate dielectric. Figure 45 – a) and b) Optical photograph of the device after the resist removal with the oxygen plasma. Figure 46 – Optical image of the graphene laying in the channel of the device. xv Figure 47 – Microscope image of the patterned substrate with the graphene flakes (a) and Vgs vs IDS and 𝑔𝑚 characteristic curves of devices presented in that substrate with W = 35.6 µm and L = 1.19 µm (b) and (c). Figure 48 – SEM images of graphene after the transfer. a) after the transfer without the patterning, b) after the patterning with graphene following the topography of the contacts, c) and d) suspended graphene patterned and dried on air evidencing the cracks and e) and f) after the patterning and dried with critical point dryer. Figure 49 – SEM images of the gate structures showing the metal ears a) and after the planarization b). c) Profilometer measurement of the gate after the planarization. Figure 50 – a) and b) optical image of different graphene patterns used in graphene to reduce the contact resistance, c) optical image of the final device and d) SEM image of the final device showing graphene without cracks. Figure 51 – Different types of the fabrication structures, a) single gate transistor, b) inverter, c) ring oscillator with variable graphene capacitors through back gate and compact ring oscillator, e) SEM image of an inverter after the electrical measurement showing the contact pads scratched or damaged, f) SEM image of the compact ring oscillator, g) SEM image of the channel of the inverter and h) microscope image of the clean graphene laying in a gate of a device prior the deposition of the remaining contacts (in this case an inverter). Figure 52 – Raman spectra of the monocrystalline graphene used in the fabricated devices, a) Raman spectra sites and b) Raman spectra at 532 nm intensity laser. It is possible to evaluate the correct patterning since out of the graphene channel there is no graphene signature. Figure 53 – a) General fabrication process of the single layer graphen continuous film. b) graphene on copper and c) carbon chunk on top of the graphene arising from contaminations in the graphene furnace. Figure 54 – Picture of the sapphire mounted over the treated copper foil. Figure 55 – General scheme of the graphene flake growth. Figure 56 – Evolution of graphene flakes with the increasing of Hydrogen (𝐻2) flow. Figure 57 – Evolution of graphene flakes with the increasing of methane (𝐶𝐻4) flow. Figure 58 – Images of graphene flakes on copper after the oxidation on a hotplate a) optical microscope and b) photograph of the copper foil. Figure 59 – Different Raman graphene peaks for a laser excitation of 532 nm [129]. xvi Figure 60 – Raman spectra of single layer graphene and bulk graphite at a 532 nm laser [131]. Figure 61 – A linear increase in G band intensity occurs as the number of graphene layers increases, with a 532 nm laser. Adapted from [132]. Figure 62 – Relationship between 2D peak and G peak for single layer graphene. Adapted from [132]. Figure 63 – a) Raman spectra a graphene flake on a copper foil and b) Raman spectra at 532 nm of the flake. Figure 64 – Contaminated CVD furnace. The black portions are carbon chunks that resulted from CNT growth. Figure 65 – Graphene cracks and PMMA residues [144]. Figure 66 – Large-signal model equivalent circuit. CPGS, CPDS, LG, LD, and LS are parasitic capacitance values and inductances. RG is the gate resistance, and RS and RD are the source and drain resistances including contact and access resistances. Adapted from [146]. Figure 67 – Major carrier type in the graphene channel at different bias voltages. Figure 68 – Small-signal model after de-embedding the parasitic elements at 𝑉𝐺𝑆=𝑉𝐷𝑖𝑟𝑎𝑐. Adapted from [147]. Figure 69 – Two-port system equivalent circuit from the Y-parameters (left) and Z-parameters (right). Figure 70 – De-embedding equivalent circuits. Device under test (left), Short (center) and Open (right). Figure 71 – Measurement setup used to extract the FOMs of the GFETs. Figure 72 – VGS vs IDS and 𝑔𝑚 characteristic curves of a device with W = 39 µm and L = 1.100 µm (0.95 µm of gate channel and 0.075 µm of drain/gate and source/gate overlap) measured at a VDS of 100 mV. Figure 73 – a) S-parameters of a device with W = 39 µm and L = 1.100 µm and a La (access length) of 85 nm and respectively fT and fmax b). c) RF measurement scheme used to measure the devices. Figure 74 – Evolution of the fT and fmax with the variation on access length. Figure 75 – Transfer curves of a device with L = 1.102 μm and W = 33.82μm. a) VGS vs IDS curve for a VDS of 10 mV and b) Curves of VGS vs IDS for different VDS and c) curves of VDS vs IDS for different VGS. Figure 76 – RF performance of the de-embedded devices. H21 and MUG of a device with an L = 1.101 µm a) and c) of a device with a L = 1.136 µm and a La of 54.35 nm. b) and d) SEM images of the respective devices showing the measurements of the channel length and access length. Device d) shows xvii a small misalignment in between the drain and gate. The fmax and fT of a) are 11 GHz and 44 GHz respectively and in c) are 14 GHz and 80 GHz respectively. Figure 77 – a) Inverter schematic with GFET. b) Equivalence of the fabricated device with the schematic shown in a) c) Measurement of a graphene inverter with a VDD of 8V showing a Vout of 500 mV of amplitude swing (channel 2) for a Vin of 1V swing centered in 5.7 V. Figure 78 – RF graphene mixer and frequency doubler. a) circuit of the graphene mixer and b) expected output spectrum. c) Measured RF spectrum of the graphene mixer and d) output spectrum of the frequency doubler for an input signal with a frequency of 3 GHz at 0 dBm. Figure 79 – Simulated vs measured IDS vs VGS of the transistor. Figure 80 – Simulation of an inverter with the extracted parameters. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 0.7 and c) response of the inverter to a 10 kHz square wave. Figure 81 – Simulation of the inverter by reducing the Rext0 to 10. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 0.8. Figure 82 – Simulation of the inverter by reducing the Ro to 40. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 2.7. Figure 83 – Simulation of the inverter by reducing shifting the VDirac to VDirac+0.3. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 2.8. Figure 84 – Ring oscillator assessment. Simulation of the optimized inverter (a) and ring oscillator simulation (b). xviii LIST OF TABLES Table 1Comparison between the performances of the reported transistors. ...................................... 26 Table 2Contact resistivity (Adapted from [104]) ............................................................................... 34 Table 3Equations of intrinsic and extrinsic drain-source resistances ................................................. 77 Table 4 - Extracted parameters from the model by using the previous transistor. ................................ 91 Table 5Parameters used for the inverter and in the ring oscillator simulation.................................... 95 1 1 INTRODUCTION Graphene is a 2D material with a one-atom-thick layer of carbon in a honeycomb lattice. Its discovery has caused an increase in the number of studies where its synthesis, physical properties, and electrical properties were analysed. The advances in those areas allowed for the exploitation of graphene’s properties for its integration and improvement of electrical circuits [1]. Moreover, the development of large-scale synthesis methods such as Chemical Vapour Deposition (CVD) has allowed for an increase in the number of research findings and has made commercial applications possible. Graphene’s exceptional electrical and mechanical properties make it particularly suitable for biomedical applications. It also exhibits excellent adsorption capabilities, enabling the development of biosensors that quantify adsorbed molecules by detecting changes in graphene’s properties [2]. Given graphene's exceptional mechanical properties, it is possible to fabricate flexible sensors, as will be discussed later. Despite these advantages, integrating graphene-based devices with CMOS (Complementary Metal-Oxide-Semiconductor) technology remains challenging due to its distinctive material properties. Many conventional CMOS fabrication processes cannot be directly applied to graphene, complicating efforts to incorporate features such as RF communication or analyte quantification through frequency changes in devices. Given the previous considerations, this thesis focuses on developing a graphene-based oscillator for biomedical applications. This could range from a ring oscillator (RO), a resonant oscillator or a MEMS structure. The proposed design should be fully compatible with the International Iberian Nanotechnology Laboratory (INL) cleanroom, aligning with the standardized processes employed in most research laboratories worldwide. 1.1 Biomedical devices The investigation and application of biomedical devices have indeed witnessed tremendous growth over the past years, particularly with the advent of various technologies aimed at enhancing patient care and monitoring. Wearable devices, flexible electronics, on-body systems, and miniature devices, along with remote charging, wireless power transfer systems, have emerged as pivotal innovations in this field. Wearable devices have gained significant traction due to their ability to monitor various physiological indicators continuously and non-invasively, allowing users to track their health without disrupting their 2 daily activities. For instance, Wang et al [3] developed a wearable device capable of simultaneously monitoring electrocardiogram (ECG) signals and counting physical activities in cardiovascular patients. This device has proven effectiveness in clinical practice, facilitating early detection of arrhythmias and enabling timely interventions to mitigate complications associated with severe cardiovascular diseases [3]. This device as well as the example of application can be seen in Figure 1 a). Similarly, Susana et al [4] introduced a non-invasive device that uses photoplethysmography sensors to monitor blood glucose levels, significantly improving the quality of life for diabetic patients by eliminating the need for frequent finger pricking. The continuous monitoring capabilities of these devices underscore their importance in modern healthcare, particularly for chronic disease management [4]. The evolution of flexible biomedical devices has further enhanced the comfort and sustainability of wearable technologies. Recent advancements in materials science have led to the development of flexible electronics using biocompatible polymers and conductive materials such as doped graphene. As reported in [5] the graphene could be used as a stretchable material to detect temperature, pressure, and metabolites in sweat, demonstrating its potential of this material for personalized health monitoring. In [6], the authors reported the development of a wireless and flexible biosensor patch designed for continuous, longitudinal monitoring of multiple physiological signals, including body temperature, blood pressure, and electrocardiography. The patch was engineered to be highly compatible with the skin, featuring optimized flexibility and mechanical stretchability to ensure durable and comfortable attachment, even on curved surfaces as can be seen in Figure 1b). The flexibility of these devices is crucial for ensuring accurate skin contact and comfort during use, which is essential for effective health monitoring. On-body devices have revolutionized continuous, non-invasive patient monitoring by integrating seamlessly with the human body. The trend towards miniaturization has enabled the development of smaller, lighter, and more comfortable devices that maintain high accuracy in monitoring functions. For instance, the pacemaker, an implantable medical device, has been miniaturized to less than the size of a coin, allowing for direct implantation into heart tissue [7], as can be seen in Figure 1 c). Hassan et al [8] further exemplified this trend with an implantable glucose sensor (LC tank resonator) that provides continuous monitoring for diabetic patients, transmitting data wirelessly [8]. This miniaturization not only enhances patient comfort but also increases adherence to treatment regimens. One of the significant challenges in the realm of implantable devices is the need for battery replacements, which can need invasive procedures. Innovations in wireless power transfer technologies have addressed this issue. Laughner et al [9] reported a wireless implantable pacemaker in mouses which could pave the way for eliminating the need for surgical battery replacements and allowing for continuous monitoring from within the body [9]. Additionally, Heo et al [10] developed a wireless deep 3 brain stimulation device for Parkinson’s disease rodents, powered through inductive coupling, which reduces the need for surgical revisions and enhances patient comfort [10] . The device could be seen in Figure 1 d). These advancements highlight the transformative potential of wireless technologies in improving the functionality and usability of biomedical devices. Given that, the recent advancements in biomedical devices, particularly in the areas of wearables, flexibility, miniaturization, and wireless power, signify a remarkable evolution in healthcare technology. These innovations are not only enhancing the accuracy and personalization of health monitoring solutions but are also paving the way for proactive healthcare management. Ongoing research into new materials, miniaturization techniques, and wireless power technologies promises to further revolutionize the field, ultimately leading to improved patient outcomes and a more integrated approach to health management. 4 Figure 1 – Examples of biomedical devices a) Wearable intelligent ECG monitoring system. Adapted from [3]. b) Design and mechanical properties of flexible biosensor patch. Adapted from [6] c) pacemaker device. Adapted from [7] d) wireless deep brain stimulation device for Parkinson’s disease rodents. Adapted from [10]. 1.2 Oscillators and graphene technology The integration of graphene into sensor technology has transformed research across various fields, including healthcare, environmental monitoring, and smart materials. Graphene has become a very attractive material due to its properties. It is a single sheet of 𝑠𝑝2-bonded carbon, zero-gap semiconductor with a high conductivity. When compared to copper with the same thickness (though achieving such thinness with copper may not be feasible), it has got a lower resistance and can sustain a higher current density than any other known material [1]. For electronic applications, its key property is its high carrier mobility, with suspended graphene reaching mobilities up to 200000 cm2 V-1 s-1 [11], while silicon has got an electron mobility of 1400 cm2 V-1 s-1 [12]. This property makes the graphene a suitable material for radiofrequency (RF) applications [13] The reported devices range from transistors with measured intrinsic cut-off frequencies (fT) of up to 300 GHz, and with applications on low-loss interconnects and passives [14][15]. These unique electrical properties, along with mechanical strength, and flexibility, make it an ideal candidate for sensor applications [16], including pressure sensing, strain detection, and physiological signal monitoring. For instance, Yang et al. [17] demonstrated a wearable graphene strain sensor capable of precise pulse wave monitoring [17]. Similarly, Xie et al. [18] reported on the detection of physiological signals using graphene, emphasizing its potential in health monitoring systems [18]. However, while graphene-based sensors rely on the graphene as the sensing material, they often rely on CMOS chips for RF communication for data transmission as can be seen in the device reported in [19]. This need reveals a significant gap in current technology, emphasizing the importance of developing RF graphene devices, particularly RF graphene oscillators, for sensing or communication. Achieving a fully graphene-based sensor requires a unified and compatible fabrication process. Relying on CMOS integration with graphene, which is being done by the research community [20], can increase device complexity and costs, and it may even degrade performance since the standard RF components used in CMOS might not be optimized for graphene's unique characteristics. By using the resonant 11 Figure 4 – a) Output signals of buffered graphene ROs reported in [25], at VDD = 3.5V b) Power spectrum of the medium and small ROs. In [27], another similar ring oscillator was presented. In that work, nine different ring oscillators were made, with nine different gate lengths, from 0.5 µm to 3.3 µm while varying the channel width, access length, and source and drain contact thickness at the same time. The shortest achieved gate delay was 31 ps, at a gate length of 0.9 µm. This value is smaller than the CMOS transistors with the same gate length. This delay allowed the authors to fabricate the fastest graphene ring oscillator reported to date, running at 4.3 GHz. It was possible to obtain this value since a high voltage gain (Av » 5) was achieved. For that work, graphene monolayers were grown by CVD on copper foil. A 4 nm thick film of aluminium was evaporated on top of graphene to be oxidized, to form the gate dielectric. The ring oscillators, which require low or zero back-gate voltage, were operated at room temperature while the ones that require large back gate voltages (VBG > 50 V) were operated on air under an N2 flow (to stabilize the position of the Dirac point at 0). In that work, the ROs made with inverters with L < 0.8 µm do not oscillate. The authors found that the gain of the stages decreased from 5 to approximately 2. This occurred due to the contact and access resistance, which do not scale with the gate length. At short gate lengths, these resistances become comparable to the channel resistance and therefore suppress the voltage gain. The fabricated devices can be seen in Figure 5. 12 Figure 5 - Fabricated ring oscillators (ROs) in [27]. a) 3D view of a buffered three-stage graphene RO. b) Circuit diagram of the three-stage ring oscillator. c) and d) SEM image of the fabricated RO. e) SEM image of an GFET in a RO [27]. Another work that presents a graphene ring oscillator is reported in [28]. In that publication, the authors not only made a fully graphene ring oscillator but also tried to incorporate some CMOS circuits to prove the compatibility of the two technologies. They proposed a novel class of graphene-Si CMOS circuits that exploit the ambipolarity of graphene, to simplify the circuit and provide additional functionality to them. The authors implemented a ring oscillator fabricated only with graphene, a Si CMOS D latch, and a timing RC circuit. The objective of the D latch is to provide switching and large voltage swing to control the GFET, while the RC circuit is used to set the oscillation frequency. The maximum obtained oscillation frequency was 4.2 MHz. The authors claimed that the ambipolarity of the graphene allows for the accomplishment of pulse-width modulators (PWMs) and voltage-controlled oscillators (VCOs) from the same circuits, i.e., without any circuit modification. The top gated GFETs were made with CVD grown graphene transferred to a SiO2/Si substrate on which h-BN was previously exfoliated. The h-BN was used since the authors believe that the GFETs fabricated on top of this substrate are more stable (with the same electrical properties over time), than the ones fabricated directly on top of the SiO2 substrates. A 4 nm thick gate dielectric made of Al2O3 was obtained after oxidizing an evaporated Al film directly on top of graphene. To perform the study reported earlier, this device was connected to the silicon circuits that are assembled on a breadboard or in printed circuit boards. These circuits will not be addressed in this report, since only the layout of the ring oscillator and its performance are important for this work. The implemented graphene RO can be seen in Figure 6. 13 Figure 6 – Graphene oscillator fabricated on top of an h-BN flake, with five GFETs reported in [28]. In [29] a graphene ring oscillator based on high performance inverters were reported. The oscillation frequency of such devices was in the range of dozens of MHz, demonstrating an effective method for fabricating RF graphene transistors. However, this approach may not be suitable for certain applications due to the low oscillation frequency. The optical micrograph of the ring oscillator can be seen in Figure 7. Figure 7 – Optical micrograph of a ring oscillator with false color annotations highlighting the various circuit elements. The scale bar represents 10 mm. Source and drain contacts are shown in blue, the local back gate. 2.2 Resonant oscillators and MEMs oscillators Ring oscillators are not the only kind of oscillators where graphene could be important. Graphene is also important in some MEMS (Microelectromechanical Systems) structures or LC tanks. In [30], a tantalum disulfide-boron nitride-graphene device was developed. In that oscillator, the boron nitride was used to protect the device against oxidization, maintaining the phase of the generated wave. A GFET was fabricated to control the oscillation frequency of the oscillator, which in this case is a voltage-controlled 14 oscillator (VCO). The oscillation frequency of the device could be adjusted by changing the gate voltage of the device. The illustration and the SEM image of the fabricated device can be seen in Figure 8. Figure 8 – SEM image of the VCO fabricated with graphene and 1T-TaS2, highlighted in the figure, and reported in [31]. In [32] another GFET based oscillator was presented. This device is based on a resonator nanoplate of aluminium nitride. A graphene membrane was placed on top of this structure obtaining an oscillation frequency of 245 MHz. The working principle of this device is similar to the reported before. The illustration and the SEM image of the fabricated device are shown in Figure 9. Figure 9 – Aluminium nitride nanoplate resonator with graphene: a) schematic illustration of the structure of the proposed device, and b) SEM image of the device reported in [32]. It is important to note that RF transistors can also be used in LC tanks to compensate for losses during oscillations. In this context, academia has been focusing on this material, as demonstrated in [33], where the authors proposed the first algorithm for analysing such circuits. This development could pave the way for the integration of this technology into LC tanks and sensors. In Figure 10 it is possible to observe the schematic of the proposed GFET based LC-VCO. 15 Figure 10 – Schematic of the proposed GFET based LC-VCO on the left, and cross-section of the GFETs on the right [33]. 2.3 Other types of oscillators Transistor-based oscillators are not the only type of oscillators that can be fabricated. Graphene MEMS-oscillators have been also reported. Similarly to transistors, to evaluate the performance of MEMS oscillators, it is necessary to establish the FOMs. The most used FOM for MEMS oscillators structures are the quality factor (Q) and the resonance frequency (fr) [34]. The quality factor is the ratio between the stored energy in one device and the dissipated energy per resonance cycle, and is given by 𝑄: 𝑄= 𝑓𝑟 𝑓𝑢−𝑓𝑜 (1) where 𝑓𝑟 is the resonant frequency, 𝑓𝑢 is the upper oscillation frequency and 𝑓𝑜 is the lower oscillation frequency, being 𝑓𝑢−𝑓𝑜, also known as Δf. The resonant frequency of an oscillating device generally refers to a particular frequency where the stored kinetic energy and the potential energy are in resonance. Graphene is a suitable material for resonator structures due to its high young modulus and its atomic thickness. These properties enable graphene to achieve resonant natural frequencies of hundreds of MHz and to tolerate high strains without damage. The graphene membrane could be actuated thermally, mechanically or electrically to achieve high oscillation frequencies. In the next few pages, several MEMS devices will be presented. In [35], the authors used graphene foils obtained by mechanical exfoliation and placed them directly on top of trenches previously opened on SiO2 with gold contacts. A general illustration of the fabricated device can be seen Figure 11. 16 Figure 11 – On the left is represented the schematic of the oscillator, and on the right the SEM image of the device, as reported in [35]. These membranes were actuated in 2 forms: electrically and optically. The oscillation frequency of the oscillators varied from 1 MHz to 170 MHz, and the Q changed from 20 to 850. A SEM image of this device is shown Figure 11 on the right. In [36] an on-chip heater for tuning of graphene nanodrums is presented. This heater adjusts the nanodrums properties through the Joules effect. Using a ring structure submitted to thermal expansion, the authors demonstrated that the applied nanodrums voltage control tunes the oscillation frequency. The oscillation frequency of the device is 11.5 MHz. The SEM image of the device and the general operation schematic of the device can be seen in Figure 12. Figure 12 – SEM image of the reported oscillator nanodrums on the left, and schematic diagram of the device on the right [36]. Other non-conventional options to obtain oscillators could consist in using spin-torque nanooscillators. This kind of oscillators are typically more complex, but the great advantage of these structures is the absence of current flowing through the device’s active area. In [37], the authors proposed a method to make spin-orbit torque nano-oscillator based on a single permalloy layer with the thickness in the 1520 nm range, grown on an alumina substrate and caped with silicon dioxide. With this method, the nano- 17 oscillators could achieve frequencies of several GHz. The fabricated device is presented below, in Figure 13. Figure 13 – SEM image of a pemalloy nano-constriction, width of 30 nm [37]. In [38], a 3-terminal spin torque nano-oscillator is presented (STNO), which is based on a magnetic tunnel junction excited by a spin injection mechanism. The combination of the two mechanisms outperforms the use of only one to excite the free layer into dynamic regimes. As a result, high output powers are achieved. The fabricated device is shown in Figure 14. Figure 14 – Optical microscope of the spin-torque nano-oscillator device, showing the MTJ and the spin Hall micro-stripe fabricated in [38]. In [39], a device that combines local injection of a pure spin current with enhanced spin-wave radiation losses is presented. The authors demonstrated coherent auto-oscillations excited by a pure spin current in magnetic nanodevices. Their findings paved the way for the implementation of magnetic nanooscillators based on conducting or insulating materials, without the use of current flowing through the active area of the device. In Figure 15 it is possible to see the device under test in [39]. 18 Figure 15 – SEM image of the device showing its structure and composition, and the measurement scheme, applying a DC current between both contacts, and probing it with a laser light [39]. A skyrmion-based spin-torque nano-oscillator is presented in [40]. The system involves a circular nanopillar with an ultrathin film free magnetic layer with strong Dzyaloshinkii-Moriya interaction and a polarizer layer with a vortex-like spin configuration. The authors showed the appearance of a skyrmion gyration which leads to oscillations of the material. The general schema of the proposed device can be seen in Figure 16. Figure 16 – Skyrmion-based spin-torque nano-oscillator, designed with a nanopillar, with the skyrmion in the free layer, and two different possibilities for the distribution of the magnetic field in the reference layer [40]. 19 2.4 RF Graphene transistors As stated below; to fabricate graphene ring oscillators, it is necessary to fabricate graphene transistors with RF capabilities, since they are the building block of these circuits. In recent years, there has been significant progress in the speed and integration of integrated circuits, primarily due to efforts in downscaling silicon transistors. However, silicon transistors are now approaching their technological limits. To guarantee that electronics technologies are evolving and to ensure that the improvement of the current devices is possible, further research on new materials to replace silicon needs to be undertaken. For this purpose, researchers are putting a big effort into the study of graphene due to its amazing electrical properties such as high saturation velocity and high carrier mobility, which are important for RF electronics. There are several RF graphene active devices reported in the existing literature. Due to graphene’s ambipolar conduction, it is possible to develop non-linear electronics which can be switched from n-type to p-type by adjusting the Fermi´s level through tuning the gate bias. The high carrier mobility and high current saturation velocity of graphene can enable the use of graphene in RF circuits. The difficulty to turn off these devices is a problem for logic applications due to increased power consumption [41], however, in RF applications it does not have a big effect [25]. RF graphene transistors have oscillation frequencies and cutoff frequencies in the tens of GHz range (concepts that will be further addressed later in this document), with some of the reported devices achieving intrinsic cutoff frequencies higher than 300 GHz [15]. Connecting these transistors or polarizing them in particular states enable the design of several RF circuits. One simple example of these can be the ambipolar mixer reported in [42]. More complex RF circuits can be fabricated with graphene, such as ring oscillators. These devices can work above 4 GHz [27] and can be used in biosensors or RF communications. In the field of RF communications, a graphene radiofrequency receiver was developed in [43]. Despite the low availability of graphene to provide power at high frequencies (because of its low saturation current [44]), some RF graphene amplifiers were reported in [45] and [46]. Although graphene isn’t a well-established technology, it is a good candidate to develop RF devices due to its properties. Graphene has a higher electron mobility than silicon, and although CMOS has a higher fT and fmax, it is achieved at twice the current consumption [47]. Nevertheless, GFETs only have a narrow IDS operation window, their performance is limited by its lower 𝑔𝑚 and parasitics, and to exceed the GFETs performance, it is predicted that a mobility higher than 3000 cm2V-1s-1 is required [47]. The performance of RF graphene FETs is commonly evaluated by the cut-off frequency (fT) and the maximum oscillation frequency (fmax). The cut-off frequency (fT), the widest figure of merit for RF graphene 20 transistors, is defined as the frequency at which the magnitude of the small-signal current gain of the transistors is reduced to unity. In general, the cut-off frequency can be defined as described in equation 2 [48]: 𝑓𝑇=𝑔𝑚 2𝜋[(𝐶𝑔𝑠+𝐶𝑔𝑑)(1+(𝑅𝑑+𝑅𝑠)𝑔𝑑𝑠)+𝐶𝑔𝑑𝑔𝑚(𝑅𝑑+𝑅𝑠)+𝐶𝑝𝑔] (2) where 𝑔𝑚 is the transconductance, 𝐶𝑔𝑠 is the gate to source capacitance, 𝐶𝑔𝑑 is the gate to drain capacitance, 𝐶𝑝𝑔is the gate parasitic capacitance, 𝑅𝑠 and 𝑅𝑑 are the source and drain resistance, and 𝑔𝑑𝑠 is the output conductance (conductance between drain and source). The transconductance, 𝑔𝑚, is the slope of the curve 𝐼𝐷𝑆 vs 𝑉𝐺𝑆 with 𝑉𝐷𝑆 constant, as shown in section 4.1.4. The fmax which refers to the frequency when the maximum available power gain becomes unitary. This refers to the ability of the transistor in providing gain, important for example in amplifiers and ring oscillators. Achieving a high fmax is challenging because GFETs are strongly affected by short-channel effects. This is primarily due to the gate capacitance approaching the same order of magnitude as the graphene quantum capacitance, which reduces the ability to modulate the graphene channel effectively. Additionally, the high contact resistance in graphene devices further impairs performance, leading to a loss of control over the channel. Typically, this value is one magnitude lower than the fT GFETs [49]. The fmax can be obtained by: 𝑓𝑚𝑎𝑥=𝑓𝑇 2√𝑔𝑑𝑠(𝑅𝑔+𝑅𝑠)+2𝜋𝑓𝑇𝑅𝑔𝐶𝑔𝑑 (3) where 𝑅𝑔 corresponds to gate resistance, and the remaining variables are the same as in equation 2. By analysing equation 2, to increase the fT it is necessary to increase 𝑔𝑚 or decrease 𝑔𝑑𝑠 and all the parasitic capacitances, by decreasing the gate oxide thickness, for example. Since the 𝑔𝑚 is proportional to the carrier mobility and all 𝑔𝑚, 𝐶𝑔𝑠, and 𝐶𝑔𝑑 are inversely proportional to the channel length, to achieve a big cut-off frequency, fT, it is essential to have a high carrier mobility and a small channel length of the device. However, this is not so simple, since the GFETs are highly affected by the short channel effect due to the quantum capacitance of the material [50]. 27 In Table 1 it is possible to observe the most relevant GFETs and their performances. The silicon MOSFETs were reviewed in [68], and the reported devices can be used to compare the MOSFET’s performance with GFET’s. In [62], the GFET with the highest transconductance is reported, 2 mS/μm in contrast with the highest reported values for n-channel MOSFET of 1.84 mS/μm, or 1.6 mS/μm for pchannel MOSFET [69]. However, a higher transconductance was achieved in 3.45 mS/μm in III-V FETs [70]. When analysing the 𝑓𝑇, the maximum value of 427 GHz was achieved. When compared with the MOSFET devices, this value is near the state of the art, with the highest reported value of 485 GHz [69]. Regarding 𝑓𝑚𝑎𝑥, the highest value was achieved in [65], 200 GHz. When compared with the reported devices in [68] the 450 GHz for an n-channel MOSFET was achieved. This highlights that, despite graphene's potential, further development is required to improve this figure of merit in graphene technology. [66] - 22 - 5 hundre ds of mA 0.25 Top gate Exfoliated graphene Low High [67] - 75 - 55 mA 0.36 Top gate CVD graphene High High [49] 29 427 - - mA 1.33 Top gate CVD graphene High High 28 3 DESIGN AND FABRICATION As discussed in the previous chapters, the design and fabrication of graphene transistors is challenging and requires careful consideration of both the design and fabrication processes. Since transistors serve as the fundamental units of ring oscillators, the oscillator type selected in this thesis, given its suitability for integration with biosensors and other biomedical devices, its fabrication is detailed in this chapter, with a primary focus on the fabrication of RF graphene transistors. Due to the limitations of the INL cleanroom, a trade-off between performance and fabrication capabilities must be considered. This chapter provides a comprehensive overview of the design approaches employed to meet the specifications required for fabricating the building blocks of the ring oscillators, specifically the transistors, while considering the available fabrication processes. Two fabrication processes are proposed and fabricated. It also outlines the strategies used to address the challenges encountered during the fabrication steps. The chapter begins with an exploration of how various design techniques are applied to optimize key parameters to achieve high-performance devices. Additionally, the fabrication of CVD-grown graphene is discussed, along with the challenges and optimization strategies involved in the material's production, since the fabricated graphene were used in the fabrication of the RF graphene devices presented in this thesis. 3.1 Materials and fabrication methods As seen previously, only a few works with graphene oscillators were reported. This is due to the single atomic thickness of graphene which presents significant challenges, since many electronic fabrication processes traditionally used in silicon technology cannot be directly applied to graphene. These conventional processes often damage the graphene lattice, leading to performance degradation. The most critical and challenging step in the fabrication of RF graphene devices is the integration of a high-k dielectric on the graphene surface. Standard fabrication techniques typically damage the graphene lattice, altering its intrinsic properties or, in some cases, destroying it. Furthermore, the fabrication of graphene in a large scale is also challenging. The incorporation of a high-k dielectric is crucial to prevent excessive current leakage due to direct electron tunnelling. High-k dielectric materials enable an increase in the physical thickness of the graphene transistor’s gate dielectrics while preserving the performance characteristics typical of thin SiO₂ layers. To address this challenge, several research groups are exploring innovative solutions, such as the physical gate transfer using core-shell nanowires [71] or the application 29 of thermal tape [72] to transfer pre-patterned structures. Additionally, self-aligned processes are being developed to minimize access resistance and parasitic capacitances, both of which are detrimental to RF performance. The devices fabricated for this thesis were designed to be compatible with the INL cleanroom, as all fabrication steps were performed within these facilities, where parameter tunability is constrained by the requirements of other processes running in parallel in this cleanroom. INL’s cleanroom (that are based on standard large scale fabrication processes), classified as ISO 5 class and spanning an area of 1,200 m², is equipped with cutting-edge tools for microand nanofabrication mainly optimized for 200 mm wafers, supporting applications across fields such as electronics, medical devices, microfluidics, energy, and sensor technologies. Despite the extensive capabilities, adjustments were necessary for graphene processing, as certain cleanroom processes are not fully optimized for graphene applications. For graphene growth, the facility includes an Easytube 3000 CVD system, while material deposition options include several specialized systems. The Kenosistec KS1000 PVD system is equipped with both RF and DC (Direct Current) capabilities, featuring a UHV multi-target setup with 11 magnetrons. This includes 3 RF magnetrons for depositing non-conductive materials and the remaining DC magnetrons for metal deposition, enabling the sputtering of thin films. The SPTS MPX CVD Module is designated for PECVD silicon oxide and silicon nitride depositions. Additionally, thin films such as Al2O3 (alumina) or AlSiCu can be deposited with the Timaris FTM system from Singulus. This machine has the availability to perform RF and DC sputtering (oxide and metals) with a good uniformity (70%) and conformality. The dielectric and amorphous silicon films are deposited using an SPTS PECVD machine, which can produce films in the nanometer to micron thickness range. For dielectric deposition, atomic layer deposition (ALD) is available, although only Al2O3 can be deposited. The system is the ALD Beneq TSF 200, which regarding its modular architecture is ideal for R&D activities, supporting thermal ALD, remote plasma ALD and direct plasma ALD. Lithography processes at INL include mask aligners and a direct-writing lithography (DWL) system from Heidelberg, with available laser beams at λ = 405 nm and λ = 375 nm, which provides significant flexibility for iterative R&D processes by allowing CAD layout exposures. For high-precision nanometerscale work, an electron beam system of Vistec is available, the EBPG 5200 with an operation voltage of 100 kV and 50 kV; however, due to its cost and complexity, it is used sparingly. Supporting lithography, INL offers a priming oven and automatic coaters by Suss MicroTec. A critical point dryer is also accessible within the facility. While INL is compatible for a range of CMOS processes, some limitations for graphene remain, particularly the lack of a gold evaporator, which is commonly needed for creating contacts in graphene 30 devices. Nonetheless, the facility’s equipment supports many aspects of graphene-based RF device fabrication. In the following sections, key considerations in the development of RF graphene devices will be examined in detail with focus in graphene transistors since they are the building block of the ring oscillators which was the selected kind of oscillator to this thesis due to their small size and since the incorporation of graphene transistors with RF capabilities in graphene biosensors could be valuable to implement other kind of RF circuitry (RF mixers, frequency doublers or rectifiers). 3.1.1 Substrate for graphene transistors fabrication The correct choice of the substrate for the graphene transistors fabrication impacts the performance and/or fabrication steps, as well as integration potential. The substrate may be imposed by the fabrication facilities, by the integration methodology required, or by the graphene fabrication and processing steps. Graphene transistors can be fabricated on several substrates, with the most common being Si/SiO2 [73], SiC [74], glass and quartz [75]. Graphene transistors are also reported in flexible substrates such as polyethylene naphthalate (PEN) [76] or polyethylene terephthalate (PET) [77]. These are very useful in nonplanar applications (wearables for example), with their low insertion loss being a good characteristic for THz applications [78]. The most used substrate is Si/SiO2, due to their compatibility with the standard fabrication processes and the easy optical identification of the graphene on SiO2. This property makes these the most suitable substrates for the fabrication of high-quality CVD-grown graphene devices after graphene transfer. The presence of a thick layer of SiO2 on top of the Si substrate makes this substrate also very useful in RF applications, decreasing the parasitic substrate capacitances. SiC substrates are often used for the epitaxial growth of graphene for electronics applications, with the advantages of the use of the conventional top-down lithography techniques well established in nanotechnology [76]. In contrast to CVD-grown graphene, graphene grown on SiC substrates does not require a transfer. However, SiC-grown graphene remains cost-ineffective. Insulator substrates such as glass or quartz are very useful in graphene FET fabrication. These substrates bring advantages for RF applications due to their ability to reduce the parasitic substrate capacitance, reducing the RF losses associated with the substrates [79]. 3.1.2 Oxide deposition on graphene To fabricate RF devices, it is necessary to grow an oxide on top of the graphene, to do a gate oxide of a GFET or the center contact of a coil, for example. The first approach to grow a high-k dielectric on top of the graphene is the ALD, however, the lack of reaction sites on graphene turns this method more 31 complex than usual, being the deposition of continuous thin oxides hard. The intentional lattice damage, that improves the oxide layers adhesion, is not desirable [80]. In the case of the GFETs (and other transistors), a big Cox is desirable, and consequently a thinner oxide, since it increases the transconductance and consequently the frequency performance of the device. However, thin oxides have high leak current and poor long-time reliability [81]. The appropriate choice of the gate oxide is very advantageous to the GFET performance, as reported in [82], where, despite the high-k of TiO₂, the HfO₂ showed to be a better choice to increase the GFET performance. The deposition of a metal seed layer prior to the ALD showed to be effective in the ALD process, however, the deposition of the seed layer might cause graphene doping during the ALD process. The use of a metal as a seed layer affects the oxide k dielectric constant and the morphology of the oxide [83]. Other approach could be the growth of an induced layer of amorphous carbon by electron beam scanning as a seed layer for oxide deposition by ALD. In [84] a thin HfO₂ thin layer with 1.3 nm of EOT (equivalent oxide thickness) was grown, achieving a gate capacitance of 2.63 µF/cm2. The functionalization of graphene prior to the ALD deposition could be done by an ozone pre-treatment which allows a conformal deposition of the oxide with low mobility degradation and minimal graphene doping [85]. In this work, a tri-methylaluminium (TMA) and O3 at 25ºC ALD was performed on a commercial ALD reactor to pre-treat the graphene prior to the Al2O3 deposition. Other surface treatments could be performed such as exposure to NO2 [86]. Spin coated polymers prior to ALD were reported also, such as in [87], where a PVA polymer was adsorbed to graphene surface as seed layer for ALD due to its high dielectric constant (~6) leading to a gate capacitance reduction. Molecular buffer layers could be also chosen prior to the ALD deposition, such as the noncovalent functionalization of graphene by carboxylate-terminated perylene molecules in [88]. Boron Nitride could also act as a buffer layer for plasma enhanced atomic layer deposition (PE-ALD). With this technique, thin dielectrics of 4 nm could be grown without functionalization or need of a seed layer [89]. The use of hexagonal Boron Nitride (h-BN) as gate dielectric on top of graphene is also reported in [66] and [90]. This approach preserves the graphene mobility with a relatively high dielectric constant (k~4), however, the wafer-scale device fabrication is not possible. New emergent fabrication processes are appearing based on top-down techniques, removing the need of the deposition/growth of an oxide on top of the graphene [49], [91], [92]. In section 3.2.5, this topic will be further explored, providing literature examples of graphene transistors where various fabrication approaches have been employed to develop RF graphene transistors. 32 3.2 Design techniques to improve performance of graphene devices Despite the challenges associated with the fabrication methods discussed in subsection 3.1, particularly in selecting the appropriate substrate for graphene deposition and the optimal approach for growing the gate oxide to fabricate RF graphene transistors and, consequently, ring oscillators, there are several techniques that can be employed to enhance the performance of these devices. While these techniques inherently involve fabrication processes, their primary focus is on optimizing and improving the performance of the transistors. These techniques will be explored in the following subsections. 3.2.1 Graphene contacts and contact resistance To achieve high performance in RF devices, mainly in RF transistors, it is necessary to achieve good contact between graphene and the metal. Numerous studies have explored methods to reduce contact resistance in graphene. This issue stems from the injection of charge carriers at the interface between a three-dimensional material (metal electrode) and the two-dimensional graphene layer. In short-channel GFETs, contact resistance can significantly impact performance, as it dominates the total resistance, rendering the modulated resistance of the channel negligible. To minimize the contact resistance (Rc), the selection of the metal contact must be carefully selected to achieve lower contact resistance. For example, the Pd provides a lower Rc when compared with Au [93]. To reduce the contact resistance several approaches have been studied such as the work function engineering of graphene work function under metal electrodes [94], the annealing of the contacts prior the graphene transfer (to remove the polymer residues that are sticked to the surface of the metal electrode) [95], cleaning the graphene surface prior the metal contacts deposition with UV/ozone plasma [96], edge contact of graphene with metal by the fabrication of antidots [97] or patterning graphene by introducing graphene cuts in the contact area [98], creating defects on graphene by thermal annealing in hydrogen of Ni contacts [99], adding a MoOx interlayer on contact between graphene and the metal electrode [100] or a clean transfer of graphene using gold as support layer [101]. Sandwiched contact structures have been reported also [102]. Regarding to the chosen metal and work function engineering, several studies are being carried out to understand how the contact resistance influences the device´s performance and how this effect can be mitigated. The total resistance between two contacts is the sum of the semiconductor resistance, the contact resistance, and the metal resistance. Sometimes the metal resistance is neglected due to its low value when compared with the other two. So, by subtracting the graphene resistance from the total 33 resistance it is possible to obtain the contact resistance between the metal and the graphene. The contact resistance for each contact is half of the total contact resistance (Equation 5). 𝑅𝑐=𝑅𝑡𝑜𝑡𝑎𝑙−𝑅𝑔𝑟𝑎𝑝ℎ𝑒𝑛𝑒 2 (5) Where 𝑅𝑐 is the contact resistance between graphene and metal, assumed to be the same for both contacts (source and drain), 𝑅𝑡𝑜𝑡𝑎𝑙 is the total resistance measured between source and drain and 𝑅𝑔𝑟𝑎𝑝ℎ𝑒𝑛𝑒 is graphene channel resistance. In [103] is possible to observe the influence of the chosen method for contact deposition in the contact resistance. For RF applications low contact resistances are preferable. In Figure 21 it is possible to see the measurement results of different methods of contact deposition. Figure 21 – a) The I2p – V2p plots of Ti/SLG devices for EBM (electron beam evaporation) and sputter processes, respectively. The optical image of measured device is shown in inset of a); (b) The graphene resistance Rgraphene (R4p) between two probes as a function of force current. The schematic for four-probe measurement is shown in inset of b. Adapted from [104]. After the measurements, the authors reported a contact resistance of 0.78 kΩ and 4.1kΩ for EBM (electron-beam evaporation) and sputter deposition, respectively. It is important to note that in GFETs where the contacts were deposited by E-Beam evaporator, the ρc (contact resistivity) is insensitive to the layer thickness, however, in the devices where the contacts were sputtered, the ρc exhibits layer dependence and increases with the decreasing of the layer thickness. It is important to note that, in multilayer graphene, this effect is not observed. In such cases, the ρc is compared with that of EBM devices. This is because, in multilayer graphene, the metal atoms primarily interact with the surface layers, creating vacancies where the metal penetrates, contacting the underlying layers. This interaction differs from single-layer graphene, where the contact resistance effect is more pronounced. Another resistance that sometimes is not considered when the GFET models are developed is the resistance between the 34 graphene and the substrate (typically SiO2 or HfO2). There are several techniques to reduce this resistance, but in some cases it should be considered such as in applications that require low leakage currents. The Graphene-metal contact resistance, Rc, has proven to be the main responsible for degrading the transistor´s performance. The contact resistance plays an important role on the transistor´s performance, mainly when the gate length decreases, since this does not scale down with the gate length, playing an important role in the cut-off frequency, extrinsic transconductance, the maximum frequency of oscillation, the 𝐼𝐷𝑆-𝑉𝐺𝑆 linearity and the limit of the on-current. Several contact resistances of the literature reported devices could be observed in the next table [104]. Metal/Graphene ρc Ω µm Reference Ni 500 [105] Ti >1000 [106] Ti/Pt/Au stack 100 [107] Cr/Pd/Au stack (1D edge contact) 100 [108] Cu (Cuts patterned) 125 [109] Pd (Cuts patterned) 457 [109] Pd 185-900 [110] Typically, graphene transistors have top and back gate, the back gate is used to dope the graphene reducing the contact resistance. The global back gate is used to dope the graphene under the contacts which significantly decreases the overall series parasitic resistance. 3.2.2 Access resistance in RF graphene transistors Despite the importance of the contact resistance between the graphene and the metal, another resistance plays a big role in the RF GFET fabrication, the access resistance (Ra). This resistance is caused by the ungated graphene region, affecting the RF performance of the device. In [111] the impact of the Rc and Ra in GFET on quartz substrates was investigated separately. To reduce this resistance several works using self-aligned structures were reported. In [60] a self-aligned structure based on T-shape gate structure was implemented achieving an fmax of 105 GHz, in [15] a high-speed transistor with a self-aligned nanowire gate was reported with a fT of 300 GHz with an extrinsic cutoff frequency bigger than 50 GHz in a quartz substrate [67]. In [112], a process for self-aligned gate graphene FETs was reported. In [113] Table 2Contact resistivity (Adapted from [104]) 35 the access resistance was reduced by the chemical doping using polyethyleneimine with a 2.5 x increase in electrical performance, such as the transconductance. 3.2.3 Designs to improve the fmax of the devices One of the main drawbacks of the GFET transistors is their low fmax. As previously described, it is one of the most important FOM of the transistors since it indicates the transistor’s power amplification ability. This low value is caused by the lack of a bandgap of graphene. Lowering the gate resistance (burying the gates, for example) could be a solution to improve the fmax [51]. In [59], a high-quality grown graphene was used to improve the quality of the device. The graphene was grown on a sapphire substrate that enables a clean transfer due to the absence of a metal to be etched, which could leave some impurities on graphene. In the abovementioned work, the authors fabricated a mushroom-shaped coreshell AlOx/Al top-gate with 200 nm (Figure 22). A self-aligned process was employed to decrease the access resistance. The 10.1 GHz and 5.6 GHz were the extrinsic values of fT and fmax of the device, respectively. Figure 22 - Schematic illustration of the fabrication processes for the top gate and self-aligned process reported in [59]. a) Formation of the undercut using an e-beam exposure in an MMA/PMMA two-layer resist. b) Deposition of aluminium to fabricate the T-gate. c) Formation of the natural aluminium oxide layer by oxidizing the aluminium d) Metallization of selfaligned source/drain contacts. e) SEM image of the final device. In [51], a fmax of 50 GHz was achieved with a buried-gate transistor (length 200 nm). Devices with 100 nm gate length were also fabricated, but the results were not satisfactory since the parasitic effects 36 have an important role in shorter channel transistors. The general fabrication process flow is shown in Figure 23. Figure 23 – Process flow of the devices reported in [51]. a) High-resistivity silicon substrate with SiO2 on top. b) Hard mask sacrificial layer for the definition of the gate. c) Etching of the gate. d) Source/drain bottom contacts definition and etching. e) Tungsten (W) deposition and planarization (CMP). (f) Deposition of HfO2 gate dielectric. g) Graphene transfer. h) Lift-off of the source/drain top contacts. These devices were fabricated in high resistivity silicon substrates following the Damascene process. The gates were patterned by e-beam lithography, followed by RIE (Reactive Ion Etching) to open the trenches. The metal was deposited by PECVD (plasma-enhanced chemical vapor deposition) and CMP (chemical mechanical polishing) was used to planarize the surface. After that, HfO2 was deposited by ALD and the excess of HfO2 was removed by ICP (inductive coupling plasma). The graphene used in this device was obtained by CVD growth on Pt foils. In Figure 24, it is possible to see the fabricated devices. Figure 24 – a) Photograph of the fabricated devices on a 200 mm Si wafer. b) Buried gate trenches. c) SEM image of the cross-section of a 100-nm-gate-length GFET [114]. Another work that was developed with a view to increasing the fmax/fT ratio was accomplished in [53]. In this work, a T-shaped gate was fabricated. This structure is similar to the one reported in [59], where a self-aligned process was used to minimize the access resistance. This technique allows small gate dioxide thicknesses of 2.3 nm, gate lengths down to 100 nm, and transconductance of 0.5 mS/mm. The best performance was obtained for a device with a gate length of 110 nm, with a fT of 23 GHz, and a maximum oscillation frequency of 10 GHz (fmax). The graphene used for this device was grown by using 43 3.2.5 Other solutions for transistor gate dielectrics In the previously mentioned publications, it is possible to note a great effort made by the researchers to place high-k dielectrics directly on top of graphene. ALD is the most used technique and the least aggressive for the graphene lattice. However, another way to place a dielectric on top of graphene could be by transferring h-BN film. In [90], a h-BN film was used as the gate dielectric and support substrate. Despite the low dielectric constant of the h-BN film (~3.4), the authors showed that this technique was able to preserve the high mobility of graphene, improving the current characteristics of the device. The h-BN film was obtained by direct exfoliation of h-BN single crystals and the thickness of the gate dielectric was approximately 8.5 nm. The advantage of using this material is its flatness, which is 3 times less rough than the silicon oxide, commonly used on GFET transistors. Back-gated devices with 3.4 µm of width and 2.8 µm of gate length were fabricated. Finally, currents of more than 1 mA/mm were achieved. The fabricated device can be observed in Figure 36. Figure 36 – Back-gated GFET with h-BN gate dielectric: a) Schematic of the atomic structure of the graphene and h-BN. b) optical image of an exfoliated h-BN flake. c) AFM image of h-BN with different layer thickness. d) optical image of GFET. e) Cross-section schematic of the back-gate device structure [90] In [66], h-BN was also used as the gate dielectric. In that work, two layers of h-BN were used, one to act as the passivation layer of the silicon, and another one to act as the gate dielectric. This technique allows for the preservation of the graphene quality and consequently of the graphene carrier mobility. The achieved fT after de-embedding was 22 GHz on devices with 450 nm of gate length and 3 µm of gate width. A high current density of 1.2A/mm was achieved. The fabricated device is shown in Figure 37. 44 Figure 37 – a) to d) Fabrication steps of the BN/graphene/BN FETs. e) Optical image of a bilayer graphene flake exfoliated and transferred on top of the h-BN substrate. f) Optical image of the final device. g) Optical micrograph of the final device. h) SEM image of the final device [66]. In works [15] and [67], the authors proposed the use of a core-shell nanowire as the gate of the GFET. In [67], the used substrate was glass to avoid the power loss through the substrate, thus minimizing the gate parasitic capacitance. The process consists of the precise alignment of the source-gate-drain electrodes, minimizing the access resistance. The physical assembly of a nanowire on top of the graphene material prevents the damage of the graphene lattice to preserve its properties. The nanowire was assembled by dielectrophoresis on top of CVD grown graphene. The shell (Al2O3) of the nanowire was deposited by ALD and the core of the nanowire was constituted by Co2Si. The general flow of the fabrication process and the fabricated device are shown in Figure 38 and Figure 39, respectively. 45 Figure 38 – Schematic illustration of the fabrication steps of the top-gated graphene transistor [67]. Figure 39 – Self-aligned graphene transistors reported in [67]. a) Optical image of the assembled nanowire array. b) Optical image of GFETs and c) Zoom in of b) in one GFET. d) SEM image of GFETs showing the channel and the gate nanowire. The previously reported transistors were able to achieve high extrinsic cut-off frequency, higher than 50 GHz, with a 170 nm gate length (diameter of the nanowire). Despite the good results achieved, this is a hard process to develop and replicate since positioning the nanowires is challenging. Further work undertaken to preserve the graphene lattice characteristics using a physical gate transfer is reported in [49]. In that publication, the access resistance is reduced due to the self-aligned technique that was employed. The authors report that a high intrinsic fT and fmax of 427 GHz and 29 GHz were achieved. Furthermore, it is also reported that a pre-patterned structure was transferred with the help of a thermal release tape directly on the top of the glass and Si/SiO2 substrates, and CVD grown graphene was previously transferred to the top of this. The gate stack was constituted by Al2O3/Ti/Au. In addition, the gate stacks were easily peeled off by thermal release tape due to the low adhesion between SiO2 and Au. 46 Finally, the source-drain electrodes were patterned after the gate stack transfer. The general process can be seen in Figure 40. Figure 40 – Illustration of the fabrication of self-aligned graphene transistors with transferred gate stacks reported in [49]. The final aspect of the fabricated devices is shown in Figure 41. Figure 41 – The self-aligned GFETs: a) Photo image of the final devices on a glass substrate. b) Optical image of the GFETs. c) SEM image of the channel of the GFET. d) TEM image of the cross section of the final device [49]. 47 3.2.6 Selected approaches for RF operation As previously discussed, several critical factors must be considered for the fabrication of RF graphene transistors, the fundamental component of ring oscillators. These include the reduction of gate resistance, achieved by employing buried gates, and the use of high-quality graphene. Minimizing access resistance is also essential to enhance the performance of RF graphene transistors, as mentioned earlier. The use of a high-resistivity silicon (HR-Si) substrate, with a SiO2 layer on top, is crucial to mitigate parasitic substrate effects, especially when compared to doped silicon with SiO2. For improved RF performance, the integration of thin gate oxides with high-k dielectrics is essential. Such materials enable better electrostatic control of the gate, which is critical for achieving a voltage gain greater than 1. Atomic layer deposition (ALD) is the preferred technique for oxide deposition due to its minimal impact on the graphene surface. Alternatively, the transfer of pre-patterned physical gates (metal/oxide stacks) or oxide films such as h-BN has been explored, although these approaches pose additional challenges for scalability. While reducing the channel length is beneficial for faster transistor switching, it requires a tradeoff due to short-channel effects inherent in graphene transistors. These effects can compromise gate control over the channel. The implementation of multi-gate transistor architectures mitigates this issue by improving channel control. As highlighted earlier, chemical vapor deposition (CVD) graphene is the most employed material due to its scalability and tunability, ensuring consistent device performance. Based on these considerations, the following strategies were selected to maximize the performance of the fabricated transistors: 1. Implementation of buried gates to reduce gate resistance. 2. Minimization of access resistance by depositing source/drain electrodes at the end of the process (via a damascene process) to align gate, source, and drain electrodes. 3. Use of a high-resistivity silicon substrate with a SiO2 layer to minimize parasitic effects between the device and substrate. 4. Incorporation of a thin oxide layer grown via ALD using a high-k dielectric (e.g., alumina) to enhance gate control over the channel. 5. Adoption of CVD graphene to enable large-scale process scalability and optimize graphene quality for device performance. It is important to note that these approaches were selected not only based on their technical advantages but also to ensure full compatibility with the fabrication processes available at the International Iberian Nanotechnology Laboratory (INL), one of the key objectives of this thesis. Consequently, alternative 48 methods such as physical gate transfer or h-BN as a gate oxide were excluded due to their scalability limitations. Despite the fabrication of multi-gate transistors, they do not exhibit better performance compared to single-gate devices and, therefore, will not be discussed further in this thesis. 3.3 Fabrication of RF graphene devices The main goal of this work is to fabricate RF graphene ring oscillators for biomedical applications. As previously discussed, the fundamental building block of a graphene ring oscillator is a graphene inverter, which is composed of several graphene transistors (as it will be addressed in section 4). Therefore, the processes required to fabricate graphene transistors capable of operating under RF conditions have been thoroughly researched. To achieve scalability in graphene technology, CVD graphene is being used. The transfer of graphene from the growth substrate to the final substrate poses significant scalability challenges and introduces defects that can adversely impact the performance of graphene devices. For the fabrication of RF graphene devices, the use of a high-k gate dielectric is required to maximize the RF performance. This is due to the increased oxide capacitance, which leads to a higher total capacitance and consequently a higher cutoff frequency (𝑓𝑇). Nevertheless, depositing or growing such materials on top of graphene is challenging due to graphene's 2D nature, its hydrophobicity, and the lack of reactive sites, particularly when using atomic layer deposition (ALD). This often results in the island-type growth of 𝐴𝑙2𝑂3 on the graphene surface. To avoid this issue, researchers have been transferring physical gates, but this approach is difficult to scale. Buried gate topologies have been reported in the literature as a viable method for fabricating graphene devices due to their relatively straightforward fabrication process. However, the use of global back gates is not perfect because they polarize the entire graphene layer, which modulates the graphene under both the source and drain electrodes, leading to variations in resistance during device operation. When a thick oxide is used, a relatively flat surface is obtained for the graphene transfer, minimizing issues during the transfer process. However, challenges arise when a gate contact needs to be patterned on a thin oxide layer, which is preferred for RF applications as it reduces parasitic resistances compared to top-gate configurations. The use of a thin oxide can lead to significant surface topography, complicating the graphene transfer process. Although directly transferring graphene onto a rough surface might result in small cracks, it simplifies the fabrication process. Given this, two approaches will be presented in this thesis. First, a bottom-gate graphene device fabrication process without surface planarization, along with a detailed discussion of the associated 49 challenges. To achieve a crack-free graphene transfer, a critical point drying process was developed and employed to dry the samples, preserving the graphene lattice characteristics. In the other approach, a surface planarization technique using ion milling prior to graphene transfer was applied, resulting in the successful fabrication of a buried gate RF graphene FET, demonstrating the effectiveness of the planarization process. The diagram of the two fabrication processes reported in this thesis can be seen in Figure 42. Figure 42 – Diagram of the two main processes reported in this thesis with and without planarization, a) and b) respectively. In a) i) HR silicon wafer with chromium + gold and alumina on top; ii) e-beam lithography to define source, drain and gate contacts by ion milling; iii) device after ion milling; iv) e-beam lithography to define the gate oxide after the growth of fresh alumina by ALD (after the resist removal by O2 plasma, and alumina by wet etch); v) result after the patterning of the gate oxide by ion milling; vi) final device with graphene. b) i) device after e-beam lithography and ICP RIE; ii) after the chromium gold deposition; iii) after the lift-off, showing the ears to be removed by ion milling, to planarize the device; iv) after the graphene transfer; v) after the e-beam lithography and copper + gold deposition to define the source/drain electrodes by lift-off; vi) final device. 3.3.1 Bottom-gate graphene device fabrication process without surface planarization The fabrication of the first structure (bottom-gate without planarization) began with a p-doped silicon wafer, on which 500 nm of SiO₂ was grown via PECVD. This choice of substrate was driven by cost considerations, as the p-doped wafers were used as a “dummy'” option during the process validation phase. Since the process was successfully validated, high-resistivity (HR) silicon wafers were used for the final structures. Subsequently, 3 nm of chromium and 97 nm of gold were deposited by sputtering. To define the contacts using ion milling, 10 nm of alumina was sputtered on top of the gold to facilitate the removal of the photoresist. After alumina deposition, the sample was prepared for electron beam (ebeam) lithography. The wafer was coated with AR-N 7520.18 1+1, and e-beam lithography was performed to pattern the source, drain, and gate contacts. The contacts were then patterned using ion milling at an angle of 130 degrees, followed by 165 degrees to remove redeposited metal "ears." The photoresist was stripped using an oxygen plasma, and an aluminum etchant (Fujifilm AES) was employed to remove the alumina, resulting in a clean surface devoid of resist residues. These steps are shown in Figure 43. 50 Figure 43 – First steps of the fabrication process with a) and b) showing an optical image of the lithography and c) and d) showing the optical micrograph after the ion milling and the resist removal by an O2 plasma. Next, 10 nm of Al₂O₃ was deposited by ALD to serve as the gate dielectric. The dielectric was patterned using ion milling after an e-beam lithography with AR-N 7520.18 1+1. The photoresist was then removed using an oxygen plasma, as illustrated in the Figure 44 and Figure 45. Figure 44 – a) and b) show an optical image of the lithography performed to pattern the gate dielectric (alumina) and c) and d) shows the optical image after the ion milling. To note, since the gate is very thin, some e-beam resist was left to act as anchor of the e-beam resist responsible for the patterning of the gate dielectric. 51 Figure 45 – a) and b) Optical photograph of the device after the resist removal with the oxygen plasma. CVD graphene grown on copper foil was transferred onto the top of the structures using a PMMAassisted wet transfer method (as detailed in the next chapter). Shortly, prior to the transfer, an O₂ plasma treatment was applied to the back side of the copper foil (which contains the graphene protected with the PMMA) to remove the graphene from that side. The copper foil was then etched in an iron chloride solution. Subsequently, the graphene-PMMA stack was transferred to an HCl solution to remove iron chloride contaminants and then to water before the final transfer to the substrate. Prior to the transfer to the final substrate the substrate surface was dehydrated and primed using a vapor prime oven to promote the adhesion of the graphene to the final substrate. After the transfer, the graphene was dried at room temperature The PMMA was then removed using acetone. Finally, the graphene was patterned using an O₂ plasma beam following lithography with AZ1505. The resist was removed using acetone. In Figure 46 it is possible to observe the graphene laying in the graphene channel. Figure 46 – Optical image of the graphene laying in the channel of the device. To evaluate the feasibility of using graphene flakes in GFET fabrication, devices were constructed using this kind of graphene. The growth of such flakes will be addressed later in this document. However, the substandard quality of the flakes, likely resulting from inadequate handling during post-fabrication, led to unsatisfactory device performance. The Figure 47 presents the performance of these fabricated devices. Additionally, as this process was implemented on p-doped silicon wafers, the devices did not exhibit RF performance. 52 Figure 47 – Microscope image of the patterned substrate with the graphene flakes (a) and Vgs vs IDS and 𝑔𝑚 characteristic curves of devices presented in that substrate with W = 35.6 µm and L = 1.19 µm (b) and (c). Since the graphene flakes did not yield satisfactory results and a large area of continuous graphene is essential for achieving high yield in device fabrication, continuous graphene films were used in a new sample replicating the same fabrication process. The p-doped silicon wafer was replaced by a high-resistivity silicon wafer to minimize parasitic capacitances from the substrate. Due to the small gaps between the source and drain contacts, the drying process is critically important. Two approaches were tested with the continuous graphene film after patterning (using O₂ plasma, as it was discovered that graphene only breaks after patterning, i.e., after the removal of the photoresist, not after the removal of the PMMA used for transfer). In the first approach, the sample was dried on air. In the second approach, critical point drying was used. In the first approach, due to the surface tension of acetone (during the drying process), resulted in damage to the graphene at some sites, making it unsuitable for RF device fabrication (see Figure 48 c) and d)). For thicknesses above approximately 500 nm, the graphene tends to conform to the surface of the contacts rather than remaining suspended (see Figure 48 b)), which mitigates the impact of the drying process. This observation supports the use of coplanar structures in sensor fabrication, where graphene on the sidewalls enhances sensor sensitivity [118]. The performance of the fabricated devices is shown in the next section. 59 under a pressure of 4.5 Torr during 30 minutes within the quartz tube furnace. For the graphene growth process, a gas mixture of 300 sccm Ar, 100 sccm H2, and 1.5 sccm CH4 was introduced into the quartz chamber, maintaining the 4.5 Torr pressure for 60 minutes. After growth, the samples were cooled using 500 sccm Ar until the furnace reached ambient temperature. As documented in the literature, rapid cooling is essential to minimize defects within the graphene lattice, thereby preserving its high crystalline quality [123]. The general process of the graphene continuous film fabrication could be seen in the Figure 53. Figure 53 – a) General fabrication process of the single layer graphen continuous film. b) graphene on copper and c) carbon chunk on top of the graphene arising from contaminations in the graphene furnace. 3.4.2 Graphene flakes Despite the overall quality of continuous CVD-grown graphene films, a significant drawback is the presence of grain boundaries, which occur when graphene flakes coalesce during growth. These grain boundaries introduce defects in the film due to the presence of dangling bonds that can anchor contaminants, acting as scattering centres and thereby degrading critical properties of graphene, such as its carrier mobility—an essential parameter in electronic applications. Increasing the grain size in largearea continuous graphene films reduces the number of grain boundaries per unit area, which in turn enhances the mobility of graphene, leading to improved performance in graphene-based devices. To mitigate the detrimental effects of grain boundaries, the growth of isolated CVD graphene flakes is essential, since it facilitates the selection of the best regions visually. Achieving high-quality graphene flakes requires precise control over the flow rates of the gases involved in the growth process. This thesis presents a comprehensive study on the CVD growth of graphene flakes, with a particular focus on the influence of key gas flow parameters, including hydrogen (H₂), methane (CH₄), and argon (Ar). 60 Hydrogen plays a crucial role in graphene growth, functioning as a co-catalyst that aids in the activation of the metal surface, thereby promoting the growth of graphene. Additionally, H₂ significantly influences the shape of the graphene grains by etching weak carbon-carbon bonds, thus controlling the morphology of the graphene flakes [124]. The flow of methane is equally critical, as it serves as the carbon source, directly impacting the growth rate and quality of the graphene layer. To optimize the growth process, a confinement graphite box containing an oxygen source (sapphire wafer) was employed to manage the native oxide layer prior to annealing. This approach was aimed at controlling nucleation on the copper surface. The copper foil was deliberately oxidized on a hot plate within a cleanroom environment to incorporate additional oxygen into the process, which helped decrease the nucleation sites on the copper foil. The presence of oxidized copper suppresses carbon nucleation, reducing the likelihood of nucleation and increasing the spacing between nucleation sites. This allows for greater lateral growth of graphene flakes and permits the use of a higher methane flow rate during growth, without saturating the copper foil with unwanted graphene satellites. Substrate preparation The roughness of the copper foil significantly influences the quality of the transferred graphene. To prevent the collapse of graphene following transfer, it is essential to minimize the roughness of the copper surface, as any irregularities on the copper foil will be transferred to the PMMA and subsequently to the final substrate. To achieve a smooth copper surface, chemical polishing was performed using an ultrasonic bath. The polishing solution consisted of 10 ml of 0.5 M FeCl₃, 10 ml of 37% HCl, and 280 ml of deionized (DI) water. After polishing, the samples were rinsed thoroughly with DI water and then dried using a nitrogen (N₂) gun. After the polishing process, the copper foils were oxidized in a hot plate set at 250°C for 30 minutes within an ISO 5 class cleanroom environment. This oxidation step is crucial for preparing the copper surface for subsequent graphene transfer. Catalyst oxidation state control To maintain the oxidation state of the copper foil during the graphene growth process, a sapphire disk (3-inch Al₂O₃ wafer) was positioned over the substrate using two graphite spacers as shown in Figure 54. This setup was then placed inside a graphite box. The graphite box serves multiple critical functions: it traps gases released from both the sapphire disk and the oxidized copper foil during growth, thereby increasing the local oxygen concentration. Additionally, the graphite box protects the sample from contamination by SiO₂ particles that may be released from the walls of the quartz tube. 61 Figure 54 – Picture of the sapphire mounted over the treated copper foil. Graphene flakes growth The graphene flakes were grown using the same CVD system (EasyTube 3000 from First Nano) as employed for continuous graphene films, with the setup previously described: copper substrates with a graphene cap enclosed in a graphite box. The growth procedure involved the following steps: 1. Heating: The reactor and the sample are heated to 1040 °C with an Ar flow (which lasts around 30 minutes). 2. Annealing: The sample was annealed in an argon (Ar) atmosphere to prepare the surface for graphene deposition for 30 minutes. 3. Graphene Deposition: Graphene growth was achieved by introducing 1.5 sccm of methane (CH₄) and 350 sccm of hydrogen (H₂) into the reactor for 90 minutes at a pressure of 4.5 Torr. Both the annealing and growth processes were conducted at the same pressure. After the growth process, the graphene flakes were characterized using optical microscopy. This was performed immediately after cooling the sample to room temperature. The presence of graphene was confirmed by observing areas of the oxidized copper where graphene was absent. The oxidized copper was clearly visible in regions without graphene. The workflow of graphene flakes growth can be seen in Figure 55. Figure 55 – General scheme of the graphene flake growth. 62 3.4.2.1 Control of graphene flake morphology through gas flow ratios Tuning the flow rates of H2, CH4 and Ar gases during the CVD process allows for precise control over the nucleation density, size, and shape of the graphene flakes. Effect of the H2 in the flake’s growth In the chemical vapor deposition (CVD) process, H2 serves both as a surface activator and an etchant. By adjusting the flow rate of H2, it is possible to influence the shape of the graphene crystals. Specifically, the ratio of H₂ to CH₄ plays a critical role in determining the morphology of the graphene flakes. A low H₂/CH₄ ratio tends to produce dendritic shapes, whereas a high H₂/CH₄ ratio results in hexagonal and circular shapes, with excess H₂ facilitating the formation of these latter geometries. Hexagonal graphene flakes are particularly desirable because they help to minimize grain boundaries when forming continuous graphene films. Studies have shown that continuous films composed of randomly oriented, irregularly shaped, micrometer-sized flakes tend to have a high density of grain boundaries, which can adversely affect the film’s properties. In contrast, hexagonal flakes with zigzag edges are beneficial for the oriented growth of continuous graphene films, reducing the number of grain boundaries and thereby enhancing the film’s properties [125]. In a study conducted to investigate these effects, the flow rates of argon and methane were kept constant at 300 sccm and 1.5 sccm, respectively, while the H₂ flow rate was varied from 50 sccm to 300 sccm at a pressure of 4.5 Torr, with a growth duration of 90 minutes. The results, as depicted in the Figure 56, align with existing literature: increasing the H₂ flow leads to a more rounded flake morphology due to the etching of the flake edges by hydrogen. Challenges were encountered in identifying an optimal graphene recipe for RF device fabrication due to contamination issues from carbon nanotube growth, as the same reactor was used for both processes. This contamination affected the cleanliness of the reactor and complicated the development of a suitable graphene synthesis protocol. Figure 56 – Evolution of graphene flakes with the increasing of Hydrogen (𝐻2) flow. 63 Effect of the CH4 in the flake’s growth Methane plays a crucial role in the growth of graphene as the carbon source in this molecule is essential for graphene formation. To conduct this, an H₂ flow rate of 350 sccm and 300 sccm of Ar at 4.5 Torr were used, with varying CH₄ flow rates to study their effects (from 1.5 sccm to 2.95 sccm). Consequently, the methane flow rate was found to directly influence the size of the graphene flakes. However, simply increasing the CH4 flow is not always advantageous. Elevated CH4 levels can lead to an increased number of nucleation sites, resulting in a higher density of coalesced graphene flakes. This coalescence often leads to multilayer graphene forming at the centers of flakes and an increase in grain boundaries. While increasing the CH4 flow enhances the availability of reactive carbon species, which promotes the growth of larger graphene flakes, it also introduces complications. Specifically, excessive methane can lead to a higher nucleation density, which may cause more flakes to merge. This merging can create multilayer regions and increase the overall number of grain boundaries within the graphene film. The evolution of the graphene flakes with the increase of CH4 can be seen in Figure 57. . Figure 57 – Evolution of graphene flakes with the increasing of methane (𝐶𝐻4) flow. The use of the same reactor for both graphene and carbon nanotube synthesis posed significant challenges in optimizing graphene recipes for RF device fabrication. 3.4.2.2 Samples characterization Following the growth process, the graphene flakes were characterized using optical microscopy (OM), scanning electron microscopy (SEM), and Raman spectroscopy. Initially, the samples were protected from oxidation by the graphene layer. To reveal the underlying copper in areas without graphene, the samples were oxidized in air by placing them on a hot plate at 180°C for approximately 5 minutes. This oxidation treatment highlighted the regions where graphene flakes were absent, facilitating the identification of graphene coverage as shown in Figure 58. 64 Figure 58 – Images of graphene flakes on copper after the oxidation on a hotplate a) optical microscope and b) photograph of the copper foil. Optical microscopy and scanning electron microscopy Optical microscopy was used to observe and evaluate the size and shape of the graphene flakes immediately after the oxidation process. For a more detailed analysis, scanning electron microscopy (SEM) was performed using a FEI Nova NanoSEM 650 at electron beam voltages of 5 kV and 10 kV. This provided high-resolution images to assess the morphology and quality of the graphene flakes Raman spectroscopy Raman spectroscopy was employed to further characterize the graphene flakes. The measurements were conducted using a Witec Alpha300R confocal Raman microscope equipped with a 532 nm frequency-doubled Nd laser. Raman spectroscopy is a powerful technique for assessing graphene quality and properties. While elastic light scattering (Rayleigh spectroscopy) can determine the number of graphene layers, it is primarily effective for exfoliated samples on optimized substrates and does not provide additional structural or electronic information [126]. In contrast, Raman spectroscopy is versatile and applicable to all types of graphene samples, providing comprehensive insights into graphene quality, including the presence of contaminants, doping, and defects, and enabling effective comparison among different samples [127]. In graphene, the Raman spectrum exhibits characteristic peaks due to phonon energy shifts caused by laser excitation. For a 532 nm laser excitation, these peaks are primarily the G peak (at approximately 1580 cm⁻¹), the 2D peak (at around 2690 cm⁻¹), and the D peak (at approximately 1350 cm⁻¹) [128] . The positions of these peaks can vary depending on the wavelength of the excitation laser used. The different Raman graphene peaks can be seen in Figure 59. 65 Figure 59 – Different Raman graphene peaks for a laser excitation of 532 nm[129]. The Raman spectrum of single-layer graphene differs slightly from that of multilayer graphene due to interactions between the graphene layers. Specifically, the 2D peak in single-layer graphene is narrower and sharper compared to that in multilayer graphene [130]. Additionally, the G peak exhibits a red shift with an increase in the number of graphene layers [131]. The number of graphene layers can be derived from the ratio of the peak intensities, I₂D/IG, as well as from the position and shape of the peaks as shown in Figure 60 and Figure 62. The I₂D/IG ratio is particularly useful for distinguishing between monolayer and multilayer graphene. The G and 2D peaks' positions and shapes provide additional information on the layer number and the presence of any defects or strain in the graphene structure [130]. Figure 60 – Raman spectra of single layer graphene and bulk graphite at a 532 nm laser [132]. The position and intensity of the G band can be influenced by various factors such as doping and strain within the graphene. Consequently, shifts in the G band position can provide valuable information about these aspects of the graphene sample. The intensity of the G band also follows a predictable behaviour that aids in predicting the thickness of the graphene layers as shown in Figure 61. 66 Figure 61 – A linear increase in G band intensity occurs as the number of graphene layers increases, with a 532 nm laser. Adapted from [133]. In addition to the G band, another prominent feature in the Raman spectrum of graphene is the D band, also referred to as the defect band. The D band appears around 1350 cm⁻¹ and is indicative of defects within the graphene structure. The intensity of the D band is directly proportional to the level of defects present in the graphene sample. In high-quality graphene or graphite, the D band is typically very weak or absent [133]. This relationship between D band intensity and defect density provides a valuable tool for assessing the quality of graphene, with lower D band intensity signifying fewer defects and higher structural integrity. Figure 62 – Relationship between 2D peak and G peak for single layer graphene. Adapted from [133]. The 2D band in the Raman spectrum, which appears around 2690 cm⁻¹, is the second-order peak of the D band and is crucial for characterizing graphene. This band is a strong and consistent feature of the Raman spectrum, even in the absence of the D band. It plays a significant role in determining the number of graphene layers present in a sample. The position and shape of the 2D band are critical indicators; as the number of graphene layers increases, the peak becomes less symmetric due to the 67 overlapping spectra of the individual layers. The 2D band can be used to distinguish between single-layer and multilayer graphene, with the capability to identify up to four layers. For single-layer graphene, the intensity ratio between the 2D and G peaks (I₂D/IG) is a key parameter. In high-quality graphene, this ratio is typically greater than or equal to 2. Given these characteristics, Raman spectroscopy is an efficient method for evaluating the quality of graphene. Initially, Raman measurements were conducted immediately after the graphene growth, as shown in Figure 63. Subsequent Raman analyses were performed after transferring the graphene to the final substrate, which is critical for nanodevice fabrication. Figure 63 – a) Raman spectra a graphene flake on a copper foil and b) Raman spectra at 532 nm of the flake. 3.4.3 Graphene growth contaminants As previously mentioned, the cleanroom facilities at INL are shared among various research projects. The Easytube system used for graphene growth was also used for carbon nanotube synthesis. The nanotube growth process used much higher flow rates of methane and ethylene (not used in graphene) compared to those required for graphene growth, which led to significant contamination of the reactor chamber and associated plumbing. Despite thorough cleaning efforts, large carbon deposits remained in the system. The high sensitivity of graphene growth parameters to environmental conditions made it challenging to achieve optimal results with this level of contamination. The residual carbon from nanotube synthesis (shown in Figure 64) adversely affected the ability to finely tune the growth conditions necessary for producing high-quality graphene. Consequently, the contamination impeded the development of graphene suitable for state-of-the-art RF devices. 68 Figure 64 – Contaminated CVD furnace. The black portions are carbon chunks that resulted from CNT growth. A cleaning protocol involving high-temperature oxidation with oxygen was developed to address contamination within the reactor chamber. However, this method proved insufficient to completely remove all residual carbon deposits from the pipes and chamber. Additionally, manual cleaning efforts were employed to further address contamination, but these measures still did not achieve the desired level of cleanliness. The persistent contamination compromised the effectiveness of the cleaning procedures and adversely affected the reproducibility of the graphene growth process. As a result, maintaining consistent and high-quality graphene production for RF device applications became challenging. 3.4.4 Graphene transfer PMMA is the most used polymer for supporting graphene during the transfer process. This polymer has excellent solubility in organic solvents such as acetone and toluene. After PMMA removal, following the graphene transfer to the final substrate, it is common to observe PMMA residues on top of the graphene membrane. Despite these residues, the PMMA transfer method remains the most reliable and widely used for graphene transfer. PMMA acts as a supporting layer to preserve the integrity of the graphene during the wet etching of the copper substrate and provides mechanical stability throughout the transfer process. However, these residues can dope the graphene, potentially degrading its thermal and electrical properties. The graphene carrier’s mobility can decrease one order of magnitude after the transfer [134][135]. The graphene transfer is also affected by the appearance of cracks in the membrane as shown in the Figure 65. Several methods have been reported to remove the PMMA from the top of the graphene surface. Hot acetone was used to remove the PMMA, since the temperature enhances the solvent extraction [136]. Other solvents could be used to dissolve PMMA such as anisole, chlorobenzene and chloroform. Despite the PMMA solvents being used to remove the PMMA from the graphene surfaces 75 where µ𝑒 and µℎ are electron and hole mobility. 𝑛0 is the residual carrier density due to disorder and termal excitation, C is the gate capacitance per area, W and L are the channel width and length, q is the electron charge, 𝛽 relates the phonon wavelength of the dominant scattering phonon and m is a fitting 𝐼𝑑𝑠1=µ𝑒𝑉0𝑄0 √1+(µ𝑒|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (𝑉𝑔𝑠,𝑉𝑔𝑑) (6) 𝐼𝑑𝑠2=µ𝑒𝑉0𝑄0 √1+(𝑢𝑒|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (𝑉𝑔𝑠,0) + µh𝑉0𝑄0 √1+(µℎ|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (0,𝑉𝑔𝑑) (7) 𝐼𝑑𝑠3=µh𝑉0𝑄0 √1+(µℎ|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (𝑉𝑔𝑠,0) + µe𝑉0𝑄0 √1+(µℎ|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (0,𝑉𝑔𝑑) (8) 𝐼𝑑𝑠4=µh𝑉0𝑄0 √1+(µℎ|𝑉𝑔𝑠−𝑉𝑔𝑑| L 𝜐sat )𝑚 𝑚𝑊 𝐿𝑓 (𝑉𝑔𝑠,𝑉𝑔𝑑) (9) 𝑓 (𝑥,𝑦)=𝑥√1+𝑥2−𝑦√1+𝑦2+𝑙𝑛( √1+𝑥2 + 𝑥 √1+𝑦2+𝑦) (10) 𝜐𝑠𝑎𝑡= 𝜐𝐹𝛽 √𝑛𝑜2+ (𝐶(𝑉𝑔𝑠+𝑉𝑔𝑑 2𝑞 )2 4 (11) 𝑉𝑔𝑠=𝑉𝑔𝑠 𝑉𝑜 (12) 𝑉𝑔𝑑= 𝑉𝑔𝑑 𝑉𝑜 (13) 𝑉𝑜=𝑄𝑜 𝐶 (14) 𝐶= 𝐶𝑔𝑑+𝐶𝑔𝑠 𝑊𝐿 (15) 𝑄𝑜=𝑞𝑛𝑜 (16) 76 parameter. These functions can be merged by using the operator Θ (x), i.e., using the combination of the step functions where the variables are 𝑉𝑔𝑠 and 𝑉𝑔𝑑. Given that, the single 𝐼𝑑𝑠 and Θ (x) equations are: 𝐼𝑑𝑠=𝐼𝑑𝑠1Θ (𝑉𝑔𝑠)Θ(𝑉𝑔𝑑) + 𝐼𝑑𝑠2Θ (𝑉𝑔𝑠)Θ(−𝑉𝑔𝑑) × 𝐼𝑑𝑠3Θ (−𝑉𝑔𝑠)Θ(𝑉𝑔𝑑) + 𝐼𝑑𝑠4Θ (−𝑉𝑔𝑠)Θ(−𝑉𝑔𝑑) (17) Θ(x)= 1+tanh(𝑉1𝑥) 2 (18) where 𝑉1 is a fitting parameter. The 𝑉𝑜 parameter is introduced to add the unintentional charging effect in the channel at low 𝑉𝑑𝑠, (𝑉𝑔𝑠 = 𝑉𝑔𝑠-𝑉𝑜 and 𝑉𝑑𝑠 = 𝑉𝑑𝑠-𝑉𝑜). Despite the dielectric thickness being less than 10 nm in that work [147], the authors of that model did not include quantum capacitance. Although critical, for simplicity, it was omitted because quantum capacitance appears in series with the geometric capacitance, and typically the smallest capacitance dominates. (the geometric capacitance). As previously mentioned, the contact resistance varies based on the type of carrier within the channel. To account for this, the model uses a series resistance that depends on the carrier type to the contact resistance. Additionally, the contact resistance at both the source and drain is assumed to be identical, as it is influenced by the channel width rather than the contact area [147]. Consequently, the contact resistance is given by the following equation: 𝑅𝑠=𝑅𝑑=𝑅𝑜+𝑅𝑒𝑥𝑡(𝑉𝑔𝑠,𝑉𝑔𝑑) (19) 𝑅𝑒𝑥𝑡(𝑥,𝑦)=𝑅𝑒𝑥𝑡𝑜1+tanh(𝑉2𝑥) 21+tanh(𝑉2𝑦) 2 (20) where 𝑅𝑜 is the resistance when 𝑉𝑔𝑠<0 and 𝑉𝑔𝑑<0, 𝑅𝑒𝑥𝑡𝑜 is the resistance added to account for the difference in the resistance due to different majority carriers, and 𝑉2 is a fitting parameter. 77 4.1.2 Transistor model parameters extraction For the extraction of the extrinsic parameters (LS, LG, LD, CPGS, CPDS, and RG), excluding Rs and 𝑅D, the S-parameters of the de-embedding structures were used. A more detailed explanation of this approach can be shown below in the section 4.1.3. The RS and RD parameters aim to account for variations in contact resistance depending on the carrier type and can be obtained from DC measurements of 𝐼𝐷𝑆 −𝑉𝐺𝑆 curves at low drain voltages. This approach is necessary because, at low drain voltages, Equation 6 and 9, can simplify the intrinsic and extrinsic drain-source resistance to the equations presented in Table 3. Holes Electron Intrinsic 𝑅𝑑𝑠=𝑉𝑑𝑠 𝐼𝑑𝑠 1 𝛼ℎ√1 + ( 𝑉𝐺𝑆 𝑉0 )2 1 𝛼𝑒√1 +( 𝑉𝐺𝑆 𝑉0 )2 Extrinsic 𝑅𝐷𝑆=𝑉𝐷𝑆 𝐼𝐷𝑆=𝑅𝑆+𝑅𝐷+𝑅𝑑𝑠 2𝑅𝑜+ 𝛼ℎ √1 +( 𝑉𝐺𝑆 𝑉0 )2 2𝑅𝑜+2𝑅𝑒𝑥𝑡𝑜 𝛼𝑒 √1 + ( 𝑉𝐺𝑆 𝑉0 )2 𝛼𝑒,ℎ=𝐿 𝑊𝜇𝑒,ℎ𝑄0 By fitting the aforementioned equations (in Table 3) to model the 𝑅DS profile, one can determine the values of 𝑅S, 𝑅D, (𝑅𝑜 𝑎𝑛𝑑 𝑅𝑒𝑥𝑡𝑜), 𝑉0, and 𝛼ℎ,𝑒. Extracting intrinsic capacitances involves measuring the device S-parameters when biased at the Dirac point (Cgd and Cds). This specific bias point is crucial because, under these conditions, the 𝑔𝑚 is equal to 0, and the parasitic parameters can be extracted following the de-embedding process in (section 4.1.3.) and the small-signal model shown in Figure 68, the following parameters can be obtained: 𝐶𝑔𝑑=𝐼𝑚𝑎𝑔[−𝑌12] 𝑗𝑤 (21) 𝐶𝑔𝑠=𝐼𝑚𝑎𝑔[𝑌11+𝑌12] 𝑗𝑤 (22) 𝐶𝑑𝑠=𝐼𝑚𝑎𝑔[𝑌22+𝑌12] 𝑤 (23) Table 3Equations of intrinsic and extrinsic drain-source resistances 78 And the remaining parameters are calculated as follows: 𝐶=𝐶𝑔𝑠+𝐶𝑔𝑑 𝐿𝑊 (24) 𝑄𝑜=𝐶𝑉𝑜 (25) 𝜇𝑒,ℎ=𝐿 𝑊𝛼𝑒,ℎ𝑄𝑜 (26) Figure 68 – Small-signal model after de-embedding the parasitic elements at 𝑉𝐺𝑆=𝑉𝐷𝑖𝑟𝑎𝑐. Adapted from [147] . 4.1.3 Transistor de-embedding For RF measurements, a more complex setup is required. The device must be set at an operating point using a DC voltage, necessitating the use of a bias tee (Figure 71). The bias tee serves to combine the DC and RF signals. The output of the bias tee, carrying both RF and DC components, is then connected to the gate and drain terminals to bias the GFET and enabling the RF measurements. The S-parameters were acquired using a Vector Network Analyzer (VNA). The general matrix of the S-parameters is as follows: [𝑏1 𝑏2]=[𝑆11 𝑆12 𝑆21 𝑆22 ] ∙ [𝑎1 𝑎2] (27) where a is the input signal, b is the output signal, 𝑆11 is the input port voltage reflection coefficient, 𝑆12 is the reverse voltage gain, 𝑆21 is the forward voltage gain, and 𝑆22 is the output port voltage reflection coefficient. 79 The S-parameters are valuable for extracting the H-parameters (such as 𝑓𝑇), as well as the admittance parameters (Y) and impedance parameters (Z). These parameters are crucial for determining the device’s capacitances, resistances, and inductances. It is important to note that Y = 𝑍−1. The admittance parameters (Y) can be obtained from the S-parameters using the following relationships: 𝑌11=(1−𝑆11)(1+𝑆22)+𝑆12𝑆21 (1+𝑆11)(1+𝑆22)−𝑆12𝑆21𝑌0 (28) 𝑌12=−2𝑆12 (1+𝑆11)(1+𝑆22)−𝑆12𝑆21𝑌0 (29) 𝑌21=−2𝑆21 (1+𝑆11)(1+𝑆22)−𝑆12𝑆21𝑌0 (30) 𝑌22=(1+𝑆11)(1−𝑆22)+𝑆12𝑆21 (1+𝑆11)(1+𝑆22)−𝑆12𝑆21𝑌0 (31) where Y0 and Z0 are the port impedance that typically Z0 = 50 ohm. The two-port system equivalent circuit from the Y-parameters and Z-parameters is shown in Figure 69. Figure 69 – Two-port system equivalent circuit from the Y-parameters (left) and Z-parameters (right). As previously described, it is possible to extract the intrinsic characteristics of a device by deembedding it. For that purpose, open and short structures should be measured to perform an open-short de-embedding. The figure of the complete device, along with the open and short structures, can be seen in Figure 70. Figure 70 – De-embedding equivalent circuits. Device under test (left), Short (center) and Open (right). 80 Comparing the 2 previous figures (Figure 69 and Figure 70) and knowing that the Yc=j w C, the following equations can be extracted: 𝐶𝑃𝐺𝐷=Imag[−𝑌𝑂12] 𝑤 (32) 𝐶𝑃𝐺𝑆=Imag[𝑌𝑂11+𝑌𝑂12] 𝑤 (33) 𝐶𝑃𝐷𝑆=Imag[𝑌𝑂12+𝑌𝑂22] 𝑤 (34) where 𝑌𝑂 are the Y-parameters of the open structure of the de-embedding. From the short circuit and knowing the 𝑌𝑂 and 𝑌𝑆 (Y-parameters of the short structure) it is possible to extract the Z parameters of the blue structure and knowing that the impedance of a resistor in series with an inductor is 𝑍𝑅𝐿 = R+ jw L, the following equations can be extracted: 𝑅𝐺=Real [𝑍𝑆𝑂11− 𝑍𝑆𝑂12] (35) 𝑅𝐷=Real [𝑍𝑆𝑂22− 𝑍𝑆𝑂12] (36) 𝑅𝑆=Real [𝑍𝑆𝑂12] (37) 𝐿𝐺=Imag [𝑍𝑆𝑂11− 𝑍𝑆𝑂12] 𝑤 (38) 𝐿𝐷=Imag [𝑍𝑆𝑂22− 𝑍𝑆𝑂12] 𝑤 (39) 𝐿𝑆=Imag [𝑍𝑆𝑂12] 𝑤 (40) To de-embed the final structure, the following formula could be used [147]. 𝑌𝑖𝑛𝑡𝑟𝑖𝑛𝑠𝑖𝑐=1 1 𝑌𝐷𝑈𝑇−𝑌𝑂−1 𝑌𝑆−𝑌𝑂 (41) 4.1.4 Extraction of 𝑔𝑚 and graphene mobility from graphene transistors Since it is important to extract the graphene properties to conclude about the graphene quality, the graphene mobility and transconductance (important parameters used to compare the performance of DC 81 transistors) can be extracted after the 𝐼𝐷𝑆-𝑉𝐺𝑆 measurements. The transconductance can be extracted by applying a numerical derivative using the following formula: 𝑔𝑚[𝑖]=𝐼𝐷𝑆[𝑖+1]−𝐼𝐷𝑆[𝑖] 𝑉𝐺𝑆[𝑖+1]−𝑉𝐺𝑆[𝑖] (42) The mobility of the graphene in the field-effect transistor can be extracted by: 𝜇= 𝐿|𝑔𝑚| 𝑊𝐶𝑔𝑉𝐷𝑆 (43) where L and W are the channel length and width and 𝐶𝑔 is the gate capacitance per area. Despite this method is used for simplicity, it underestimates the graphene mobility since it does not consider the contact resistance of the graphene and the ungated regions. To more accurately extract graphene mobility, Hall measurements should be conducted [147]. 4.2 Transistor performance assessment In this section, the performance of the previously fabricated devices, as described in section 3.3, will be evaluated. The analysis will begin with the extraction of the figures of merit. It is noteworthy that improvements in the fabrication processes, as highlighted earlier, have resulted in enhanced RF performance. Specifically, the devices detailed in Section 3.3.3, fabricated with a gate oxide thickness of 5 nm, demonstrated superior performance compared to those presented in Section 3.3.1 and 3.3.2. However, the devices discussed in Section 3.3.1 were not fully characterized, as the de-embedding structures did not achieve the expected performance. 4.2.1 Transistor figures of merit extraction As previously reported in this work, and as agreed by the academic community, the key figures of merit (FOM) for GFETs are the cutoff frequency (𝑓𝑇) and the maximum oscillation frequency (𝑓𝑚𝑎𝑥). These FOMs are crucial for evaluating the performance of transistors in practical applications, whether in DC or RF circuitry. In brief, the cutoff frequency (𝑓𝑇) is the frequency at which the magnitude of the small-signal current gain is unity (𝐻21=0 𝑑𝐵). Regarding the S-parameters, 𝐻21 can be expressed as: 𝐻21=−2𝑆21 (1−𝑆11)(1+𝑆22)+𝑆12𝑆21 (44) 82 To predict the 𝑓𝑇, as shown before, the generally used expression is: 𝑓𝑇=𝑔𝑚 2𝜋 [(𝐶𝑔𝑠+𝐶𝑔𝑑)(1+(𝑅𝑑+𝑅𝑠)𝑔𝑑𝑠)+𝐶𝑔𝑑𝑔𝑚(𝑅𝑑+𝑅𝑆)+𝐶𝑝𝑔] (45) The 𝑓𝑚𝑎𝑥 is described as the frequency at the maximum gain (Mason’s Gain (U)), Maximum Available Gain (MAG) and Maximum Stable Gain (MSG), or simply U/MAG/MSG), becomes unitary (U/MAG/MSG = 0 dB). This gain should satisfy some conditions to be calculated [148]. To extract the 𝑓𝑇 and 𝑓𝑚𝑎𝑥 from the S-params, the first thing to evaluate is the stability factor, extracted from the expression: 𝑘=1+|𝑆11𝑆22−𝑆12𝑆21|2−|𝑆11|2−|𝑆22|2 2|𝑆12||𝑆21|≡Stability Factor (46) If all k’s are less than one (k<1 for all frequencies), the U/MAG/MSG corresponds to Mason’s Gain (U), and it can be calculated using the following expression: 𝑈= |𝑆21 𝑆12−1|2 2𝑘|𝑆21 𝑆12|− 2 𝑅𝑒𝑎𝑙 [𝑆21 𝑆12]≡Mason′s Gain (47) If all k’s are not less than one, the k should be evaluated for ever frequency. If k<1, the U/MAG/MSG corresponds to Maximum Stable Gain (MSG) and can be calculated using the following expression: 𝑀𝑆𝐺= |𝑆21| |𝑆12| ≡Maximum Stable Gain (48) If k>1, the U/MAG/MSG corresponds to Maximum Available Gain (MAG) and can be calculated using the following expression: 𝑀𝐴𝐺=𝑀𝑆𝐺 ∙(𝑘 − √𝑘2− 1)≡Maximum Available Gain (49) 83 The general equation of fmax, as shown before, is: 𝑓𝑚𝑎𝑥=𝑓𝑇 2√𝑔𝑑𝑠(𝑅𝑔+𝑅𝑠)+2𝜋𝑓𝑇𝑅𝑔𝐶𝑔𝑑 (50) The extraction of the figure of merit (FOM) for graphene field-effect transistors (GFETs) requires the experimental setup illustrated in Figure 71. This setup incorporates two bias tees to separate direct current (DC) and radio frequency (RF) signals, enabling the simultaneous application of a DC bias voltage and an RF signal to the device. A DC power supply is employed to provide the necessary gate and drain bias voltages, thereby biasing the GFET into the desired operational region. A vector network analyser (VNA) is used to generate and measure high-frequency RF signals, allowing for the determination of the device's scattering parameters (S-parameters), which are critical for the calculation of the transistor's FOM. Additionally, a control computer interface is employed to regulate the gate's DC voltage and to facilitate the extraction and analysis of the S-parameters. Figure 71 – Measurement setup used to extract the FOMs of the GFETs. 4.2.2 Bottom-gate graphene device fabrication process without surface planarization (with CPD) To evaluate the performance of the devices fabricated using the CPD method (fabricated in section 3.3.1), extrinsic RF characterization was performed. Intrinsic RF characterization could not be performed due to limitations in the fabrication process since the de-embedding structures did not exhibit the expected performance. Not only RF measurements, but also the DC measurements, were performed with the VGS vs IDS and the respectively 𝑔𝑚 is shown in Figure 72. Figure 73 illustrates the RF measurements, the S-parameters (a) and the extracted FOMs (b). In this device, an extrinsic cut-off 84 frequency (fT) of 5.5 GHz and a maximum oscillation frequency (fmax) of 0.7 GHz, measured at a VDS of 3 V and a VGS of 5 V were demonstrated. These values were obtained without employing a global back gate, suggesting a high level of p-doping in the graphene membrane. This fabrication method achieved a high yield of operational devices, with approximately 70% exhibiting RF functionality. Figure 72 – VGS vs IDS and 𝑔𝑚 characteristic curves of a device with W = 39 µm and L = 1.100 µm (0.95 µm of gate channel and 0.075 µm of drain/gate and source/gate overlap) measured at a VDS of 100 mV. Figure 73 – a) S-parameters of a device with W = 39 µm and L = 1.100 µm and a La (access length) of 85 nm and respectively fT and fmax b). c) RF measurement scheme used to measure the devices. 4.2.3 Planar buried bottom-gate topology The performance of the transistors fabricated through the buried process (presented in section 3.3.2) was analysed. In the first process (𝑡𝑜𝑥 = 10 nm of alumina) a yield around 100% was achieved. To assess the success of the planar buried bottom-gate topology against the process without surface 91 reported model accurately captures the transistor's behaviour. This level of accuracy suggests that the model is sufficiently robust to predict the performance of other transistors, provided that relevant parameters are appropriately adjusted. Analysing this device under various conditions offers critical insights into its operational thresholds and performance metrics, which are essential for validating theoretical predictions against practical outcome. The Figure 79 illustrates the model's fit to the device, along with the extracted parameters (Table 4), which will be used in subsequent sections to perform the circuit simulations. Figure 79 – Simulated vs measured IDS vs VGS of the transistor. W (μm) L (μm) tox (nm) μh (cm2V-1s-1) μe (cm2V-1s-1) 33.82 1.102 5 899.56 1124.45 Cgs (fF) Cgd (fF) Ro (Ω) RG (Ω) Rext0(Ω) 22.5e-5 45e-15 70=(RD+RS)/2 10 20 4.4.2 Inverter design Like previously reported, the unity element of the ring oscillator is the inverter. With that purpose, a graphene inverter was designed and simulated with the previous model by using a finite element analysis software. To note that all the next simulations were performed using this finite element analysis software. An inverter is created by connecting two GFETs in series, as shown in Figure 77 a). This setup mirrors the configuration of CMOS inverters, where the upper transistor functions like a p-type and the lower one like an n-type. The operating principle of this inverter is that when one transistor is fully conducting, the other should be turned off, or in the case of GFETs, operate near the Dirac point. Due to Table 4 - Extracted parameters from the model by using the previous transistor. 92 a slight variation in VDS, there is a corresponding small difference in the VDirac of the GFETs, allowing for the construction of an inverter with closely matched GFETs. This arrangement produces a transfer curve with a distinct "W" shape, and an inverter can be effectively implemented by operating the device with Vin set between the lowest points of this “W-shaped” curve. To conduct the simulations with more practical values suitable for use in circuits, the Dirac point was adjusted to 0 V. It's important to note that due to the shift in the Dirac voltage (VDirac) caused by the drain-source voltage (VDS), the inverter's maximum gain is not at 0 V but rather shifted to approximately 1.5 V. The VDS of the inverter is set at 3.3 V. As observed, for an input signal with a peak-to-peak voltage of 1.3 V, the output peak-to-peak voltage is around 0.62 V, which closely matches the values (regarding the inverter’s gain) observed in the measured device described Figure 80. It is worth mentioning that some discrepancies between the simulation and the experimental measurements are expected. These differences arise from variations in the modeled devices, which, despite being similar, exhibit differences in graphene quality, this variability is due to the inherent challenges of achieving uniform graphene characteristics across a sample. Additionally, small variations in the fabrication process, such as lithography misalignments or slight changes in channel length or width, can lead to noticeable differences in device behavior, especially at smaller dimensions. The characteristics of the simulated inverter could be seen in the next figure being the maximum inverter’s gain (Avmax) of 0.7. Given that gain, and according to Barkhausen's criterion, it is expected that the ring oscillator fabricated with that devices will not oscillate. Figure 80 – Simulation of an inverter with the extracted parameters. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 0.7 and c) response of the inverter to a 10 kHz square wave. 93 4.5 Oscillator trimming As discussed before, given the low gain of the previous devices, maximum gain (Avmax) lower than 1 (0.7), and according to Barkhausen's criteria, it is expected that the device will not oscillate. In the measurements conducted in the previous section, it was not possible to measure all the fabricated devices, due to the time constraints. Due to variations in W/L ratios, La, and the different characteristics of the graphene (stemming from the variability in graphene quality across the sample), it is possible that some oscillators may have oscillated. To explore the parameters that should be optimized for developing graphene inverters with Avmax greater than 1, several parameters will be varied, and their influence on the Avmax of the inverter will be analysed. 4.5.1 Reducing Rext0 to 10 To investigate the impact of graphene's characteristics on the inverter and achieve a maximum gain (Avmax) greater than 1, thereby satisfying the Barkhausen criterion, various parameter adjustments were performed. Since graphene mobility influences some of the other parameters, Rext0 was initially reduced to 10, an achievable as reported in [147]. Since Rext0 represents the extrinsic resistance at zero voltage, including contact resistance (the resistance between graphene and metal electrodes) and access resistances, this parameter can be minimized by optimizing graphene-metal contacts or by employing the techniques previously discussed to reduce the access length (La). The W-shaped transfer curve and the Vin vs. Vout characteristics, along with the corresponding maximum gain, are shown in the Figure 81. Although the gain increased, reaching a value of 0.8, it remains insufficient to satisfy the Barkhausen criterion, making this inverter unsuitable for use in a ring oscillator. Figure 81 – Simulation of the inverter by reducing the Rext0 to 10. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 0.8. 94 4.5.2 Reducing Ro to 40 Since Ro represents the intrinsic channel resistance at the Dirac point, determined by the inherent properties of the graphene material, its value was reduced to 40, a value that is readily achievable as reported in the literature [147]. To achieve this reduction, higher quality graphene (with increased carrier mobility) should be used, or a suitable substrate, such as h-BN, should be employed to minimize the interactions between graphene and the substrate. Additionally, this parameter can be further decreased by using a high-k gate dielectric with low thickness, which enhances carrier control over the channel, thereby reducing Ro. With this reduction, it was possible to achieve a graphene inverter with a maximum gain of 2.6, which is sufficient to satisfy the Barkhausen criterion. The obtained results are presented Figure 82. Figure 82 – Simulation of the inverter by reducing the Ro to 40. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 2.7. To further optimize this inverter, the Dirac point of the top GFET (which functions as the p-type FET) was shifted to VDirac + 0.3 V. 4.5.3 Reducing Rext to 10, Ro to 40 and shift VDirac to VDirac+0.3 V The VDirac of the transistors was initially slightly unmatched, and as discussed earlier, the inverter operates due to the slight difference in VDS and VDirac between the transistors. To further increase the mismatch, the VDirac of the top transistor (p-mos) in the previous inverter was shifted to VDirac +0.3 V. After this adjustment, as observed in the W-shaped curve, the difference between IDS max and IDS min increased, leading to an improvement in the inverter's gain from 2.6 to nearly 2.7. This kind of shift can be achieved using a dual-gate structure, where one gate specifically adjusts the Dirac point, or by chemical doping. The resulting characteristics of the inverter are shown in Figure 83. 95 Figure 83 – Simulation of the inverter by reducing shifting the VDirac to VDirac+0.3. a) W shape curve of the inverter; b) Vout vs Vin and Gain of the inverter showing a maximum gain of 2.8. 4.5.4 Oscillator frequency tunning To validate the previously optimized inverter, a square wave with a maximum voltage (Vmax) of 2.35 V with a minimum voltage (Vmin) of 1.15 V, and a frequency of 10 kHz was applied to the inverter's input. This input resulted in an output square wave with a Vmax of 2.5 V and a Vmin of 0.880 V, thereby confirming the calculated gain of approximately 2.7. The results are illustrated in Figure 84 (a), and the updated parameters for the optimized inverter are listed in Table 5. The suitability of this optimized inverter for use in a ring oscillator was also assessed. According to the Barkhausen criterion, essential for establishing oscillations in a feedback loop, the total loop gain must be equal to or greater than one, and the total phase shift around the loop must be 360 degrees. With a gain of 2.7, the inverter meets these requirements, ensuring that any initial noise or perturbation is sufficiently amplified to initiate and sustain oscillations, while the appropriate phase shift ensures constructive reinforcement of the signal as it traverses the loop. The simulation results validate this, demonstrating that the oscillator operates at 1.08 GHz with a voltage swing of 2.318 V (Vmax = 3.263 V and Vmin = 0.945 V) as seen Figure 84. W (μm) L (μm) tox (nm) μh (cm2 V-1 s-1) μe (cm2 V-1 s-1) 33.82 1.102 5 nm 899.56 1124.45 Cgs (F) Cgd (F) Ro (Ω) RG (Ω) Rext0 (Ω) 22.5e-5 45e-15 40 = (RD+RS)/2 20 10 Table 5Parameters used for the inverter and in the ring oscillator simulation. 96 Figure 84 – Ring oscillator assessment. Simulation of the optimized inverter (a) and ring oscillator simulation (b). 4.6 Discussion Modelling the fabricated devices plays a vital role in enhancing their performance and predicting the behaviour of oscillators, particularly when direct measurements are not feasible. The devices produced through a planar fabrication process demonstrated intrinsic cut-off frequencies of up to 80 GHz. This frequency, notably high compared to other values reported in the literature, highlights a strong correlation between the achieved 𝑓𝑇 and the simplicity of the fabrication process, as shown in Table 1. The practical realization of a ring oscillator using the optimized inverter confirms the design's viability and its potential applications in timing circuits and signal generation within digital systems. While simulations suggest the potential for oscillation, further enhancements are required to achieve reliable oscillation in the fabricated devices. Potential improvements include optimizing graphene-metal contacts, reducing the access length to decrease Rexto, using higher-quality graphene with increased carrier mobility, and enhancing substrate quality, such as by employing boron nitride. Additionally, the use of a high-k gate dielectric with reduced thickness could be advantageous. To address the mismatch in Dirac points among transistors, various techniques can be considered. These include chemical doping [152], electrical gating configurations [153], or induced strain in graphene [154]. Furthermore, ferroelectric polarization fields may also be used to shift the Dirac point [155]. It is important to note that, given the fabrication of various graphene transistors and oscillator topologies and considering the variability in graphene quality across the sample, some of the fabricated ring oscillators are likely to function. However, as previously mentioned in this thesis, time domain constrains prevented the validation of these oscillators. 97 5 CONCLUSIONS Graphene has become a breakthrough material with high interests because of its unique properties and potentials for disruptive applications in various fields. Graphene's application in electronics, especially for radiofrequency (RF) circuits, is quite promising within its various use cases. Nevertheless, transferring this possibility into real-world graphene-based RF devices is a significant challenge requiring additional efforts and technological development. This thesis aimed to advance the understanding of graphene's capabilities, address the challenges associated with its integration into RF devices, and contribute to the development of state-of-the-art graphene technology. This work is concerned with design, fabrication, and characterization of graphene-based RF transistors and oscillators paving the way of its integration in biosensors. These were developed using standard fabrication processes to be repeatable and enable seamless technology transfer to industrial applications. A comprehensive review of the literature identified key obstacles were performed. The fabrication process was a critical aspect of this work, particularly in shared facilities, which required adaptations to prevent equipment contamination and accommodate facility limitations. Two fabrication methodologies were developed: a bottom-gate process without surface planarization and a planarized buried bottom-gate process using ion milling prior to graphene transfer. The use of critical point drying proved effective in preventing graphene from breaking after patterning. Despite constraints, these approaches proved effective, enabling the successful fabrication of graphene-based devices. The graphene's growth and transfer processes were also studied. The PMMA-assisted transfer method, while introducing residuals, showed negligible impact on the performance of graphene FETs due to the device dimensions. Challenges such as the production of large graphene flakes, which are critical for high-yield RF performance, were noted, being the influence of H2 and CH4 in the graphene morphology. The complexity of fine-tuning growth parameters and contamination from carbon nanotubes hindered the development of an optimized synthesis protocol. Consequently, continuous graphene films were employed for device fabrication to prioritize scalability and consistent performance. The modelling and characterization of the fabricated devices highlighted the progress achieved. Intrinsic cutoff frequencies up to 80 GHz and a maximum oscillation frequency of 14 GHz were obtained using the planar bottom-gate topology with a 5 nm oxide layer. While a functional ring oscillator was not obtained with these transistors, simulations demonstrated that trimming inverter parameters enable the design of a RF graphene ring oscillators with this fabrication process. This underscores the potential of the proposed approach, contingent on further optimization. Despite the variability in graphene quality across samples, the thesis established a repeatable fabrication process applicable to other graphene- 98 based devices beyond the scope of this research. Proposed improvements include optimizing metalgraphene contacts, reducing access length to lower external resistance, and employing higher-quality graphene with enhanced carrier mobility. The use of improved dielectrics with high-k could also significantly elevate device performance. In conclusion, this thesis has made significant contributions to leverage graphene technology use by addressing critical challenges in the design, fabrication, and characterization of graphene-based RF devices. Although the fabrication of a graphene oscillator demonstrating RF performance was not achieved, the findings of this research lay the groundwork for future developments. In particular, the potential application of this technology in biosensors is highly promising, thanks to the developed standard-compatible fabrication process and the designed layouts. Since graphene remains exposed during fabrication, this opens opportunities to develop functionalization methods specifically tailored for biosensing applications. These results provide a foundation for integrating graphene's unique properties into next-generation biomedical and RF technologies, paving the way for further exploration and innovation in these fields. 5.1 Future work Future work should build on the progress achieved in this thesis, which provided valuable insights into graphene's RF properties and developed a process compatible with the standard fabrication processes. To validate the proposed ring oscillator design, fabrication using the optimized parameters and improvements outlined in this research is essential. This practical realization would confirm the accuracy of the simulations and enable further performance refinement. Considering the intended application of these ring oscillators in biosensors, their validation should include functionalization strategies. This could involve functionalizing graphene interconnects or using the capacitive elements of the proposed graphene-based structures. Such functionalization would allow for changes in the oscillation frequency in response to the binding of specific analytes, paving the way for highly sensitive and selective biosensor development. Additionally, the properties of graphene must be further enhanced to improve device performance. Efforts should focus on increasing carrier mobility, minimizing defect density, and refining synthesis methods to produce high-quality, uniform graphene. A back gate should be applied to shift the Dirac point of the transistors, enabling the use of the devices at reasonable voltages. These advancements would not only optimize the performance of RF devices but also broaden graphene's potential applications in cutting-edge electronic and sensing technologies. 99 6 REFERENCES [1] S. Lee and Z. Zhong, “Nanoelectronic circuits based on two-dimensional atomic layer crystals,” Nanoscale , vol. 6, no. 22, pp. 13283–13300, 2014, doi: 10.1039/C4NR03670K. [2] S. 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