Hybrid inverter Zeta-Ćuk for grid-tied photovoltaic applications

1 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < Hybrid Inverter Zeta-Ćuk for Grid-Tied Photovoltaic Applications Anderson A. Dionizio, Leonardo P. Sampaio, Sérgio A. O. da Silva, Member, IEEE, Vítor Monteiro, Senior Member, IEEE, João L. Afonso, Senior Member, IEEE, 1 Abstract— This paper proposes a novel single-phase integrated inverter for photovoltaic (PV) applications called Hybrid Inverter ZetaĆuk (HIZC). The HIZC operates in discontinuous conduction mode and employs four unidirectional power switches, which are achieved by associating series power diodes to MOSFETs. In addition, during the grid's positive half-cycle, the inverter acts similarly to the Zeta converter. On the other hand, during the negative half-cycle, the inverter operates similarly to the Ćuk converter. Due to the adopted design criteria, the Zeta and the Ćuk operation modes show similar behavior. The small-signals analysis considers the Zeta and Ćuk operation modes, showing a significant similarity between their frequency responses, proofing the similarity of the HIZC's functionality in both operation modes. The HIZC can boost the voltage of the PV array and perform the DC-AC conversion at the same time. The maximum power available at the PV array is harvested using a multi-loop control in conjunction with the perturb-and-observe algorithm, while an AF-αβ-PLL system guarantees synchronism with the power grid. Experimental results prove the structure feasibility of the proposed topology for PV applications. In addition, the HIZC presents high-efficiency conversion and also low total harmonic distortion in the current injected into the power grid. Index Terms— Ćuk converter, Integrated Inverter, Photovoltaic System, Power Electronics, Zeta Converter. I. INTRODUCTION n recent years, the investments in renewable energy sources have significantly improved [1,2]. This growth is motivated by a necessity to expand electricity generation and distribution [3-6]. Among the renewable energy sources, photovoltaic (PV) is widely employed due to its modular characteristics, guaranteeing large voltage and current ranges [2, 3, 7-9]. Once the PV generation occurs in direct current (DC), it is necessary to adopt one or more power conversion stages when the PV system is used for grid-tied alternating current (AC) applications [6,9]. Conventionally, a PV system uses a double power conversion stage, where a step-up converter, usually a boost converter, is associated with a voltage source inverter (VSI), commonly a full-bridge inverter. This system can control both structures once the power converters are decoupled [10-12]. On the other hand, this system can use many electrical components, presenting lower efficiency and higher weight and volume when compared to the integrated inverter [5, 6, 10, 11]. The integrated inverters are built in distinct ways, with different control strategies for each structure. Usually, these structures can step up the voltage across the PV array and inject a sinusoidal current into the utility grid through a single DC-AC power conversion stage [5, 9]. A modular grid-connected single-phase inverter is presented 1 This work was supported in part by the National Council for Scientific and Technological Development (CNPq) under Grant 308620/2021-6 and Grant 304707/2021-0; in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brazil (CAPES) - Financing Code 001, and in part by the National Funds through the Portuguese funding agency FCT under Grant SAICTPAC/0004/2015-POCI01-0145-FEDER-016434 A. A. Dionizio is with the Electrical Engineering Department, Federal University of Technology - Paraná, Cornélio Procópio-PR 86300-000, Brazil (e-mail: [email protected]). in [13]. The module can obtain the individual maximum power in each panel. The topology is based on the Ćuk and SEPIC converters and employs a high-frequency transformer, guaranteeing the necessary gain and galvanic isolation. In [14], a Ćuk inverter topology with a high-frequency transformer is also used, where a repetitive control is associated. An experimental 500 W setup proves the feasibility of the system. The main results show high efficiency and injected current with low total harmonic distortion (THD). Similarly, [5] has proposed a bridgeless inverter based on the Zeta converter. The structure can operate in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), using a feedback controller to identify the conduction mode boundaries. Both papers, [5] and [14] use repetitive controllers, guaranteeing a satisfactory response. A topology based on the DC-DC Zeta converter named Modified Zeta Inverter (MZI) is presented in [6], where the MZI structure operates in DCM. However, its functionality differs from the conventional Zeta converter, which delivers a negative current through the magnetization inductor in the third operation stage. The magnetization inductors of the MZI are series associated with power diodes. Thus, these inductors' power flow is unidirectional once the diodes prevent negative currents. An integrated inverter based on the Zeta converter for PV applications has been proposed in [9]. The topology named L. P. Sampaio is with the Electrical Engineering Department, Federal University of Technology - Paraná, Cornélio Procópio-PR 86300-000, Brazil (e-mail: [email protected]). S. A. O. Da Silva is with the Electrical Engineering Department, Federal University of Technology - Paraná, Cornélio Procópio-PR 86300-000, Brazil (e-mail: [email protected]). V. Monteiro with the Department of Industrial Electronics, University of Minho, 4800-058 Guimaraes, Portugal (e-mail: vmonte[email protected]inho.pt). J. L. Afonso is with the Department of Industrial Electronics, University of Minho, 4800-058 Guimaraes, Portugal (e-mail: jla@ dei.uminho.pt). I This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 2 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < Single-Phase Integrated Zeta Inverter (SP-IZI) operates in DCM and presents three operation stages in each switching period. The structure combines two modified Zeta modules, where one is responsible for the functionality during the positive half-cycle, and the other is responsible for operating in the negative half-cycle. A four-switch single-stage and single-phase inverter has been proposed in [15]. The topology is based on the Buck-Boost DC-DC converter and can be employed in autonomous applications or on grid-tied. However, the topology needs an extra inductor for grid-tied applications once the inverter presents discontinuity in the output current. Although the invert in [15] uses fewer semiconductors than the proposed HIZC, the current flows through three semiconductors simultaneously in some operation stages. The HIZC presents current in two or fewer semiconductors in each operation stage. The elevated number of semiconductors presenting current increases the conduction losses. The inverter in [15] corroborates this issue since the structure shows nearly 2/3 of conduction losses. In [15], only the theoretical losses are shown, demonstrating the maximum value of 95.7%, which should be lower when measured. The HIZC achieves a maximum efficiency of nearly 96% in the experimental setup. This paper proposes a new integrated inverter based on the Zeta and the Ćuk conventional topologies. The structure acts as an interface converter between the PV array and the utility grid. Fig. 1 presents the proposed inverter. The HIZC employs four unidirectional power switches built using a series of connected diodes. Thus, the HIZC can be used in microinverters as an interface converter between the PV array and the electrical power grid. Fig. 1. HIZC proposed topology. The HIZC proposed topology presents some advantages over other structures, such as: (i) The HIZC can increase the voltage of the PV array and simultaneously perform the DC-AC conversion to the power grid using only a single stage; (ii) The HIZC uses the total voltage of the PV array in the conversion stage, without the need for split capacitors; (iii) The HIZC does not employ a high-frequency transformer; (iv) The characteristics of the topology allows simple control strategies, guaranteeing a sinusoidal output with low distortion; (v) The HIZC is highly efficient; (vi) The voltages across all the semiconductors in the HIZC are relatively low when considering the input and output voltages of the inverter. The HIZC converter presents some advantages with respect to the MZI proposed in [6]: (i) The HIZC uses the total PV array voltage, while the MZI must split the voltage between two capacitors equally, and thus, the static gain of the MZI must be higher, provoking more losses; (ii) The magnetization inductors of the MZI operate only in half-cycle, while the magnetization inductors of the HIZC operate during the whole cycle, splitting the current between two inductors, reducing the peak and the RMS value of the current, and thus reducing the conduction losses; (iii) The voltage stress in the switches of the HIZC is lower than that of the MZI, which reduces the losses and the demonstrable damage to the components. The HIZC offers some advantages with respect to the SP-IZI [9]. The main benefit is the fact that the HIZC uses the total voltage in the PV array, while the SP-IZI splits equally this voltage across two capacitors. In addition, the Li inductor in the HIZC offers better input current filtering than the SP-IZI. This paper is organized as follows: Section II presents the operation, functionality, main equations, and theoretical waveforms for the HIZC. Section III describes the modeling and control adopted. Section IV compares the experimental results with those of other integrated inverters. Finally, section V presents the conclusions. II. OPERATION AND FUNCTIONALITY OF THE HIZC The proposed HIZC acts as an interface converter between a PV array and the single-phase AC utility grid. The HIZC operates in DCM with linear static gain. In DCM, the HIZC operates similarly to the Zeta converter, presenting three operation stages during the positive half-cycle in each switching period, such as Dz1Ts, Dz2Ts, and Dz3Ts. On the other hand, the HIZC operates similarly to the Ćuk converter during the negative half-cycle of the power grid, which presents the following three operation stages: Dc1Ts, Dc2Ts, and Dc3Ts. The HIZC structure employs four unidirectional power switches deployed by associating series power diodes to the switches. Furthermore, the inverter requires two input inductors, one output inductor, two coupling capacitors, and an output filter capacitor, as presented in Fig. 1. The proposed control of the HIZC is designed to extract the maximum available power at the PV array while injecting this energy into the utility grid as a sinusoidal synchronized current. The HIZC uses the Perturb and Observe algorithm to perform the maximum power point tracking (MPPT), while the synchronism to the power grid is carried out by an adaptive alpha-beta phase-locked-loop (AF-αβ-PLL) system. The controllers, MPPT, and PLL algorithms are discretized and embedded in a digital signals processor (DSP), as shown in Fig. 2. The modulation strategy for the HIZC topology is based on the high-frequency signal obtained by the employed controller and PLL information. Thus, two switches (S2 and S4) operate at low-frequency and in a complementary way. In contrast, the signal for the switch S1 occurs in the positive half-cycle of the power grid by comparing the high-frequency signal to a Lo iLo vg . . . vPV iPV Cdc S1D1 Lm C1 D2 S2 Li S3 D3 C2 S4 D4 gS3 gS1 gS2 gS4 Zeta Ćuk vLm + vC1 + vLi ++ vC2 vLo + iC1 iC2 iLi iLm ig Co +Lgrg + - - - - - -- - + This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 3 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < sawtooth wave at the switching frequency. Similarly, it occurs the same with the switch S3, during the negative half-cycle of the power grid. Fig. 2. HIZC control. A. Zeta Mode During the positive half-cycle of the power grid, the HIZC operates in Zeta mode. In this mode, switches S1 and S2 are commuted, while switches S3 and S4 remain turned off during this period. The first stage of operation, Dz1Ts, starts when the switch S1 turns on. The energy in the PV array flows through this switch and diode D1, which is forward-biased. In this stage, the inductor Lm is magnetized and energized with the PV-array voltage, vPV, and the voltage across the inductor Li is the difference between the coupling capacitors C2 and C1, i.e., vLi = vC2-vC1. A relation between the PV voltage, capacitor C1, and the grid voltage gives the voltage across the output inductor, vLo = vPV+vC1-vg. The current through the coupling capacitor C1 is the sum of the Lo and Li inductor currents, iC1 = iLo+iLi, and the current through the capacitor C2 is the same as the inductor Li. Fig. 3 (a) shows the HIZC in this subinterval. The second operation stage, in Zeta mode, starts when the switch S1 turns off. The energy accumulated in the inductors flows through the switch S2 and the power diode D2. The inductor Lm is demagnetized, and its accumulated energy is transferred to the capacitor C1. The inductor Lm voltage is the same as the capacitor C1, vLm = -vC1. The accumulated energy in the inductor Li is transferred to the coupling capacitor C2. The voltage across this inductor is the difference between the PVarray and capacitor C2 voltages, i.e. vLi = vPV-vC2. The current through the coupling capacitor C1 is the same as the inductor Lm, while the current through the capacitor C2 equals the Li current during the whole Zeta mode. This stage is visualized in Fig. 3 (b). The third operation stage, Dz3Ts, starts when the current through the switch S2 and diode D2 is not enough to polarize the diode D2, i.e., the sum of the inductors' currents is nearly zero. Thus, the D2 is reverse-biased, and the currents do not flow through the switch S2, although this semiconductor remains turned on during the Zeta mode. In this operations stage, the energy flows only in the passive elements. The output inductor current is the sum of the Lm and Li inductors' currents, iLo = iLm+iLi. The operation stage Dz3Ts is shown in Fig. 3 (c). (a) (b) (c) Fig. 3. Operation stages of the Zeta mode: (a) First, Dz1Ts; (b) Second, Dz2Ts; (c) Third, Dz3Ts. B. Ćuk Mode In the negative half-cycle of the utility grid, the HIZC topology operates in Ćuk mode. The switches S3 and S4 are driven in this mode, in which only switch S3 is commuted with a high frequency. On the other hand, the switch S4 is commuted at a low frequency. At the same time, the switches S1 and S2 keep turned off during this mode. The first subinterval in Ćuk mode, Dc1Ts, starts when the switch S3 is turned on, allowing the energy to flow through the A/D Converter Signal Conditioning Board iPV DSC (TMS320F28335) gS1 gS2 gS3 gS4 vPV PI Switching Logic vgiLo vPV iPV MPPT vPV * PLL vg Sin(θ) Ip iLo iLo * PI P W M d . . .Cdc S1D1 Lm C1 D2 S2 Li S3 D3 C2 D4 gS3 gS1 gS2 gS4 S4 Lo Co Lgrg . . .Cdc S1D1 Lm C1 D2 S2 S3 D3D4 gS3 gS1 gS2 gS4 S4 Lo Co Lgrg . . .Cdc Lm D2 S2 Li S3 D3 C2 D4 gS3 gS1 gS2 gS4 S4 S1D1C1Lo Co Lgrg This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 4 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < associated diode D3. The inductor Li is energized and magnetized with the power of the PV array, and the voltage across Li is the PV array voltage, vLi = vPV. The Lm inductor is magnetized with the voltage difference between the coupling capacitors, vLm = vC2-vC1. The difference between the coupling capacitor C2 and the utility grid, vLo = vC2vg gives the voltage across the output inductor. The current through S3 and D3 semiconductors is the sum of the inductors' currents, iS3 = iLm+iLi+iLo. The current through the coupling capacitor C2 is the sum of the Lm and Lo currents, iC2 = iLm+iLo, while the C1 current is the same as the Lm inductor during the whole Ćuk mode. The operation stage Dc1Ts is visualized in Fig. 4 (a). The second operation stage in Ćuk mode, Dc2Ts, starts when switch S3 turns off, and the energy flow polarizes de diode D4. Switch S4 is turned on during the whole negative half-wave cycle of the utility grid. (a) (b) (c) Fig. 4. Operation stages of the Ćuk mode: (a) First, Dc1Ts; (b) Second, Dc2Ts; (c) Third, Dc3Ts. The energy accumulated in the inductors Lm and Li are transferred to the capacitors C1 and C2, respectively, and the voltages across these inductors are the same as the capacitors C1 and C2, where vLm = -vC1 and vLi = -vC2. The current through the capacitor is the same as the inductor Li. Fig. 4 (b) presents this operation stage. Similarly, in the Zeta mode, the third operation stage occurs when the sum of the inductor currents through the diode D4 is insufficient to keep it forward-biased. Thus, the energy flows only through the passive element. Fig. 4 (c) presents this operation stage of the HIZC. C. Main Theoretical Waveforms The main theoretical waveforms for the HIZC converter can be obtained by considering ideal components, making it easier to understand the structure. The insertion of non-ideality and parasitic components causes a more complex understanding without a significant gain. For the same reason, the HIZC modeling also considers all components as ideal. The current flows through each group formed by a switch and a diode only into an operation stage during a switching period. In the other stages, the group presents distinct voltage levels, which can be through the switch or diode. The current through these groups has the same peak, iSP. The peak current depends on the duty cycle Dz1 or Dc1. Fig 5 shows the theoretical voltages and currents for the switch S1, S2, and the diodes D1 and D2. The currents and voltages into the switches S3 and S4, besides the diodes D3 and D4, reach the same levels in distinct operation stages. The voltages across the three inductors are ideally the same level during a switching period. In the first operation stage, the voltage is the same as the PV array voltage. During the second operation stage, the voltage is the same as the power grid, and in the third operation stage, the voltages across all inductors are ideally null. The current through the inductor Lm is positive during the whole positive power grid half-cycle. On the other hand, during the negative grid half-cycle, the current through the inductor Lm assumes positive and negative levels. The inductor Li presents positive and negative current levels during the positive grid half-cycle and negative current during the negative grid half-cycle. The output inductor, Lo, presents currents synchronized with the power grid. Fig. 6 (a) exhibits the theoretical waveforms for the inductors during a switching period during the positive grid half-cyle, and Fig. 6 (b) shows the voltages and currents of the inductors during the negative power grid half-cycle. The positive and negative half-cycles of the power grid determine when the HIZC operates in the Zeta or the Ćuk mode, changing the switches' gate signals. Fig. 7 (a) shows the ideal and theoretical signals for each switch employed in the HIZC. For the positive half-cycle, the gate signal for switch S1 uses a sinusoidal pulse width modulation (SPWM). Similarly, the gate signal for switch S3 employs an SPWM during the negative half-cycle. On the other hand, S2 and S4 are commuted by the grid frequency, where S2 is turned on during the positive halfcycle, whereas S4 is turned on during the negative half-cycle. . . .Cdc S1D1 Lm C1 D2 S2 Li S3 D3 C2 D4 gS3 gS1 gS2 gS4 S4 Lo Co Lgrg . . .Cdc S1D1 Lm C1 D2 S2 Li S3 D3 C2 D4 gS3 gS1 gS2 gS4 S4 Lo Co Lgrg . . .Cdc Lm D2 S2 Li S3 D3 C2 D4 gS1 gS2 gS4 S4 S1D1C1Lo Co Lgrg This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 5 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < Currents through inductors present distinct waveshapes during the positive and negative half-cycles. According to those mentioned earlier, the input inductor Li presents the same current as the coupling capacitor C2 during the positive halfcycle. Thus, the average current is zero for each switching period. However, this inductor is magnetized and demagnetized, presenting a significant current ripple and RMS value. (a) (b) (c) (d) Fig. 5. Theoretical waveforms for the HIZC during a switching period: (a) S1 and S2 switches during the grid positive halfcycle; (b) S1 and S2 switches during the grid negative halfcycle;(c) D1 and D2 diodes during the grid positive half-cycle; (d) D1 and D2 diodes during the power grid negative half-cycle. The voltage across the coupling capacitors C1 and C2 presents distinct values. The C1 voltage is near the grid voltage, introducing a high-frequency ripple, while the voltage across the capacitor C2 exhibits the grid voltage with an offset of the PV array voltage. Therefore, the average, RMS, and maximum voltages for the capacitor C2 are higher than the C1. The output capacitor Co acts by filtering the high-frequency ripple. Thus, the voltage across this capacitor is almost the utility grid voltage. All inductors present the same voltage during each operation stage if the voltage ripples are neglected. Each switching period is divided into three subintervals, where during the first, the voltage is the same, independent of the grid voltage condition. The voltage across all inductors during the second subinterval is approximately the power grid voltage, and during the third subinterval, the voltages across all inductors are ideally zero. Fig. 8 shows voltages across the capacitors and inductors. (a) (b) Fig. 6. Theoretical current and voltage waveforms for the inductors of the HIZC during a switching period: (a) During the positive power grid half-cycle; (b) During the negative power grid half-cycle. If the input and magnetization inductance are the same, both inductors will have equal current ripples. Thus, the magnetization inductor Lm also presents the highest ripple at the peak of the grid voltage, exhibiting a sinusoidal shape during the positive half-cycle. On the other hand, the current through the output inductor Lo presents a sinusoidal shape with a low ripple at high frequency caused by the switching. Fig. 7 (b) shows the current waveforms for the three inductors for the HIZC. (a) (b) Fig. 7. Theoretical waveforms for the HIZC during a period of the utility power grid: (a) Gate signals; (b) Inductors currents. vS1 vS2 iS1 iS2 Dz1TSDz2TSDz3TS TS vPV+vg vPV t t t t 0 0 0 0 iSP iSP vg vS1 vS2 iS1 iS2 Dc1TSDc2TSDc3TS TS 2vPV t t t t 0 0 0 0 vPV vPV+vg vD1 vD2 iD1 iD2 Dz1TSDz2TSDz3TS TS -(vPV+vg) -vg t t t t 0 0 0 0 iSP iSP vD1 vD2 iD1 iD2 Dc1TSDc2TSDc3TS TS t t t t 0 0 0 0 vPV+vg TS t t t 0 0 0 -vg V PV vLm =vLi=vLo iLm ILmmax ILmmin iLi ILimax ILimin t 0 iLo ILomax ILomax ILo DZ1 TSDZ2 TSDZ3 TS TS t t t 0 0 0 vLm =vLi=vLo iLm -ILmmax -ILmmin iLi -ILimax -ILimin t 0 iLo -ILomin -ILomax ILo DC1 TSDC2 TSDC3 TS V PV vg gS1 2π t t t 0 0 0 π 3π/2 π/2 0 t 0 gS2 gS3 gS4 iLm iLi iLo 2π t t t 0 0 0 ILip ILmp π 3π/2 π/2 0 This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 6 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < Fig.8. Theoretical voltage waveforms for the HIZC during a period of the utility power grid. D. Main Equations and Static Gain This section presents the main equations related to the steady-state analysis in order to obtain the HIZC static gain. Hence, by analyzing the HIZC operation mentioned in Section II. A and II.B, the equations are derived for a single switching period. As is well-known, the average inductor voltage is null in a steady state. Thus, analyzing the voltage across the Lm inductor in Zeta mode, the following relation is obtained: 𝑣𝐿𝑚 =𝑣𝑃𝑉𝐷𝑧1 −𝑣𝐶1𝐷𝑧2 +(𝑣𝑃𝑉 +𝑣𝐶1 −𝑣𝐶2 +𝑣𝐿𝑖)𝐷𝑧3 =0. (1) The voltage across the inductor Li, in the Zeta mode, is given as: 𝑣𝐿𝑖 =(𝑣𝐶2 −𝑣𝐶1)𝐷𝑧1 +(𝑣𝑃𝑉 −𝑣𝐶2)𝐷𝑧2 +(𝑣𝑃𝑉 +𝑣𝐶1 −𝑣𝐶2 +𝑣𝐿𝑚)𝐷𝑧3 =0. (2) The output inductor, Lo, presents the average voltage related by: 𝑣𝐿𝑜 =(𝑣𝑃𝑉 +𝑣𝐶1 −𝑣𝑔)𝐷𝑧1 −𝑣𝑔𝐷𝑧2 +(𝑣𝐶1 −𝑣𝑔+𝑣𝐿𝑚)𝐷𝑧3 =0. (3) Some relations are established when equating (1)-(3), such as the voltage relation vC2 = vC1+vPV. The average voltage across the coupling capacitor C2 is higher than the C1 voltage. This response is expected because of characteristics from the Zeta and Ćuk converters. The C1 average voltage during each switching period is near the grid voltage, vC1 = vg. Evaluating the voltages during the third operation stage, Dz3Ts, the sum of the Lm and Li is an equal relation between the PV array voltage and the coupling capacitors voltages, vLm+vLi = vPV+vC1-vC2. As mentioned before, vC2 = vPV+vC1, resulting in vLm+vLi = 0. Additionally, during this operation stage, the voltage across the output inductor can be expressed using the Lm or Li voltage. Thus, the voltages across the three inductors are ideally null in the third operation stage. Considering the null voltage during the third operation stage, from (1), the HIZC static gain is obtained as per: 𝐺𝑠=𝑣𝑔 𝑣𝑃𝑉 =𝐷𝑧1 𝐷𝑧2. (4) According to the indicated voltages, all inductors are charged and magnetized with nearly the PV-array voltage during the first operation stage, reaching the maximum value at the end of the first operation stage, Dz1Ts. During the first operation stage, the current through switch S1 is the sum of the three inductors' currents. In the second operation stage, the current through semiconductors starts at the maximum value and decreases to zero. Thus, the current peak in semiconductors is obtained as follows: 𝑖𝑆𝑃 =𝑣𝑃𝑉𝐷𝑧1𝑇𝑠(1 𝐿𝑚+1 𝐿𝑖+1 𝐿𝑜)= 𝑣𝑃𝑉𝐷𝑧1𝑇𝑠 𝐿𝑒𝑞 , (5) where Leq is the parallel association between the three HIZC inductances. The switch S1 presents current only during the first operation stage. Thus, its average current can be determined as follows: 𝑖𝑆𝑎𝑣 =𝑣𝑃𝑉𝐷𝑧12𝑇𝑠 2𝐿𝑒𝑞 . (6) [16] presents an approach to modeling the system in which the available power in the converter's input transfers to the switch when it is commuted on. An effective resistance, Re, processes this power. The effective resistance for the HIZC topology, using (6), is calculated as per: 𝑅𝑒= 𝑣𝑃𝑉 𝐼𝑠𝑎𝑣 =2𝐿𝑒𝑞 𝐷𝑧12𝑇𝑠. (7) Disregarding the power losses, the input power is equal to the output power. Thereby, the available energy in the PV array is injected into the power grid as a sinusoidal and controlled current. The ideal power balance is related as follows: 𝑃𝑖𝑛 = 𝑃𝑜𝑢𝑡 =𝑣𝑃𝑉2 𝑅𝑒=𝑣𝑔2𝑃𝑜𝑢𝑡 𝑣𝑔2. (8) The HIZC maximum static gain is obtained considering the inverter operation at the peak voltage of the utility grid, Vp. Hence, by manipulating (7) and (8), the static gain is determined as follows: 𝐺𝑠= 𝑉𝑝𝐷𝑧1 √4𝐿𝑒𝑞𝑃𝑜𝑢𝑡𝑓𝑠 , (9) where fs is the HIZC switching frequency, and Vp is the voltage peak of the utility grid. From (4) and (9), the subinterval Dz2 is calculated as: 𝐷𝑧2 =√4𝐿𝑒𝑞𝑃𝑜𝑢𝑡𝑓𝑠 𝑉𝑝. (10) 2π Vp t 0 π 3π/2 π/2 0 -Vp vg Vp - VPV t 0 -Vp - VPV Vp t 0 -Vp vC2 vC1 t Vp t 0 -Vp VLm = VLi = VLo VPV -VPV This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 7 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < The same analysis can be performed for the Ćuk mode, which generates the same results. This equality between Zeta and Ćuk modes is necessary for the HIZC correct operation. E. Average and RMS Current Equations Due to the DCM characteristics, RMS current values are higher when compared with the CCM operation for the same power rate. However, the efficiency of a converter operating in DCM can be as high as that of a converter operating in CCM or higher once other characteristics improve the efficiency, such as the zero current switching (ZCS), intrinsic in DCM operation [17]. Analyzing a utility grid period, inductors Lm and Li present the same average and RMS values. The computing of the average current through these inductors using a half-cycle of the power grid is found as: 𝐼𝐿𝑚,𝑖𝑎𝑣 = 𝐼1+𝐼2 8𝜋𝑉𝑝, (11) where Vp is the peak of the utility grid, I1 and I2 are calculated as follows: 𝐼1=(2𝑉𝑃𝑉𝐷z1𝑇𝑠 𝐿𝑚− 𝐼𝐿𝑜𝑚𝑖𝑛)𝜋𝐷z1𝑉𝑝−𝐼𝐿𝑜𝑚𝑖𝑛𝜋𝐷z1𝑉𝑝. (12) 𝐼2=−8𝐼𝐿𝑜𝑚𝑖𝑛(𝑉𝑝−𝑉𝑝𝐷z1 −𝑉𝑃𝑉𝐷z1). (13) The quantity ILomin is the lowest value for the output inductor at the voltage peak of the power grid and can be expressed by: 𝐼𝐿𝑜𝑚𝑖𝑛 = 2𝑃𝑜𝑢𝑡 𝑉𝑝−𝑣𝑃𝑉𝐷𝑧1𝑇𝑠(𝐷𝑧1+𝐷𝑧2) 2𝐿𝑜. (14) The integral for each period obtains the RMS value for the current through the input and magnetization inductors expressed as follows: 𝐼𝐿𝑚,𝑖𝑟𝑚𝑠 =2 3√𝐼3+𝐼4+𝐼5 𝐿𝑚 2𝜋, (15) where 𝐼3=24𝜋𝑇𝑠2𝑉𝑃𝑉 3𝐷z1 3−18𝐼𝐿𝑜𝑚𝑖𝑛𝐿𝑚𝜋𝑇𝑠𝑉𝑃𝑉 2𝐷z1 2 𝑉𝑝, (16) 𝐼4=36𝑇𝑠2𝑉𝑃𝑉 2𝐷z1 3−48𝐼𝐿𝑜𝑚𝑖𝑛𝐿𝑚𝑇𝑠𝑉𝑃𝑉𝐷z1 2, (17) 𝐼5=9𝐼𝐿𝑜𝑚𝑖𝑛 2𝐿𝑚 2𝜋. (18) Using the peak current for the semiconductors (5), the respective average and RMS currents through the switches S1 and S3 that occur only during the first operation stage (Dz1 and Dc1), can be obtained as follows: 𝐼𝑆1,3𝑎𝑣 =𝐷z1𝑖𝑆𝑃 8, (19) 𝐼𝑆1,3𝑟𝑚𝑠 =√2 3√𝐷z1(𝐼6+𝐼7+𝐼8) 𝐿𝑚 2𝜋, (20) where: 𝐼6=Dz1𝑇𝑠𝑉𝑃𝑉(4𝐷𝑧1𝑇𝑠𝑉𝑃𝑉 +3𝐼𝐿𝑜𝑚𝑎𝑥𝐿𝑚), (21) 𝐼7=3𝐼𝐿𝑜𝑚𝑎𝑥 2𝐿𝑚 2−Dz1𝑇𝑠𝑉𝑃𝑉(6𝐼𝐿𝑜𝑚𝑖𝑛𝐿𝑚), (22) 𝐼8=3𝐼𝐿𝑜𝑚𝑖𝑛 2𝐿𝑚 2−6𝐼𝐿𝑜𝑚𝑎𝑥𝐼𝐿𝑜𝑚𝑖𝑛𝐿𝑚 2. (23) Similarly, during a utility power grid period, the average and RMS currents for the switches S2 and S4 can also be achieved using (5), as follows: 𝐼𝑆2,4𝑎𝑣 =𝑉𝑃𝑉𝐷z1𝑖𝑆𝑃 2𝜋𝑉𝑝, (24) 𝐼𝑆2𝑟𝑚𝑠𝐶𝐴 =√3 6√𝑉𝑃𝑉𝐷z1(𝐼6+𝐼7+𝐼8) 𝐿𝑚 2𝜋𝑉𝑝. (25) III. MODELING AND CONTROL This section introduces the main small-signal equations related to the dynamic system operation to provide bases for obtaining the HIZC transfer functions. A. Control Design The control of the HIZC aims to perform the power transference from the PV array to the utility grid through a sinusoidal and synchronized active current, harvesting the maximum available PV array power. The HIZC is synchronized to the power grid by an adaptive filter AF-αβ-pPLL, which obtains the angle of the utility grid (θ) used in a sine function. The AF-αβ-pPLL is based on the instantaneous active power theory and designed to operate with voltage disturbances, such as sags and frequency variations, according to the results obtained in [18]. The P&O algorithm is used to perform the MPPT. Initially, the PV array voltage and current are measured to calculate the voltage reference (𝑣𝑃𝑉∗), which is used to reach the maximum power. The P&O causes small perturbances on the voltage reference and analyzes whether there is an improvement or decrement in the PV array voltage and power. Thus, the P&O updates the voltage reference [19-22]. A Proportional-Integral (PI) controller compares the reference to the PV-array voltage. This control generates a current peak (Ip) multiplied by a synchronized sine vector, resulting in the current reference. An inner PI controller compares the reference current to the output inductor current (iLo). The PI response multiplied by a PWM gain (KPWM) generates a duty cycle (d) combined with a switching logical control, which drives the power switches. The switching logic uses the PLL information to determine if the switches S1 and S2 operate (Zeta mode) or S3 and S4 (Ćuk mode) Fig. 9 (a) shows the block diagram, and Fig. 9 (b) represents the adopted switching logic. B. Equivalent Circuit The HIZC topology operates similarly to the Zeta and the Ćuk converters. In each switching period, only two switches and two diodes present current. However, the current flows in This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 8 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < all passive components during both modes. Two equivalent circuits can be obtained, the first for the operation like the Zeta converter and another for the Ćuk. (a) (b) Fig. 9. Control structure: (a) Block diagram; (b) Switching control logic. As mentioned before, the three stages of the operation for the Zeta and Ćuk modes are equivalent. By the topology design, the magnetization and demagnetization of the inductors Lm and Li present the same intensity. Thus, the HIZC modeling can be simplified using an equivalent circuit from the Zeta or one other from the Ćuk mode. The response from both equivalent circuits must be similar to guarantee the adequate operation of the HIZC. A representation of the inductors Lm and Li is employed in the equivalent circuits and named Le, calculated by the parallel association of the Lm and Li inductors, Le = (Lm+Li)/LmLi. Additionally, these inductances present the same value so that the Le inductance can be expressed as Le= Lm/2=Li/2. The coupling capacitors, C1 and C2, also present current flow during the entire HIZC operation. Thus, an equivalent capacitance, named Ca, is adopted. This capacitance is the parallel association between C1 and C2, Ca = C1+C2. Fig. 10 (a) represents the Zeta mode equivalent circuit, and Fig. 10 (b) represents the Ćuk mode. (a) (b) Fig. 10. Equivalent circuit: (a) Zeta mode; (b) Ćuk mode. C. Inner Loop Modeling State-space averaging (SSA) is widely employed in modeling linear systems. Commonly, the currents through inductors and the voltages across capacitors are chosen as state variables in electrical systems, while the voltages and current sources are adopted as system inputs [23]. Static converters can be modeled using the SSA method in both CCM and DCM operation modes. When a static converter operates in CCM, the SSA presents a satisfactory representation, where each subinterval has its matrices related, and the average model is quickly obtained from the pondered meaning. On the other hand, when a static converter operates in DCM, the pondered meaning in the SSA method presents errors caused by the differences between the RMS and average values, mainly in the inductors' currents. In [24], a correction matrix called M adequates the state's matrix, presenting good results for second-order converters, such as Buck, Boost, and Buck-Boost. However, the approach presented in [24] is inadequate for fourth-order converters. On the other hand, [17] proposes a generalized method for fourthorder power converters, which is used in [9] to model an integrated inverter based on Zeta topology. This approach results in good modeling for fourth-order converters, such as Zeta, Ćuk, and SEPIC. Thus, the proposed HIZC can be modeled similarly. Using the correction approach for DCM operation and the SSA method initially, the modeling of the HIZC is described as per: 𝑥󰇗=𝑀𝐴𝑚𝑥+𝐵𝑚𝑢, (26) 𝑦=𝐶𝑥. (27) The vector 𝑥 represents the average states variables (inductors currents and capacitor voltages), Am, is the average states matrix during the three operation stages, Bm is the average input matrix, and 𝑢 vector represents the input system, in this case, PV array and utility grid voltages. The M matrix is expressed as [17]: 𝑀= [ 1−𝐷𝑏 𝐷𝑎00 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ] . (28) From the HIZC equivalent circuit during Zeta mode [see Fig. 8 (a)] and its operation presented in Section II and in Fig. 1 and Fig. 3, the SSA model considering the correction approach is determined as follows: [ 𝑖󰇗𝐿𝑒 𝑖󰇗𝐿𝑜 𝑣󰇗𝐶𝑎 𝑣󰇗𝐶𝑜 𝑖󰇗𝐿𝑔 ] = [ 0 0 𝑎13 𝐷z3 𝐿𝑒+𝐿𝑜0 0 0 𝑎23 𝑎24 0 𝐷𝑧2−𝐷𝑧2 2 𝐶𝑎𝐷𝑎𝐷𝑧2−1 𝐶𝑎0 0 0 01 𝐶𝑜0 0 −1 𝐶𝑜 0 0 1 𝐿𝑔0−𝑟𝑔 𝐿𝑔 ] [ 𝑖𝐿𝑒 𝑖𝐿𝑜 𝑣𝐶𝑎 𝑣𝐶𝑜 𝑖𝐿𝑔 ] KPWM d iLo Ip Sin(θ) MPPT vPV iPV vPV * PLL iLo * vg Kpi Kii /s Kpv Kiv /s gS1 gS2 gS3 gS4 PWM >0 sin(θ) d > vPV S1D1 S2 D2 Cdc Lo Le Ca vCdc gS2 gS1 Covg iLe vLe iLo + - +- vLo +- vCa iCa . . . Lg iLg +- vLg rg + - vCo + - + - vPV S1 D1 S2 D2 Cdc Lo LeCa vCdc gS2 gS1 Covg iLe vLe iLo +- +- vLo +- vCa iCa . . . Lg iLg +- vLg rg + - vCo + - + - This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 9 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < + [ 𝐷𝑧1 𝐿𝑒0 𝐷𝑧1 𝐿𝑜0 0 0 0 0 0−1 𝐿𝑔 ] [𝑣𝑃𝑉 𝑣𝑔], (29) 𝑦=[0 1 0 0 0] [ 𝑖𝐿𝑒 𝑖𝐿𝑜 𝑣𝐶𝑎 𝑣𝐶𝑜 𝑖𝐿𝑔 ] , (30) where 𝑦 represents the output vector; 𝑎13 =−(𝐿𝑒+𝐿𝑜)𝐷z1−𝐿𝑒𝐷z3 𝐿𝑒(𝐿𝑒+𝐿𝑜); 𝑎23 =(𝐿𝑒+𝐿𝑜)𝐷z1−𝐿𝑜𝐷z3 𝐿𝑜(𝐿𝑒+𝐿𝑜), and 𝑎24 =−(𝐷𝑧1+𝐷𝑧2)(𝐿𝑒+𝐿𝑜)−𝐿𝑜𝐷z3 𝐿𝑜(𝐿𝑒+𝐿𝑜). If the converter acts in CCM, the third subinterval is eliminated. However, eliminating this operation stage (29) will be adequate for the average model, and (30) will not be altered. When HIZC acts in the Ćuk mode, its functionality is equivalent to the Zeta mode. The average voltage across the capacitor Ca is distinct because of characteristics from the Zeta and Ćuk converters. The other states' variables and inputs are unaltered. In the equivalent circuit of the Zeta mode, the PV array supplies energy for HIZC only during the first operation stage. However, in the equivalent circuit of the Ćuk mode, the PV array provides energy for HIZC during the whole structure functionality. Thus, each case's input matrix, Bm, must be distinct. Equalizing the operation stages, i.e., Dz1Ts = Dc1Ts, Dz2Ts = Dc2Ts, and Dz3Ts = Dc3Ts, and using the equivalent circuit for this mode [see Fig. 10(b)], a SSA representation can be found as follows: [ 𝑖󰇗𝐿𝑒 𝑖󰇗𝐿𝑜 𝑣󰇗𝐶𝑎 𝑣󰇗𝐶𝑜 𝑖󰇗𝐿𝑔 ] =𝐴𝑚 [ 𝑖𝐿𝑒 𝑖𝐿𝑜 𝑣𝐶𝑎 𝑣𝐶𝑜 𝑖𝐿𝑔 ] + [ 𝑏11 0 𝐷𝑐3 𝐿𝑜0 0 0 0 0 0−1 𝐿𝑔 ] [𝑣𝑃𝑉 𝑣𝑔], (31) where b11 = (𝐷𝑐1+𝐷𝑐2)(𝐿𝑒+𝐿𝑜)+𝐷𝑐3𝐿𝑒 𝐿𝑒(𝐿𝑒+𝐿𝑜) The Am matrix is the same in both HIZC modes, resulting in the same poles from (29) and (31). This conclusion indicates that Zeta and Ćuk modes have similar dynamics and comportment. [16] proposed a generalized switch averaging (GSA) for modeling DCM converters. The GSA approach divides the converter into two subsystems: i) one linear, formed by the passive elements, which can be represented for the SSA model; ii) one non-linear, formed by the semiconductors. [9] models an integrated inverter based on a Zeta converter for grid-tied applications using this association, presenting a high similarity between the mathematical model and a simulated circuit. The non-linear subsystem obtains three gains: one for the duty cycle, one for the voltage across the switch, and another for the diode current [16]. In the HIZC, the voltage across the switch is considered the voltage across the association of S1 and D1. For the current diode, the current is adopted through the diode D2. The three gains are presented as follows: 𝑘𝑐= 2𝐷𝑧2 (𝐷𝑧1+𝐷𝑧3)2, (32) 𝑘𝑣𝑠 = 𝐷𝑧1𝐷𝑧2 𝑣𝑃𝑉(𝐷𝑧1+𝐷𝑧3)2, (33) 𝑘𝑖𝑑 = −𝑅𝑒𝐷𝑧12 𝑣𝑃𝑉(𝐷𝑧1+𝐷𝑧3)2. (34) The transfer function that relates the output inductor, Lo, to the duty cycle for the HIZC topology is determined as follows: 𝐺𝑖𝑑(s)=𝑖𝐿𝑜(𝑠) 𝑑 (𝑠) =𝐶(𝑠−𝑀𝐴𝑚+𝐵𝑑𝑘𝑠𝑀𝐶𝑚 1−𝑘𝑠𝐸𝑑)−1 𝐵𝑑𝑘𝑐 1−𝑘𝑠𝐸𝑑, (35) where 𝑘𝑠=[𝑘𝑖𝑑 𝑘𝑣𝑠], and the matrices 𝐵𝑑 and 𝐸𝑑 are defined as follows: 𝐸𝑑=[𝐶1−𝐷𝑧2 1−𝐷𝑧1𝐶2−𝐷𝑧3 1−𝐷𝑧1𝐶3] [ 𝑖𝐿𝑒 𝑖𝐿𝑜 𝑣𝐶𝑎 𝑣𝐶𝑜 𝑖𝐿𝑔 ] +[𝐸1−𝐷𝑧2 1−𝐷𝑧1 𝐸2−𝐷𝑧3 1−𝐷𝑧1 𝐸3][𝑣𝑃𝑉 𝑣𝑔], (36) 𝐵𝑑=[𝐴1−𝐷𝑧2 1−𝐷𝑧1 𝐴2−𝐷𝑧3 1−𝐷𝑧1 𝐴3] [ 𝑖𝐿𝑒 𝑖𝐿𝑜 𝑣𝐶𝑎 𝑣𝐶𝑜 𝑖𝐿𝑔 ] +[𝐵1−𝐷𝑧2 1−𝐷𝑧1 𝐵2−𝐷𝑧3 1−𝐷𝑧1 𝐵3][𝑣𝑃𝑉 𝑣𝑔], (37) where the matrices A1, A2, A3, B1, B2, and B3 are the states' and inputs' matrices for the SSA during the three operation stages Dz1Ts, Dz2Ts, and Dz3Ts. Matrices C1, C2, and C3 are the output matrices for the GSA, while E1, E2, and E3 are the direct transition matrices. The matrix Cm is obtained by the operation averaging, i.e., Cm = C1Dz1 + C2Dz2 + C3Dz3. Using the modeling of the equivalent circuit for the Ćuk mode gets a close response. The transfer function exhibits the same structure shown in (20), with only some distinct matrices. The high similarity between both models is corroborated by plotting the frequency response for the transfer functions and the switched converter, as demonstrated in Fig. 11. Fig. 11. Frequency responses for nominal operating values. Ćuk mode Zeta mode Switched converter Ćuk mode Zeta mode Switched converter Magnitude (dB) Phase (deg) Frequency (Hz) This article has been accepted for publication in IEEE Open Journal of Power Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/OJPEL.2025.3576296 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 16 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID NUMBER (DOUBLE-CLICK HERE TO EDIT) < [20] S. K. Kollimalla and M. K. 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