Compherensive design of a 100 kW/400 V high performance AC-DC converter

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER Compherensive Design of a 100 kW/400 V High Performance AC-DC Converter Ghasem ESFANDIARI, Hadi ARAN, Mohammad EBRAHIMI Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran [email protected], [email protected], [email protected] DOI: 10.15598/aeee.v13i5.1313 Abstract. In this paper, a comprehensive design for a 100 kW/400 V, three-phase pulse-width modulated (PWM) AC-DC converter is presented that serves as the front-end power supply for wide-range varying active load. This power supply includes two series stages; a six-switch AC-DC boost converter and a DC-DC buck converter to regulate 400 VDC at load side. The design of all inductors and capacitors is fulfilled using mathematical expressions. In addition, small signal modelling and controller design are presented in order to raise the design efficiency of the proposed converter. Also, due to the high power application, improved softswitching techniques are applied. Furthermore, systematic approach to design an input EMI filter for DCDC converter is explained. The simulation results performed by PSCAD software show that high performance of the proposed power supply is obtained in terms of stability, high power factor, high efficiency and low total harmonic distortion (THD). Keywords AC-DC converter, controller design, small signal modelling, soft-switching technique. 1. Introduction Three-phase AC-DC electric power conversion is widely employed in diverse applications such as adjustablespeeds drive, uninterruptible power supplies, HVDC systems, etc. [1], [2], [3]. Conventionally, AC-DC converters known as rectifiers are developed using diodes and thyristors to provide uncontrolled and controlled DC power. They have poor power quality, low power factor, high THD and low efficiency. Besides, they need large size of AC and DC filters. Nowadays, it is a common concern to use converters which provide reduced size, high power factor, high efficiency, low THD and well controlled DC voltage to present flexible system operation. Therefore, with the advent of new solid-state self-commutating devices such as IGBTs, MOSFETS, GTOs, etc., new converters are known as switch-mode rectifiers (SMRs), power factor correctors (PFCs), PWM rectifiers, multilevel and multi-pulse rectifiers [4], [5]. Appropriate modeling and control of PWM converters are increasingly being regarded in high power applications. As design of inductors and capacitors in power converters are based on the requirements of application, proper analytical expressions should be fulfilled. Also, in most cases of converters’ controller design, there are two steps: selection of modulation strategy, which corresponds to open-loop control, and design of dynamic closed-loop control. Therefore, development of converters’ small signal models is the best well-known approach to design proper controller [6], [7], [8]. High-power converters suffer considerably from low switching frequency due to the high switching losses. Thus, adverse control bandwidth and large passive components are achieved by low switching frequency. On the other hand, since high switching noise is more intense in high power converters, soft switching techniques are the best options to improve switching noise as well as switching frequency. In high power converters, zero-current-transition (ZCT) technique is a pleasing method, where the IGBTs are power devices [9], [10]. The topology of the presented 100 kW/400 V AC-DC converter is shown in Fig. 1. It includes two stages: a six-switch AC-DC boost converter equipped with soft switching technique in series with a soft switched DC-DC buck converter. The proposed converter is connected to a three-phase, 50 Hz utility grid with Vrms = 220 V. c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 417 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER This paper is organized as follows: Section 2. gives mathematical expressions to design passive components of the proposed topology which are essential to extract converters’ small signal model and then to design controller. Section 3. presents theoretical expressions to design auxiliary circuits of improved soft switching techniques for both stages. Also, Section 4. includes the details of designed EMI filters for DC-DC buck converter. Simulation results are shown in Section 5. . Finally, in Section 6. the conclusion is drawn. Va Vb VcL S1 S4 LxCx S4x S1x S3 S6 S6x S3x S5 S2 S2x S5x C In EMI Filter Lr2 Cr2 DFCb Lb Out EMI Filter Load Fig. 1: The topology of proposed AC-DC converter. 2. Small Signal Modelling and Controller Design In this section, firstly passive components of both ACDC boost and DC-DC buck converters are designed based on the requirements of the presented application. Then, small signal models of both converters are extracted to design proper controllers. 2.1. Design of Passive Components 1) Six-Switch AC-DC Boost Converter To obtain optimal value of boost inductor and DC-link capacitor, single-input-single-output (SISO) model of six-switch AC-DC boost converter by separating the daxis and the q-axis dynamics is used [11]. Being nonminimum phase as an inherent feature in mentioned converter is revealed by a simple right-half-plane zero (RHPZ) in the small signal control-to-output transfer function ~vdc(s)/~ d(s). The desirable performance of converter is largely affected by RHPZ which completely depends on the boost inductor value. Since the location of the RHPZ is closest to imaginary axis in the complex s-plane under the worst operating conditions, the main aim is to design boost inductor to achieve favorable performance. On the other hand, the value of DC-link capacitor depends on the value of the boost inductor. High values of boost inductors results in low values of DC-link capacitors. Thus, there is a tradeoff between selection of boost inductor and DC-link capacitors. Figure 2 is used to gain control-to-output transfer function by SISO model. The differential equations n ea eb ec L,R L,R L,R ea eaia ib ic m Load SaSb Sc icidc vdc C S'c S'b S'a van vbn vcn Fig. 2: A six-switch AC-DC boost converter. of the system in the synchronous rotating d-q frame are as follows: Ldid dt+RLid−Lωiq=ed−vd,(1) Ldiq dt+RLiq−Lωid=eq−vq.(2) Cdvdc dt=3 4(udid+uqiq)−idc,(3) where edand eqare source voltages and idand idrepresent the input currents in d−qframe. Also, the control inputs vdand vqare related to the ddc by Eq. (4). vd=udvdc 2, vq=uqvdc 2, (4) where udand uqare switching functions. Decoupling of idand idin Eq. (1) and Eq. (2) is achieved by defining vdand vqas Eq. (5). vd vq=vd1+vd2 vq1+vq2. vd1 vq1=  ud1 vdc 2 uq1 vdc 2 =Lωiq −Lωid. (5) Applying decoupling control variables, differential Eq. (1), Eq. (2) and Eq. (3) are convertd to Eq. (6), Eq. (7) and Eq. (8). Ldid dt+RLid=ed−vd2=ed−ud2vdc 2.(6) Ldiq dt+RLiq=eq−vq2=−uq2vdc 2.(7) Cvdc dvdc dt+vdcidc =3 2(vd2id+vq2iq) = =3 4ud2vdcid. (8) c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 418 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER In normal conditions, the term vq2iqcan be ignored, due to zero value of iqcreated by control system. By substituting ud2= 1 −d=D0−~ d, ed=Ed+~ed, idq = Idq +~ idq, vdc =Vdc +~vdc, vc=Vc+~vcand D0= 1 −D in Eq. (6) and Eq. (8), small signal and dc models can be written as Eq. (9), Eq. (10), Eq. (11), Eq. (12) and Eq. (13). Ld~ ld dt+RL~ ld=~ed−(D0~vdc −vdc ~ d) 2.(9) Cd~vc dt+~vdc Rdc =3 4D0~ ld−Id~ d. (10) ~vdc =~vc+RcCd~vc dc.(11) Vdc = 3 4D0Ed RL Rdc +3 8D02 .(12) Id=Ed RL+3 8RdcD02 .(13) Therefore, small signal model of Fig. 2 in d-axis frame is shown in Fig. 3. 3/2 e(t) 3/2 L 3/2 RL3/4 Rdcd(t) id(t) 3/4 D:1 3/4 Did(t) 3/4 Idd(t) vc(t) v(t) Rdc C Fig. 3: Small signal model of Fig. 2 in d-axis frame. Equation (12) and Eq. (13), express the relation between Vdc and Idwith steady state duty cycle D, RL, Rdc and Ed. Using Eq. (12), the minimum and maximum amount of output voltage is provided by Dmin = 0 and Dmax = 1 −r8RL 3Rdc , respectively. Therefore, the boundaries of Vdc can be defined by Eq. (14).    2RdcEd 8RL 3+Rdc   ≤Vdc ≤     3 4(1 −Dmax)Ed RL Rdc +3 8(1 −Dmax)2     . (14) The output-to-control transfer function ~vdc(s) ~ ds is calculated based on Fig. 3 as following. ~vdc(s) ~ d(s)=KDC 1 + N1s+N2s2 1 + M1s+M2s2, N1=(D0VdcRcC−2LId−2RLRcIdC) D0Vdc −2RLId , M1=C(8RL(Rc+Rdc)+3D02RdcRc)+8L 8RL+ 3D02Rdc , N2=−2LCRcId D0Vdc −2RLId , M2=8LC(Rc+Rdc) 8RL+ 3D02Rdc , KDC =6RdcEd(3D02Rdc −8RL) (8RL+ 3D02Rdc)2. (15) To calculate boost inductor value, suppose that the voltage drop across the inductor at full load is x % of the source voltage Ed, and then using Eq. (16) the value of Lis obtained. pR2 L+ (Lω)2Id=x 100Ed⇒    (pR2 L+ (Lω)2) RL+3 8RdcD02  =x 100, L=sx 100 RL+3 8RdcD022 −R2 L 2πf . (16) In Eq. (16), to have real values for L, the term under radical must be positive. Thus, voltage drop on the boost inductor has a minimum value presented in Eq. (17). x≥100RL RL+3 8RdcD02 .(17) Also, the value of D0in Eq. (16) can be acquired by quadratic Eq. (18) obtained from Eq. (12). (RdcVdc)D02−(2EdRdc)D0+8 3RLVdc = 0.(18) To solve Eq. (18), the constraint ∆≥0must be satisfied. Consequently, the value of boost inductor resistance has a maximum value given in Eq. (19). RL≤3E2 dRdc 8V2 dc .(19) c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 419 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER To dictate desirable performance to the proposed converter, the capacity od DC-link capacitor is selected such that corner frequency (fp) of complex poles in the transfer function ~vdc(s) ~ d(s)to be approximately three of four times less than the frequency of RHPZ. The complex poles of Eq. (15) which are as 1 + 2ξ ω0s+1 ω2 0s2= 0, have corner frequency fp and damping factor ξwritten by Eq. (20) and Eq. (21). fp=1 2πs8RL+ 3D02Rdc 8LC(Rc+Rdc).(20) ξ=C(8RL(Rc+Rdc)+3D02RdcRc)+8L 2p(8LC(Rc+Rdc))(8RL+ 3D02Rdc).(21) Therefore, Eq. (22) gives the value of C. C=8RL+ 3D02Rdc 8L(Rc+Rdc)(2πfp)2.(22) In this paper, the reference output voltage for sixswitch AC-DC boost converter is considered Vdc = 650 V. Therefore, for Rdc =4Ωand Ed= 311.1V, the maximum permissible value of boost inductor resistance is RL≤0.343 Ω. Suppose that RL= 0.1 Ω, then Dmax = 0.74 or D0 min = 0.26. Also, using Eq. (18), D0 can be found as (2600)D02−(2488.8)D0+173.33 = 0 ⇒ D0= 0.88. Consequently using Eq. (17), the minimum acceptable value of xwould be 8 %. Finally, considering x= 12 %, the designed value of boost inductor by Eq. (16) is L= 350 µH. With this inductor value, the frequency of RHPZ is 485 Hz. Considering fp=fRHP Z /3and RC= 0.1, the selected value for C would be 860 µF. 2) DC-DC Buck Converter Evaluating DC-DC buck converter circuit in Fig. 4 during time intervals 0< t ≤DT (position 1, switch on) and DT < t ≤T(position 2, switch off), the maximum peak-to-peak ripple current of inductor Lis as follows [12]: ∆iLmax =v0(1 −Dmin) fsL,(23) where Tis switching period, Dis duty cycle, fS= 100 kHz is switching frequency and VO= 400 V is converter output voltage. The minimum inductance required to maintain the continuous conduction mode operation for the duty cyRon ig(t) Vg(t) 1 2 L RL V0(t) R0 vc(t) rc RD C i(t) VD Fig. 4: Equivalent circuit of PWM DC-DC buck converter. cle with the range of [Dmin, Dmax]is given by Eq. (24). Lmin =R0max(1 −Dmin) 2fs ,(24) where R0max corresponds to the lowest level of converter load which is considered to be 1.5 kW. The peakto-peak ripple voltage is independent of the voltage across Cand will be determined only by the ripple voltage across the equivalent series resistance if Eq. (25) is satisfied. Cmin =max(Dmax,1−Dmin) 2fsrc .(25) Vr=rc∆iLmax.(26) Usually, Vris allowed to be 1 % of output voltage. In the proposed topology, the input and output voltage of the buck converter is set to be 650 V and 400 V, respectively. Therefore, considering 100 V input voltage ripple and 90 % efficiency, minimum and maximum value of duty cycle is as: Dmin =V0 ηVgmax =400 0.9·750 = 0.592,Dmax =V0 ηVgmin =400 0.9·550 = 0.807 ⇒ ∆iLmax = 6.5A⇒rcmax =0.01 ·V0 ∆iLmax = 0.615. Suppose, rc= 0.1 Ω, finally, the obtained minimum values for inductor and capacitor of buck converter are 217.6 µH and 40.35 µF. In this paper, selected passive components for DC-DC buck converter are 250 µH and 100 µF. 2.2. Small Signal Modelling 1) Six-Switch AC-DC Boost Converter The first step to design a proper controller for ACDC converters is the extraction of differential equations in the d-q frame to form converter’s average model. Then, small signal analysing should be fulfilled to obtain converter’s small signal model. Next, various transfer functions should be calculated using small signal model. The control method used in this paper is based on the reference [6]. Figure 5 shows standard c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 420 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER control scheme of the converter in d-q frame. Therefore, Eq. (27), Eq. (28) and Eq. (29) which represent the average model of a six-switch AC-DC boost converter based on line-to-line quantities are used to small signal modelling. Vref Vdc Hv(s) - Voltage Compensator idref id iq iqref Kp+Ki/S Kp+Ki/S dd1 dd dq1 dq 3Lω/Vref 3Lω/Vref Fig. 5: Standard control scheme of six-switch boost converter in d-q frame. did dt =ω1−vdc vref iq−RL Lid+ 1 3LVd−1 3Ldd1vdc. (27) diq dt =−ω1−vdc vref id−RL Liq−1 3Ldq1vdc.(28) dvc dt =3 2C(dd1id+dq1iq)−1 cidc.(29) where id,iqare line-to-line currents, dd1,dq1are duty cycles in d-q frame, Vdis input line-to-line voltage in d-axis and Vref is desired output voltage. In these equations, cross-coupling between idand iqcurrents is reduced by term 1−vdc Vref , when two terms 3Lω Vref and −3Lω Vref are added to duty cycles dd1,dq1. In a similar way, by substituting idq =Idq +~ idq, dd1=Dd1+ ~ dd1, dq1=Dq1+~ dq1, vdc =Vref +~vdc and idc =Idc +~ idc in Eq. (27), Eq. (28) and Eq. (29), small signal and dc models are written by Eq. (30), Eq. (31), Eq. (32), Eq. (33) and Eq. (34). 3Ld~ ld dt+ 3RL~ ld=−3LωIq Vref −Dd1~vdc− −~ dd1Vref . (30) 3Ld~ lq dt+ 3RL~ lq=3LωIq Vref −Dq1~vdc− −~ dq1Vref . (31) Cd~vc dt = 1.5(~ dd1Id+Dd1~ id+~ dq1Iq+Dq1~ lq)− −~vdc Rdc . (32) Dd1=Vd−3RLId Vref , Dq1=−3RLIq Vref .(33) Id= vd−qv2 d−8RLIdcVref −36R2 LI2 q 6RL .(34) After small signal modelling, in this control method two main transfer functions ~ lq(s) ~ lq,ref (s)and ~vdc(s) ~ ld,ref (s) should be acquired. According to Fig. 5, the first transfer function is used to design a PI controller for power factor correction. The designed gains for PI controller are KP=40 and Ki=1·105. The second transfer function is obtained to design voltage compensator. Equation (35) and Eq. (36) represents the main transfer functions. Figure 6 illustrates the control diagram used to design current and voltage compensators. The control gains are determined in a way that control loops in Fig. 6 present stable performance with adequate phase and gain margins. Converter + PI Compensator Gi(s) id,ref(s) id(s) iq,ref(s) id(s) (a) Hv(s) Gv(s) PI Compensator Converter Vdc,ref(s) Vdc(s) id,ref(s) (b) Fig. 6: Control diagram of (a) current and (b) voltage loops for a six-switch AC-DC boost converter. In this paper, a three-pole one-zero compensator (HV(s)) is used to regulate output voltage. Hv(s) = Kv(s) = Kv1 + s ZV s1 + s PV1 + s PC.(37) The gain KVshould be sufficiently large to have proper phase margin. On the other hand, to have fast transient response, ZVis determined based on Eq. (38). Zv≤1 4ZRHP .(38) Also, pole PVis relatively placed close to ZRHP after the crossover frequency, which leads to proper damping and gain margin in control system. In addition, c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 421 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER ~ lq(s) ~ lq,ref (s)=~ ld(s) ~ ld,ref (s)= 1 + KP Ki s 1 + 3RL+KpVref KiVref s+3L KiVref s2 .(35) Gv(s) = ~vdc(s) ~ ld,ref (s)=1.5(RdcKiH+ (RdcX+RpCKiH)s+ (RpCX −3RdcKpL)s2−(3RpCKpL)s3) KiVref + (KiVref RtC+Q)s+ (3L+QRtC)s2+ (3LCRt)s3, H=Dd1Vref −3RL, X =KpH−3KiL, Q = 3RL+KpVref , Rt=Rc+Rdc, Rp=RcRdc. (36) pole PCis close to frequency 1 Rc·Cto compensate the effect of capacitor equivalent series resistance. All control gains of designed controller for three different levels of output power are depicted in Tab. 1. Tab. 1: Control gains of HV(s). Output power Control gains KvZvPvPc 1.5 kW 137 169.5 3030.3 11628 50 kW 100 3125 7142.8 11628 100 kW 300 3125 7142.8 11628 2) DC-DC Buck Converter A typical way to generate small signal model of DC-DC converters is the state-space description, which writes the differential equations that describe the converter [8]. Generally, the state equations of a system can be written in the compact matrix form of Eq. (39). Kdx(t) dt=A~x(t) + B~u(t), ~y(t) = C~x(t) + E~u(t). (39) Considering Fig. 4 as our system, ~x(t)is a vector containing [i(t), vc(t)], ~u(t)contains [Vg(t), VD] and ~y(t) includes [ig(t), vO(t)]. Equation (39) is written with index “1” when switch is on, and with index “2” when switch is off. Afterward, Eq. (40) and Eq. (41) represent small signal model of the system. Kd~x(t) dt=A~x(t) + B~u(t) + ((A1−A2)X+ +(B1−B2)U)~ d(t), (40) ~y(t) = C~x(t) + E~u(t) + ((C1−C2)X+ +(E1−E2)U)~ d(t), (41) where A=DA1+D0A2, B =DB1+D0B2, C = DC1+D0C2, E =DE1+D0E2. In these equations, Dis steady state duty cycle and D0= 1 −D. The value of state vector and output variables in steady state are as follows: X=−A−1BU, Y= (−CA−1B+E)U. (42) The small signal circuits of analyzed DC-DC buck converter is shown in Fig. 7. vc(t) v0(t) R0 C i(t) L vg(t) id(t) ig(t) 1:D RL+DRon+D'RD (Vg+VD+(RD-Ron)I)d(t) Fig. 7: Small signal model for a non-ideal DC-DC buck converter. To control the DC-DC buck converter, the main transfer function Gvd(s) = ~vO(s) ~ d(s)should be calculated based on Fig. 7, while ~vg= 0 and ~ iload = 0. Gvd(s) = R0·Vit + (VitR0CRC)s) (M0)+(M1)s+ (M2)s2, Vit =Vg+Vd+ (RD−Ron)I, M1=L+R0CRC+ROU ·RLnC, M2=ROU ·LC, M0=R0+RLn, ROU =R0+RC, RLn =RL+D0RD+DRon. (43) c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 422 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER Then, using control diagram of Fig. 8, compensator GC(s)is designed in a way that output voltage is regulated with wide bandwidth and zero steady state error. Gc(s) Gvd(s) Compensator Converter Vref=0 V0(s) d(s) Fig. 8: Control diagram of a DC-DC buck converter. Therefore, the best option for compensator seems to be a PID controller presented by Eq. (44). Gc(s) = GC01 + ωL s1 + s ωz 1 + s ωp11 + s ωp2.(44) For above compensator designed parameters are: GC0= 0.3,ωL= 1695,ωZ= 8333.3,ωp1= 117647 and ωp2= 3.45 ·1011. 3. Soft-Switching Techniques As in high power converters hard-switching techniques produce high switching losses and intense conductive EMI, soft-switching techniques draw more attention in this regard. It is well known that in high power converters where power switches are IGBTs, ZCT techniques are attractive. Thus, in this section two different improved ZCT (IZCT) techniques are presented for both stages of proposed topology. 3.1. IZCT Technique for Six-Switch AC-DC Boost Converter Figure 9 shows one leg of IZCT circuit implemented for phase a. It includes two main switches (S1and S2), two auxiliary switches (S1xand S2x) and one LC resonant tank (Lxand Cx). In this circuit, not only each phase leg has an independent soft switching, but also voltage stresses across all devices are preserved to the level of DC-link voltage [9]. Vdc C0 S2x S1x D2x D1x Lx IxVcx Cx D1 D2 L IL Vsa Fig. 9: IZCT circuit for phase a leg. In Fig. 9, the relationship between main switches and corresponding auxiliary switches is diagonal. It means S1xis turned on and turned off when S1is going to be turned on. Also, S1xhas another similar operation when S1is turned off. The gating method of both main and auxiliary switches is clearly depicted in Fig. 10. S1 S1x S2x S2 S1x S2x Fig. 10: Gating method in IZCT technique for six-switch ACDC boost converter. In order to design LC resonant tank using Eq. (45), three steps should be performed to obtain the values of T0and Z0. Lx=Z0T0 2π, Cx=LxT0 Z2 0 . (45) First, normalization factors such as maximum DClink voltage (Vdcm) and maximum phase current (ILm) are determined and normalized quantities are written as: ILn =IL ILm , Vdcn =Vdc Vdcm , Z0n=Z0 ILm Vdcm , where ILis phase current, Vdc is voltage of DC-link and Z0is resonant tank impedance. Second, in order to achieve soft switching operation, parameter koff should satisfy Eq. (46). koff =3Vdcn Z0n·ILn − −s4−Vdcn Z0n·ILn 2 + 1 ≥1. (46) The value of Z0and koff is determined by Eq. (46). In the third step, parameter T0is determined by Eq. (47). T0=πToff cos−11 koff .(47) where Toff is device dependent and it should be more than main IGBT current fall time (i.e. 0.8 µs). Afterward, the pulse width of auxiliary switches in on/off operation can be set by Eq. (48), where koff is equal to koff when Vdcn=1 and ILn=1. PWsx =T0 21 + koff 2koffm ILn.(48) c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 423 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER In this paper, the value of maximum DC-link voltage and line current are Vdcm = 650 V and ILm = 240 A. Then, by designing resonant tank in this load level, we can write Iln = 1,Vdcn = 1,Z0n=Z0 2.7. On the other hand, from Eq. (46) the maximum value of Z0n is 0.833. Suppose Z0n= 0.6, thus, other parameters can be found as following: Z0= 2.7·Z0n= 1.62 Ω ⇒ koff = 1.52 ⇒T0= 2.95 µs⇒Lx= 0.76 µH⇒Cx= 0.29 µF, PWSx = 2.2µs. 3.2. IZCT Technique for DC-DC Buck Converter The scheme of IZCT for a DC-DC buck converter is shown in Fig. 11. This method includes an active snubber cell that is specifically suitable for IGBT-based PWM converters at high power and high frequency levels [10]. Fig. 11: DC-DC buck converter with IZCT technique. The converter with active snubber cell can successfully operate under different load levels. To design a suitable resonant tank (Lrand Cr), the following steps for maximum load current are considered. First, resonant inductor and capacitor are chosen to let the resonant current peak (IRM ) be twice the maximum load current; therefore, Eq. (49) should be satisfied. IRM =VgrCr Lr = 2IOmax.(49) In the second step, Lrand Crare selected such that the one half resonant cycle tRto be equal to twice the fall time of the main IGBT. Thus, Eq. (50) is met. tR 2=π√LrCr= 2tf,S1.(50) After designing resonant tank of active snubber cell, auxiliary switch is gated by a signal with the width equal to inverse of main switch pulse. But, according to Fig. 12, it should be delayed by TD. Mathematical analysis of the converter circuit demonstrated in Fig. 11, shows that the value of TD is about a quarter resonant cycle. TD=tR 4=π 2√LrCr.(51) Fig. 12: Gating method in IZCT technique for DC-DC buck converter. As in this paper the maximum value of output power is 100 kW, consequently the value of IOmax is equal to 250 A. Therefore, using Eq. (49) we can write VgrCr Lr = 2IOmax ⇒rCr Lr =2·250 650 = 0.77 ⇒ Cr= 0.6·Lr. Also, the second equation to find suitable values for passive components in active snubber cell using Eq. (50) is: √LrCr=2tf,S1 π⇒LrCr= 2·400 ns π2 = 6.48 ·10−14. Therefore, the value of resonant tank inductor and capacitor and the time delay required for control of auxiliary switch are: Lr= 330 nH, Cr= 200 nF, TD= 0.4µs. 4. EMI Filters for DC-DC Buck Converters It is always essential to provide EMI filters at the input and output of switching converters. Input EMI filters not only attenuate the switching noises but also protect converter and its load from input voltage disturbances [8]. Also, output EMI filters are provided to attenuate high-frequency DC voltage ripples at load side. 4.1. Input EMI Filter Design By attenuating high-frequency input currents, input EMI filter in a DC-DC converter can limit the variation of input impedance; consequently, it can provide us with the opportunity to connect a DC-DC buck converter at load side of an AC-DC converter. Due to the wide variation of DC-DC converters’ input impedance, without input EMI filters an instability in the control system can occur by the connection of DC-DC converters in series with AC-DC one. Although by adding EMI filters the former problem can be solved, a new problem appears; the input filters change the dynamic of the converters and it leads to instability of the control system again [8]. Considering Fig. 13 when input filter is added, the new transfer function of converter (Gvd(s)) is calculated by Eq. (52) and Eq. (53). Gvd(s) = (Gvd(s)|z0(s) = 0) ·correction factor,(52) c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 424 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER correction factor =1 + ZO(s) ZN()s 1 + ZO(s) ZD(s).(53) The term Gvd(s)|zO(s)=0is the original controlFig. 13: Adding an input EMI filter to a converter. to-output transfer function, ZO(s)is the output impedance of the filter, ZN(s)is the converter input impedance Zi(s)under normal operation of feedback controller which means ~vO(s)=0, and ZD(s)is equal to Zi(s)when ~ d(s)=0. Therefore, input EMI filter is designed in a way that the value of correction factor to be approximately unity. To reach this aim, two following inequalities should be satisfied. kZO(s)kkZd(s)k,kZO(s)kkZN(s)k.(54) The topology of the used filter in this paper is presented in Fig. 14. The standard values of Rfand Cb are 1 Ωand 4700 µF. These values completely satisfy above constraints. Fig. 14: The topology of input EMI filter. For proposed topology, the inequalities Eq. (54) can be rewritten as general form of Eq. (55). On the other hand, since ZOhas the highest value in its corner frequency and Zihas the least value in the corner frequency of ZD, the constraint Eq. (55) may be insufficient; therefore, to have the correction factors close to unity, constraint Eq. (56) should be also met. sLf Cf kZikmin.(55) 1 pLfCf≤ω0 4.(56) The bode diagram of input impedances of designed DC-DC buck converter is drawn in Fig. 15. The minimum value for Ziis 2.8 Ωor 8.91 dB at ω0=5320 rad·s−1. Therefore using inequality Eq. (55), we can write Lf<7.84·Cf. In addition, from inequality Eq. (56) following expression can be concluded. LfCf≥14300 ·10−12. Therefore, to design input EMI filter different values can be considered to satisfy above constraints. In this paper, Cf=470 µFand Lf=330 µH are selected. Fig. 15: Bode diagram of Ziand different input EMI filters. 4.2. Output EMI Filter Design In order to reduce high-frequency voltage ripples in output side, the use of one-stage low-pass LC filters of Fig. 16 is recommended [13]. The corner frequency of this filter should be significantly lower than the converter switching frequency. Usually, the Eq. (57) is regarded in the design of output EMI filters. fc= (1 % −10 %) ·fs=1 2πpLf0Cf0 .(57) In this paper, the corner frequency of filter is arbitrarily set 3 % of the switching frequency. Thus, as a typical solution, the value of capacitor Cfo is equal to 56 µFfor an available inductor 50 µH. Fig. 16: The connection of a low-pass filter to a DC-DC converter. c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 425