A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation

ORIGINAL RESEARCH published: 20 February 2018 doi: 10.3389/fnins.2018.00063 Frontiers in Neuroscience | www.frontiersin.org 1February 2018 | Volume 12 | Article 63 Edited by: Gert Cauwenberghs, Jacobs School of Engineering, UC San Diego, United States Reviewed by: Hesham Mostafa, University of California, San Diego, United States Georgios Detorakis, University of California, Irvine, United States Chetan Singh Thakur, Indian Institute of Science, India Rodrigo Alvarez-Icaza, IBM, Stanford University, Stanford, United States *Correspondence: Bernabé Linares-Barranco [email protected] Specialty section: This article was submitted to Neuromorphic Engineering, a section of the journal Frontiers in Neuroscience Received: 30 October 2017 Accepted: 26 January 2018 Published: 20 February 2018 Citation: Camuñas-Mesa LA, Domínguez-Cordero YL, Linares-Barranco A, Serrano-Gotarredona T and Linares-Barranco B (2018) A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation. Front. Neurosci. 12:63. doi: 10.3389/fnins.2018.00063 A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation Luis A. Camuñas-Mesa1, Yaisel L. Domínguez-Cordero1, Alejandro Linares-Barranco2, Teresa Serrano-Gotarredona1and Bernabé Linares-Barranco1* 1Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC y Universidad de Sevilla, Sevilla, Spain, 2Department of Computer Architectures, University of Sevilla, Sevilla, Spain Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, following a specific organization of the connectivity pattern between layers of neurons known as receptive field. These networks have been traditionally implemented in software, but they are becoming more computationally expensive as they scale up, having limitations for real-time processing of high-speed stimuli. On the other hand, hardware implementations show difficulties to be used for different applications, due to their reduced flexibility. In this paper, we propose a fully configurable event-driven convolutional node with rate saturation mechanism that can be used to implement arbitrary ConvNets on FPGAs. This node includes a convolutional processing unit and a routing element which allows to build large 2D arrays where any multilayer structure can be implemented. The rate saturation mechanism emulates the refractory behavior in biological neurons, guaranteeing a minimum separation in time between consecutive events. A 4-layer ConvNet with 22 convolutional nodes trained for poker card symbol recognition has been implemented in a Spartan6 FPGA. This network has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1 s time. Different slow-down factors were applied to characterize the behavior of the system for high speed processing. For slow stimulus play-back, a 96%recognition rate is obtained with a power consumption of 0.85 mW. At maximum play-back speed, a traffic control mechanism downsamples the input stimulus, obtaining a recognition rate above 63%when less than 20%of the input events are processed, demonstrating the robustness of the network. Keywords: convolutional neural networks, neuromorphic vision, Address Event Representation (AER), event-driven processing, neural network hardware, Reconfigurable Networks 1. INTRODUCTION The concept of neuromorphic engineering was first proposed by Carver Mead back in the 1980s based on the analogy between the behavior of transistors biased in sub-threshold region and the physics in biological neurons (Mead, 1989). This approach opened a new processing paradigm which takes inspiration from the structure and operation of the human brain Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node (Sterling and Laughlin, 2015): information encoded in spikes (also called events) which are processed in parallel by massive layers of neurons interconnected via synapses. In recent years, the development of bio-inspired event-driven neuromorphic Dynamic Vision Sensors (DVS) (Lichtsteiner et al., 2008; Posch, 2011; Serrano-Gotarredona and LinaresBarranco, 2013) provides a new and revolutionary way of capturing visual scenes by the generation of flows of events accurately representing the motion of real objects. In a DVS, each pixel operates autonomously and sends an output event (spike) whenever it senses a change of light greater than a preset threshold. This way, a continuous flow of events with a high temporal resolution (sub-microsecond) is obtained, representing moving reality as it changes, without waiting to assemble or scan artificial time-constrained frames. These flows of events can be processed by Spiking Neural Networks (SNNs), performing complex tasks like object tracking (Delbrück and Lang, 2013) or shape recognition (Zhao et al., 2015). A particular type of SNNs are the event-driven Convolutional Neural Networks (ConvNets), where the interconnections between layers of neurons do not follow an all-to-all pattern. In a ConvNet, each neuron from layer iis connected only to a subset of neurons in layer i+1, known as projective field. These projective fields can be represented by a 2D convolutional kernel, and imply an important reduction in the amount of synapse memory in a network, which facilitates its hardware implementation. These Convolutional Neural Networks were originally developed for frame-driven processing (LeCun et al., 1989), training them with static images, although some methods have been proposed to transform a frame-driven ConvNet into an event-driven one implemented in software (Pérez-Carrasco et al., 2013; Diehl et al., 2015), and other methods directly train the event-driven networks with spikes(Orchard et al., 2015). In the present work, we propose a hardware implementation of event-driven ConvNets that can process visual information from a DVS in real time, avoiding time-consuming software approaches. The current evolution of hardware neuromorphic platforms tends to large-scale modular computing systems with increasing numbers of neurons and synapses (Indiveri et al., 2011; Liu et al., 2015; Furber, 2016). Some successful approaches are the IBM TrueNorth (Merolla et al., 2014), the Stanford Neurogrid (Benjamin et al., 2014), the Heidelberg BrainScaleS (Schemmel et al., 2010) and the Manchester SpiNNaker (Furber et al., 2014). These projects used different techniques to design hierarchically scalable networks with multiple chips per board, and multiple boards per rack, assembling systems with between 1 and 460 millions of neurons and between 1 and 460 billions of synapses, obtaining power consumptions between 100 mW and 50kW (Furber, 2016). In a previous work, we developed an event-driven convolutional unit with 64 ×64 neurons in VLSI which could be used to build larger arrays and implement arbitrary ConvNets (Camuñas-Mesa et al., 2012). However, this approach presented two important limitations: the excessive physical size of a complex network, and the lack of a saturation mechanism in the I&F neurons, which is necessary for a multi-layer ConvNet.1Zamarreño-Ramos et al. (2013) proposed a scalable approach based on reconfigurable networks implemented on FPGA to overcome the first limitation, presenting up to 262 k neurons and 32 millions of synapses, including routing capabilities in the convolutional nodes. (PérezCarrasco et al., 2013) proposed an exact method to map the saturation from a conventional frame-based description to an event-driven system, and tested it in software. Recently, rectifying non-saturating non-linearities like ReLUs (Rectified Linear Units) have been proposed as an alternative to rate saturation mechanism in frame-based systems (Cao et al., 2015; Diehl et al., 2015). However, ReLUs are not a good solution for spiking hardware implementations, because if a neuron in a layer becomes excessively active it will generate a large amount of spikes and can collapse the communication network. In this work, we designed a configurable convolutional unit for FPGAs that can be used to build large-scale ConvNets, including a programmable rate saturation mechanism that reproduces the refractory period of biological neurons, allowing to transform conventional frame-based networks into equivalent event-driven implementations. This unit has been tested and characterized for rate saturation period values between 50 µs and 51.2 ms. This unit has been designed to assemble large 2D arrays (Zamarreño-Ramos et al., 2013), and a whole ConvNet with 22 convolutional blocks trained for poker card symbol recognition has been implemented in one Spartan6 FPGA. This network included 5 k neurons and 500 k synapses within a single FPGA. More complex hierarchical structures using larger FPGAs, and assembling multiple FPGAs in a PCB and multiple PCBs in a rack, can potentially be used to implement very large-scale Convolutional Neural Networks. While other neuromorphic approaches are based on expensive dedicated hardware, the proposed architecture allows for implementing arbitrary ConvNets on cheap commercial FPGAs. The implemented network was tested with a stimulus where 40 poker cards are observed by a DVS in 1 s time window. Different slow-down factors were applied, from real time processing to 100 times slower, obtaining recognition rates as high as 96% with a power consumption of 0.85 mW. The paper is organized as follows. Section 2.1 describes the convolutional node in detail, with special emphasis on the rate saturation mechanism, while Section 2.2 details the complete ConvNet implemented for poker card symbol recognition. Section 3 presents the experimental results obtained for characterization of both the individual module and the ConvNet, and, finally, these results are discussed in Section 4. 2. MATERIAL AND METHODS This Section describes the proposed configurable convolutional node in Section 2.1 (including details of its main operations 1Note that, if there is no non-linear saturation mechanism in a multi-layer ConvNet, so that all convolutional operations are linear, one could collapse all convolutions into a single one. Frontiers in Neuroscience | www.frontiersin.org 2February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node in sections 2.1.1, 2.1.2, 2.1.3, and 2.1.4) and the ConvNet implemented for recognition tasks in Section 2.2. 2.1. Configurable Convolutional Node A generic event-driven Convolutional Neural Network (ConvNet) follows the structure represented in Figure 1A, with multiple layers of feature maps, including several convolutional units in each layer. Each unit is formed by a bi-dimensional array of neurons, and receives events from every unit in the previous layer, applying different convolutional kernels depending on the origin of the event, implementing a multi-kernel operation. The aim of this work is to design a 2D array structure in hardware formed by convolutional units which can efficiently implement an arbitrary ConvNet, as illustrated in Figure 1B. For that, a configurable network node is designed. The block diagram of the network node is shown in Figure 2, including a convolutional unit formed by a bi-dimensional array (with configurable size) of I&F neurons, a router and a configuration block. This node has been designed to assemble large 2D arrays, where each node is directly connected to 4 other neighboring nodes through North, South, East and West ports. Each of these ports carries bidirectional flows of events (input and output). Internally, all input and output ports are connected to a router, which sends each incoming event to either the appropriate output port or the local convolutional unit, depending on both the event header and the routing table, according to the destination-driven protocol (Zamarreño-Ramos et al., 2013). An internal configuration block receives commands through a Serial Peripheral Interface (SPI) connection, and sends them to the router or to the convolutional unit. FIGURE 1 | Implementation of (A) a generic ConvNet with several layers of feature maps using (B) a 2D array structure of convolutional units. The convolutional unit designed in this work is fully configurable, so that it can be used to implement different nodes (each one with different properties) within complex multi-layer networks. Figure 3 shows the details of the convolutional unit. It computes the convolution of the input events eνin(t,x,y,p,k) with a kernel wk(x,y), generating output events eνout(t,x,y,p), where tis time, xand yare the spatial coordinates, pis the polarity of the event, and kis the kernel id, as multi-kernel processing is allowed. Input events are stored in an input FIFO, while the controller block reads events from this input FIFO, processes them using integrate and fire neurons (pixels), and writes output events in an output FIFO, which sends them out to the next module. A fullFIFO signal is generated when the output FIFO is full in order to stop receiving more input events, allowing the implementation of a flow control mechanism, which is described later. The state of the convolution (the values of all pixels or neurons) is stored in the Neuron Memory, while the Kernel Memory stores all the kernel values and their corresponding parameters: xand y-size, and center shift, as shown in Figure 5B. If the center shift is zero, the kernel will be applied to a neighborhood of pixels where the one given by the address of the input event is in the middle. A different value of this parameter shifts the position of the kernel before being applied to the pixels. Another memory is used to implement the refractory period mechanism which is described later. The convolutional unit receives configuration data through an SPI interface, which is used to write the kernels (with their parameters) and the parameters of the neuron controller (threshold, leakage, rate saturation period). The configurability of the convolutional unit includes some parameters which have to be adjusted before the hardware implementation, and some other parameters which can be modified after implementation using the SPI interface, as they are related to the training of the network. Pre-implementation parameters are the following: •Address space of input events: maximum values for xand yaccepted by the convolutional unit (xmax in ,ymax in ). These numbers will define the number of bits for xi in and yi in in the input events. •Address space of output events, which corresponds to the number of pixels in the 2D array (xmax out ,ymax out ). These numbers will define the number of bits for xi out and yi out in the output events. •Size of the neuron memory. This parameter is given by nx× ny×nbits, where (nx,ny) represent the number of pixels in the array and nbits the resolution of the register where their state is stored. •Size of the kernel memory. This memory is divided in 2 different blocks: 1) the block where the kernels weights are stored, whose size is given by the maximum number of kernels Nk, and the size of each kernel xmax k×ymax k; and 2) the block where the kernels parameters are stored, being these parameters the size of each kernel and the center shift. Only the size of this whole memory is specified. The number of kernels Nkwill define the number of bits needed for the kernel id kiin the input events. Frontiers in Neuroscience | www.frontiersin.org 3February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node FIGURE 2 | Block diagram for the node designed to build 2D arrays. FIGURE 3 | Block diagram for the convolutional unit. A controller block receives input events from an input FIFO, reads the pixels state and the convolutional kernel from the corresponding memory blocks, and sends output events to an output FIFO. An SPI block receives configuration data. A specific memory block is used to implement the rate saturation mechanism. A fullFIFO signal is generated by the output FIFO to implement the traffic control mechanism. •Size of the rate saturation memory. This parameter is given by nx×ny×nbits_TR, where (nx,ny) represent the number of pixels in the array and nbits_TRthe resolution of the register used to implement the rate saturation mechanism, as described later. •Range of the rate saturation period. This parameter (bTR) selects the range of values available for the rate period TR, establishing Tmin Rand Tmax R. The exact value within this range is specified after implementation using the SPI. The programming of the rate period range is described in section 2.1.3. Post-implementation parameters are: •Threshold of the integrate and fire pixels. Although the pixel values in theory should vary between −Th and Th, in practice we work only with positive numbers, so the negative threshold is set to 0, the positive value is set to 2 ×Th and the reset value is Th. •Leakage parameters: Tleak, which indicates the period of the leakage pulses that are applied to all the pixels, and Nleak, which indicates the amplitude of the these pulses. Frontiers in Neuroscience | www.frontiersin.org 4February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node •Rate saturation period (TR), the exact value within the available range established before implementation. •Kernel values and parameters: values which are written on the kernel memory. Figure 4 shows the typical state evolution of an integrate and fire pixel, with reset value xreset =Th and positive threshold 2×Th. The state of the pixel is updated with a positive or negative value each time a new event is processed. The decay of the pixel state represents the global leakage. The rate saturation period TR FIGURE 4 | Illustration of the evolution of a neuron while processing input spikes, showing the global leakage effect (represented by blue segments) and the rate saturation period limitation (indicated by red arrows). The state of the neuron is updated with each input spike (increased with positive spikes and decreased with negative ones). If the threshold is reached before TR, the output spike is not generated until the rate saturation time is over. imposes a limitation to the minimum time between consecutive output spikes. In this example, the second output spike was not generated when the pixel reached the threshold, but when the rate saturation mechanism allowed for it. The following sections describe in detail the behavior of the convolutional unit. Concerning the router included in the network node shown in Figure 2, it is based on the 2D structure represented in Figure 1B, where each convolutional unit is identified by its (x,y) coordinates. The router receives external events from the four neighboring nodes and, based on its programmed routing table, decides whether to send them to its local convolutional unit or to other neighbor. In particular, we used a destination-driven protocol, so the address of the destination node is written in the routing header of each event, introducing a network layer handled by the routers and transparent to the convolutional units. When the router receives an external event, it reads the addressing header and decides the output port to which the event must be forwarded. If the destination address corresponds to the node address, the event is sent to the local convolutional unit. If this is not the case, it compares the destination address with the present node address to decide the output port to which the event must be forwarded, choosing the shortest path to the destination in terms of number of hops. On the other hand, when the router receives an event from the local convolutional unit, it inserts a header indicating the destination node according to the routing table. When that node is connected to several destination nodes, the router clones the event as many times as the number of destination nodes and writes each address in the corresponding header. Further details about the router are given in (Zamarreño-Ramos et al., 2013). FIGURE 5 | Illustration of the convolutional operation. (A) Input event, where xi in and yi in are the spatial coordinates, pi in the polarity (positive or negative), and kithe kernel id. (B) Position of kerneliinside the pixel array, centered on a pixel given by coordinates (xi in +shiftx,yi in +shifty). (C) Kernel parameters, where xmax k,ymax k represent the kernel size and shiftx,shiftyindicate the position where the convolutional kernel is centered relative to the input event address, as shown in (B). Frontiers in Neuroscience | www.frontiersin.org 5February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node 2.1.1. Convolutional Operation Every time a new incoming event arrives at the convolutional unit, it is stored in the input FIFO, and as soon as there is at least one event in the FIFO, the controller block performs the following steps: 1. Read the event from the input FIFO, obtaining the address (xi in,yi in), the polarity pi in, and the kernel id ki, as shown in Figure 5A. 2. Using the kernel id ki, access the kernel memory (in particular, the parameters block, in Figure 5C) to read the size and center shift of the indicated kernel. This information, together with the event address, gives the coordinates of the pixels which have to be updated with the kernel values, as shown in Figure 5B. If all these coordinates are outside the pixels array, discard the event. FIGURE 6 | Rate saturation mechanism. (A) A pixel generates an output event at t=t0, so no output events will be allowed until tlim =t0+TR−1t. The pixel state reaches the threshold at t1(<tlim), so it keeps the threshold state until t2.(B) At t=t0, the future time tlim is calculated using the value in the 32 −bit global counter. Only 8 bits of tlim are stored (t8b lim), given by bTR.(C) The pixel reaches the threshold again at t=t1. As t1<tlim, no output event should be allowed. For that, t8b 1and t8b lim are compared. 3. Knowing the coordinates of the pixels affected by the incoming event, calculate both the positions of the states of these pixels in the neuron memory, and the positions of the corresponding kernel weights in the kernel memory. This operation is performed by the Address calculation block in Figure 3. 4. One by one, read an individual pixel value (also called partial sum, in CNN terminology) and kernel weight, and calculate the addition of both of them. If the incoming event is negative (pi in = −1), invert first the kernel weight. 5. If the result of the addition is larger than the positive threshold (positive event) or smaller than the negative one (negative event), check the minimum period TRfor that specific pixel. If firing event is allowed, go to step 6. If not, update the new pixel value (or partial sum) in the corresponding position of the memory, and wait for the next input event. This missing event will be sent out the first time this pixel receives an input event after TRis over, introducing an error 1tthat will be compensated using the method described in section 2.1.3. 6. Generate an output event with address (xj out,yj out) and polarity pj out, and write it in the output FIFO, reset the corresponding pixel and update it in its memory position. 2.1.2. Global Leakage In parallel with the convolution process described before, a global leakage process runs continuously in the controller block. A global 32-bit counter is increased with every clock cycle, until it reaches the previously programmed value Tleak. This process has the highest priority, and every time it reaches Tleak it cycles through all the data stored in the Neuron Memory and decreases all neuron values by Nleak if they are positive, and increases them if they are negative, never crossing the reset value. This process makes all neurons converge toward the reset value. 2.1.3. Rate Saturation Period Mechanism The main novelty of this work is the hardware implementation of a mechanism that emulates the refractory period property of biological neurons. This property guarantees a minimum separation in time (given by TR) between two consecutive spikes generated by a single neuron. Figure 6A illustrates how the neuron state is increased every time a new input event arrives until it reaches the threshold. At t=t0, an output event is generated and the neuron state is reset, so the controller block reads the present time t0in the 32 −bit global counter (as shown in Figure 6B) and calculates the future time when it will be allowed to generate an output spike again tlim. This future time is given by tlim =t0+TR−1t, where t0 is the present time, TRthe minimum rate period or refractory time, and 1tis a small correction applied to the calculations to compensate for frequency deviations. The calculation of this 1tis described at the end of this section, so for now we will assume 1t=0. At t=t1, the neuron reaches the threshold (see Figure 6A), but it is not allowed to generate an output event, as t1<tlim. Therefore, the neuron keeps the threshold value until t2, when a new input event is received and an output event is finally generated (because t2>tlim). Although this output event should be generated ideally at tlim, we propose a computational Frontiers in Neuroscience | www.frontiersin.org 6February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node simplification where the output event is not sent out until the pixel receives another input event at t2. The error 1tintroduced by this simplification is compensated in the calculation of the next tlim. A flag f1tis used to indicate whether this compensation has to be applied or not. The resolution of the global counter is 32 bits, so that is also the size of tlim. The rate saturation period memory stores information about tlim for each pixel in a register, resulting a size of nx×ny×nbits_TRfor this memory. If the whole tlim is stored for each pixel, each memory register needs 32 bits and the memory consumes a lot of resources. We propose to reduce the size of this memory by a factor of 4, storing only 8 bits per pixel (t8b lim in Figure 6B), from bTR to bTR −7. The value of bTR is a parameter that must be specified before implementation (7 ≤bTR ≤31), and it corresponds to the MSB (Most Significant Bit) of the rate saturation period TR. Therefore, the possible values of TRthat can be programmed after implementation will be given by Tmin R= 2bTR−7and Tmax R=2bTR+1−1. According to this strategy, 8 bits from tlim (t8b lim) are stored at the register of the rate saturation period memory corresponding to that specific pixel. After that, the next time this pixel reaches the threshold, the controller block reads the time t1in the 32−bit global counter, extracts 8 bits from it (t8b 1, from bTR to bTR −7, as shown in Figure 6C) and compares it with t8b lim. If t8b 1>t8b lim, it sends out the event; otherwise, it stores the threshold value in the corresponding position of the neuron memory and waits for the next incoming event. However, this mechanism can cause wrong decisions, as the bits more significant than bTR are not compared (it can happen that t8b 1<t8b lim while t1>tlim due to overflow, so an output event would be missed). In order to avoid this kind of errors, a flag fof indicating overflow is used together with a refresh mechanism. The use of this flag is described in Figure 7. Every time the threshold is reached after updating the state of a pixel with a new input event, the present value of the global counter (tin Figure 7) is used to find out if it is allowed to send out an event or not. For that, 8 bits from this counter (t8b) are compared with the stored value of t8b lim. If t8b<t8b lim, the pixel is still under the TRlimitation, so its state is set to the corresponding threshold value and the flag f1tis set to 1, meaning that a 1tcorrection will be necessary. On the other hand, if t8b>t8b lim, the controller block cannot be sure that TRtime is really over until it checks the overflow flag fof . If fof =1, the pixel is still limited by TR, so the threshold value is stored in the pixel’s state and f1tis also set to 1. If fof =0, the overflow flag is not active, so the event is sent out while the pixel’s state is reset. After that, the value of the next tlim is calculated, taking into account the value of 1tas the difference between the current time and the previous tlim (as illustrated in Figure 6A) when the flag f1t=1, and resetting this flag. After the calculation of the new tlim, the 8 bits t8b lim are stored in the rate saturation mechanism memory, and if overflow is detected during the calculation (t8b lim <t8b), the corresponding flag fof is set to 1. A global refresh mechanism is used to ensure the correct behavior of the overflow flag fof , as described in Figure 8. A refresh pulse is generated every time the global counter treaches the value trefresh =2bTR+1−1 (all bits from bTR to b0set to 1). When this happens, the controller block reads all fof flags FIGURE 7 | Flow diagram describing the rate saturation period mechanism. (one per pixel), and if fof =1, it is set to 0, indicating that overflow is not a problem anymore, while if fof =0, it resets t8b lim =0, indicating that TRtime is already over for that pixel. Finally, the 1tcorrection applied to the calculation of tlim is also illustrated in Figure 6A. When the first output event is generated at t0, we assume 1t=0. However, the second output event occurs at t2, although it should have been generated at tlim. Therefore, the event generated at t2had been delayed by the rate saturation mechanism, as indicated by the flag f1t=1 described before. In this case, the next tlim is not measured from t2, but from the last tlim. In this particular example, after sending out the event at t2, the next tlim would be calculated as tlim =t2+TR−1t2. This correction is important to make sure that a neuron with rate saturation period TRreceiving an input train of events with frequency fin higher than 1/TRwill generate an output train of events with average frequency given by fout =1/TR. Without this correction, fout would be smaller, as it would depend of the exact arrival time of the input events. This 1tdoes not introduce any error in the high temporal resolution of the events generated by a DVS, it actually introduces a correction in the effective value Frontiers in Neuroscience | www.frontiersin.org 7February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node of the maximum event frequency given by the rate saturation period TR. 2.1.4. Traffic Control Mechanism As shown in Figure 3, the convolutional unit activates a fullFIFO signal when the output FIFO is full, and this signal is used to implement a traffic control mechanism at the network level. Considering that the network receives a flow of events from a DVS using AER protocol, we implemented a mechanism which drops input events whenever a node in the network has the FIGURE 8 | Flow diagram describing the refresh mechanism associated to the rate saturation period. fullFIFO signal active. Instead of holding the acknowledge and introducing artificial delays in the events flow, this mechanism reduces dynamically the amount of input events while keeping the spatio-temporal correlation between them. When the input event rate is too high, the network subsamples the input event flow, reducing the event rate as certain events are dropped. However, the precise timing of the events which are actually processed by the network is not altered. It is evident that the information carried by the dropped events is lost, but the information carried by the processed events is not modified by the network traffic, so the spatio-temporal correlation between them is kept. The implemented traffic control mechanism introduces some uncertainty in the network behavior, as event dropping depends on each individual propagation delay inside the network, which is not completely deterministic. This effect can cause slightly different results when processing the same stimulus twice. We compensate this by analyzing statistically the behavior of the network after repeating each experiment up to 100 times, as shown in Figure 14. 2.2. Convolutional Neural Network for Recognition Tasks As described in Section 2.1, the convolutional node has been designed to assemble large 2D arrays in order to implement event-driven Convolutional Neural Networks (ConvNets). As an example, we implemented on FPGA the ConvNet described by (Pérez-Carrasco et al., 2013) for high-speed poker symbol recognition. The network is represented in Figure 9, and it consists of 4 convolutional layers (named C1, C3, C5 and C6 FIGURE 9 | Schematic block diagram of the Convolutional Neural Network used for poker card symbol recognition. Yellow, red, green and purple boxes represent convolutional layers, while pink boxes correspond to subsampling layers. Layer C1 extracts oriented edges, which are downsampled by S2. Those different edges are combined by C3 and downsampled again by S4. Layer C5 obtains specific features that are combined by C6 to decide which of the four poker symbols is being observed. Frontiers in Neuroscience | www.frontiersin.org 8February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node in the figure) and 2 subsampling layers (named S2 and S4). This figure shows that 22 convolutional modules are used to implement the whole network: 6 modules with 28 ×28 pixels in layer C1, 4 modules with 10 ×10 pixels in layer C3, 8 modules with 1 ×1 pixel in layer C5 and 4 modules with 1×1 pixel in layer C6. Subsampling layers S2 and S4 reduce the address space by a factor 2, from 28 ×28 to 14 ×14 and from 10 ×10 to 5 ×5, respectively. This is done by summing the events in each subsampling window of 2 ×2 pixels into a single pixel. A schematic block diagram of the hardware implementation on FPGA is represented in Figure 10, where all the modules are placed in an array of 6 ×4. The input splitter sends the incoming events to all 6 blocks in column 1 (i, 1)i=1,...,6, while the output merger receives all events from modules in column 4 (i, 4)i=1,...,6 and sends them out. The internal routers in each module are programmed to reproduce the connectivity of the network in Figure 9. Therefore, the yellow modules in Figure 10 correspond to layer C1, the red modules correspond to layer C3, the green blocks correspond to layer C5, and the purple ones to layer C6. The two blue FIGURE 10 | Schematic block diagram of the FPGA implementation of the Convolutional Neural Network used for poker card symbol recognition. Yellow modules represent layer C1, red modules correspond to layer C3, green modules correspond to layer C5 and purple ones to layer C6. Blue modules only include routing capabilities. modules only include the router for communication purpose, as no more convolutional modules are needed. Subsampling layers S2 and S4 are implemented by shifting the bits in the parallel buses between C1-C3 and between C3-C5, ignoring the Least Significant Bit in both xand y-coordinates. Therefore, all events in each 2 ×2 subsampling window are summed into a single pixel. The aim of this work is the implementation of a given ConvNet in a commercial FPGA, so we consider that the network has already been trained. In the particular example of ConvNet we use to illustrate our architecture, the network was implemented and trained in software by Pérez-Carrasco et al. (2013) in the frame domain using backpropagation, mapping the obtained parameters to the equivalent event-driven representation. Taking these parameters as a starting point, we have mapped them to our specific implementation. The mapping of the network parameters from the values given by Pérez-Carrasco et al. (2013) (see row 1 in Table 1) can be described as a two-stage procedure. First, the amplitude parameters (kernel weights and convolution thresholds) and the time parameters (rate saturation periods and leakage rates) had to be adapted (scaled and rounded) to the hardware implementation, and second, they had to be tuned to compensate for the nonidealities of the hardware by using an optimization algorithm. The original amplitude values were represented in software using double-precision floating point numbers, while the proposed hardware implementation uses 9-bit integers for the neuron states (from 0 to 511). However, we compute negative values by shifting reset state to Th, and using 0 and 2 ×Th as negative and positive thresholds, respectively. Although in principle it would be possible to use a maximum value of Th =256, in practice it could cause overflow errors resulting in numbers larger than 511. We avoid this problem by setting a maximum value of Th =128. Therefore, the first stage scales up all thresholds to 128, while keeping the corresponding kernel weights proportional for each layer. This change does not affect the rate saturation period values, but it does affect the leakage rate values as they are defined in Table 1.LRiis defined as the ratio between the threshold value and the time it would take to decrease it until the reset value for layer i. Therefore, it also has to be scaled up with the threshold. The obtained parameters are shown in row 2 of Table 1. This first stage of the mapping is done automatically by a routine which reads all the indicated network parameters, and scales and rounds their values. However, the direct adaptation of these parameters does not produce the same behavior in the network, as the hardware implementation has some nonidealities that were not present TABLE 1 | Network Parameters. Version TR3 (ms) TR5 (ms) th1th3th5th5LR1 (s−1) LR3 (s−1) LR5 (s−1) LR6 (s−1) Pérez-Carrasco et al. (2013) 0.10 0.46 0.64 1.42 7.36 2.17 0.72 0.90 1.21 0.72 FPGA scaled 0.10 0.46 128 128 128 128 143.62 81.16 21.00 42.41 FPGA optimized 0.08 0.43 66 114 93 126 3,959.93 3,576.70 906.61 214.88 Frontiers in Neuroscience | www.frontiersin.org 9February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node processing. Figure 19D shows the activity generated by all the convolutional nodes in layer C5, which corresponds to 62 events during the 10 ms time window, and a total of 137 for the whole sequence. Finally, Figure 19E shows the activity generated by the 4 output neurons in layer C6, with only 7 events in the presented cut, and a total number of 15 events for the complete symbol processing. The figure shows how the neuron associated to the club symbol generates two positive events and a negative one, while the other neurons generate only negative events, so the symbol was recognized correctly. The latency between the onset of the stimulus and the first positive event is less than 6 ms at real time, which represents a very fast recognition task. Although the proportion of events processed by the network is less than 20% at real time, this example illustrates how a successful recognition is obtained by exploiting the robustness of the network. The power consumed by the whole network inside the FPGA was measured while processing the input sequence for different slow-down factors, obtaining 7.7 mW when the stimulus was being processed at real time, and even lower consumptions for slower processing: 5.25 mW when it was 10 times slower, and 0.85 mW for a slow-down factor of 100. Considering that each symbol was presented for an average time of 25 ms in the realtime situation, the energy per classification can be obtained as 192.5 µJ, or inversely a number of 5, 194.81 classifications per Joule. The same calculations can be done for slow-down factor of 10 with Tsymbol =250 ms, and for a slow-down factor of 100 with Tsymbol =2.5 s. Table 7 summarizes the main results given in this section for different slow-down factors. 4. DISCUSSION In recent years, the field of machine learning has experienced a huge progress taking advantage of the availability of immense image databases and the current computing power. Different tasks have attracted the attention of researches, like classifying handwritten digits from the MNIST dataset (LeCun and Cortes, 1998) or classifying an object into one of 1000 classes, as is required for the ImageNet dataset (Russakovsky et al., 2015). For instance, modern ConvNets like LeNet-5 (LeCun et al., 1998), AlexNet (Krizhevsky et al., 2012), GoogLeNet (Szegedy et al., 2015), VGG-16 (Simonyan and Zisserman, 2014) or ResNet (He et al., 2016) have been developed to solve such tasks with impressive results. However, the main bottlenecks in these TABLE 7 | Summarized main results. Measurement Real-time Slow-down factor 10 Slow-down factor 100 Recognition rate 63% 95% 96% Ratio of processed events 17% 70% 100% Power consumption 7.7 mW 5.25 mW 0.85 mW Tsymbol 25 ms 250 ms 2.5 s Energy per classification 192.5 µJ 1.312 mJ 2.125 mJ Classifications per Joule 5,194.81 761.90 470.58 applications are related to speed and power. The human brain represents a source of inspiration to design better approaches, given its ability to perform classification tasks in real time with a very small power consumption, so that is the goal of neuromorphic systems like the one presented in this work. While conventional frame-based ConvNets process huge amounts of data, neuromorphic systems process visual information encoded in events as generated by DVS sensors inspired by the biological retina, resulting in very sparse data which facilitates the reduction in processing time and power consumption. The pseudosimultaneity property of neuromorphic systems allows individual events generated by the sensor to propagate through all the layers in the network immediately, while frame-based systems need to wait until large packages of information (frames) are processed by each layer, introducing multiple delays. Despite these clear advantages in neuromorphic systems, conventional frame-based ConvNets are still giving better performance, mostly due to the availability of image datasets mentioned before and very well-known training techniques based on frames, like backpropagation. Nevertheless, recent works have demonstrated similar performance in neuromorphic SNNs using event-based training techniques (Wu et al., 2017; Zheng and Mazumder, 2017), suggesting that it is only a matter of time that eventbased ConvNets become competitive with respect to frame-based ones in terms of classification, while presenting better results in terms of speed and power consumption. Some frame-based approaches are using hardware accelerators (Aydonat et al., 2017; Qiao et al., 2017) to improve their performance in terms of speed. Some large-scale neuromorphic approaches (Schemmel et al., 2010; Benjamin et al., 2014; Furber et al., 2014; Merolla et al., 2014) have dealt with the speed/power tradeoff, showing very impressive results (Furber, 2016), although they are based on very expensive dedicated hardware. The architecture proposed in this paper allows for implementing large-scale ConvNets using cheap commercial FPGAs presenting competitive results in terms of the tradeoff recognition rate/speed/power. A new configurable event-based convolutional node with rate saturation mechanism has been designed for hardware implementation of convolutional neural networks on FPGAs. This node was designed to assemble large 2D arrays, and includes three main blocks: (1) a processor unit, which calculates the convolutional operation of the input events with a programmable kernel and generates the corresponding output events, (2) a router, which manages the communication between the processor circuit and the neighboring modules, implementing the network structure, and (3) a configuration block, which receives commands through an SPI connection in order to set all the programmable parameters of the network. The proposed implementation of the rate saturation mechanism guarantees a programmable minimum separation in time between consecutive spikes for each single neuron, while the implemented traffic control mechanism discards input events when the network is busy, keeping spatio-temporal correlation and avoiding artificial delays. Although rectifying non-saturating non-linearities like ReLUs have been proposed as a simpler alternative to rate saturation mechanism in framebased systems, they are not a good solution for spiking hardware Frontiers in Neuroscience | www.frontiersin.org 16 February 2018 | Volume 12 | Article 63 Camuñas-Mesa et al. A Configurable Event-Driven Convolutional Node implementation, as an excessively active neuron would generate a large amount of events and collapse the communication network. A Convolutional Neural Network with 4 layers and 22 nodes for poker card symbol recognition has been implemented on a Spartan6 FPGA using a 2D array of the proposed convolutional node. The individual node has been characterized for different rate saturation period values from 50 µs to 51.2 ms, showing a correct behavior. The proposed network, with more than 5 K neurons and 500 K synapses, has been carefully characterized for the recognition of a sequence of 40 poker card symbols in 1 s time with different slow-down factors, from real time processing to 100 times slower. The slower versions showed recognition rates around 96% when all the input events were processed by the network, while less than 20% of the events were processed at real time, obtaining a recognition rate higher than 63%, demonstrating the robustness of the method even when the input stimulus is barely visible by a human observer due to the high speed. A recognition latency smaller than 6 ms was shown in the presented results. Arbitrary convolutional neural networks can be easily implemented using the proposed node and methodology, which can be expanded to multi-FPGA arrays by using appropriate I/O blocks reported elsewhere (Yousefzadeh et al., 2017). In the example presented in this paper, a relatively small FPGA was used with a slow clock signal (50 MHz). However, some newer FPGAs include more than 5 millions logic elements, and support maximum processing frequencies up to 1.5 GHz. This would imply around 36 times more slices and a clock signal 30 times faster. This number of slices would be able to fit up to 180 K neurons and 18 M synapses within a single FPGA. AUTHOR CONTRIBUTIONS AL-B, TS-G, and BL-B conceived the idea and supervised the project. YD-C and LC-M developed the hardware implementation, and designed and conducted the experiments. LC-M wrote the paper with inputs from all the authors. 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This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms. Frontiers in Neuroscience | www.frontiersin.org 18 February 2018 | Volume 12 | Article 63