A low-voltage /spl radic/x floating-gate MOS integrator

ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland A LOW-VOLTAGE & FLOATING-GATE MOS INTEGRATOR Esther 0. Rodriguez', Albert0 Ylifera' ,2 and Adoraci6n Rueda' 'Instituto de Microelectrdnica de Sevilla (IMSE). Centro Nacional de Microelectr6nica (CNM), Edificio CICA. Avda. Reina Mercedes s/n. 41012-Sevilla. SPAIN Dto. de Tecnologia Electrbnica., Facultad de Informitica y Estadistica, Universidad de Sevilla. Campus de ReinaMercedes. 41012-Sevilla. SPAIN. e-mails: esther, yufera, rueda@ imse.cnm.es Abstract In this paper, the design and simulation results of a 1V integrator using Floating Gate MOS (FGMOS) transistor techniques is presented. Combining FGMOS working in strong and in weak inversion a current-mode companding integrator is proposed, that implemented in a standard CMOS process is able to work with very low supply voltage. It has application in audio signal processing. Simulation results show a very low power consumption (1.3pW), low frequencies below 5Hz feasible, and a dynamic range of 55dB for a maximum THD=l.2%. The gain of the integrator is adjustable in more than 2 decades. 1. Introduction A recent interest exists in novel realizations of low-voltage filters based on the global linearization mechanism called instantaneous companding [ 11. Several practical implementations have been reported with either BJT or MOS based integrators, leading to the known log-domain or squareroot domain filters [2-81, with benefits in term of improved dynamic range. In [9], general block diagrams for compressing-expressing integrator realizations were proposed based on two nonlinear blocks G and Z. The G-block is a nonlinear transconductance V-I element with a non-linearity that can be either compression or expansion, and the Z-block is a nonlinear transcapacitance I-V block. In this paper, we present a new $x -domain integrator which belongs to the class A given in [9]. Its conceptual block diagram is shown in Fig.1, and the nonlinear functions for N and G are of the ,& and (A)-' type, respectively. The implementation we propose for these functions relies on the use of Floating-Gate-MOS (FGMOS) devices and the translinear principle with MOS's working in weak inversion region [10,11]. The resulting integrator is easily tunable by changing either a voltage or a current. However, it is limited to low current levels in order to preserve weak inversion operation of some transistors. In Section 2 the proposed circuits are presented and analyzed; and in Section 3 electrical simulations are shown proving their feasibility. il. ..... . .. ... " . . . ........ . ...... ... ... . . , I- -I/ T 1 G-block Z-block Figure 1: Block diagram for the proposed integrator 2. The FGMOS-based ,h Integrator 2.1. The G-Block The proposed G element is implemented as a two-input FGMOS transistor working in strong inversion and saturation region. The circuit is shown in Fig. 2. The output current, lour, is given by, where p is the transconductance parameter, V, is the transistor nominal threshold voltage, and CO and CI are the input capacitances associated to the floating-gate transistor inputs which are connected to V, and VDD respectively. CT is the total capacitance seen from the floating-gate node including CO, C, and MOS capacitances. This circuit performs a 2expander operation for the Vc voltage giving a current as output. The use of FGMOS makes possible the reduction of the threshold voltage seen from the input terminal Vc, allowing low values of the supply voltage V~D. However, there is a low limit for VDD which is imposed by the strong inversion mode conditions. For example, for the case of CO =C, =C#, VDD must be greater than the nominal value of V,. Hence, technologies with lower threshold voltages will allow further reductions on minimum power supply. Also, an upper limit 0-7803-5482-6/99/$10.00 '2000 IEEE I184 exists in order to maintain positive the effective threshold voltage; for the above example, this limit will be 2Vp Figure 2: G-block plus integrating capacitor C 2.2 The N-Block The VC voltage in eq. (1) is proportional to the square-root of the drain-current. In order to compensate this quadratic dependence, the N-block must generate a capacitor current, IC, of the form, 'in IC-K - zKt being K, a undefined constant. Hence, the differential equation from Fig. 2 becomes, or in integral form, (4) where capacitor values and p are related with transistor MC in the G-block, while K, is a constant depending on the N-block function implementation. Equation (4) represents a linear input-output integration relationship that uses V, as the nonlinear intermediate variable. For the implementation of equation (2) we propose the circuit in Fig. 3, which relies on the use of translinear loops realized with FGMOS's working in weak inversion saturation region. It consists of four FGMOS transistors: MO, MI and M2 as inputs, and M3 as output. The input capacitors associated to each floating-gate are in the following denominated as Cji for thej-th transistor (j=O,1,2,3) and its i-th input (i=O,I or 2). The input linl enters transistor MO biased with a lDc current which defines the circuit input signal range. A current for tuning purpose, Z,, at MI transistor, and a feedback transistor, M2, whose input, Iour, comes from the integrator output are also included. The current Ioull is the output of this block which will be delivered to C (it plays the role of IC in Fig.2). As we will see in the following explanation, the three-input transistor M3 works as a a multiplier for the direct and feedback signals. Two of its input gates are used as input for the multiplier, while the third gate voltage (vb3) controls its effective threshold voltage. VDD Figure 3: 2-block FGMOS-based implementation. For a Q-input FGMOS transistor in weak inversion with VsB=O and in saturation region, the drain current can be expressed by: where w = C /CT represents the input weight of the FGMOS transisIbr at the q-th gate, CT is the sum of all the capacitor connected to the floating gate, and Cq is the capacitor value associated to the q-th input. The subthreshold slope n is a constant between I and 2, and UT is the thermal voltage. Analyzing the circuit in Fig. 3, the voltages at the floating gates results as, (7 (6) VA = -.log - -- v. nUT 10 (:j :;; lout (7) where the first subscript of the weights is associated with the transistor and the second with the corresponding floating gate input. Combining eqs. (7) and (8) it results, 1-185 VA = nuT - ' log( Z) - wlo (9) The input gate voltages (Vinl, Viour and VA) are then expressed as functions of extemal signals: voltage (vbl, Vb2, vb3) and currents (IDc, IA, linl). The drain current of M3 is now given by, and using (6), (7) and (9), it results where K1 has an exponential dependency of the voltages vbj (j=1,2,3), and, "A = w30/wl 0 (12) a0 = (w~~w3o)/(w~ow2o) (13) "DC = w31/w00 (14) The result obtained in eq. (11) is a product of currents including the input current (Iinl), the feedback current (Zout) and the tuning current (IA), each one with an a coefficient. The negative coefficient, -ao, is obtained by cascading A42 and MI. For CTo= CTl= Cn= CT3= 2Col= 2Cll= 2C21= 4C3o= 2C31= 4c32, the exponential coefficients are set to: ~l,=O.5, a,=-0.5 and aDc=I, respectively. Hence, and 4nUT 4nUT KI = Is3.e With the above capacitor selection, eq. root function looked for the N-block. 2.3 The integrator 15) gives the squaredBy connecting block G and Z as indicated in Fig.1, a linear integrator is obtained. The schematic for a two-input integrator is illustrated in Fig. 4, with Iinl and Iin2 representing the two input currents and lout the output. G BLOCK Figure 4: Two-input Integrator. Considering eq. (15) for the N2-block, Iour2 is given by Since Ioutl and lOut2 are added in Fig. 4 to gives IC, the final integrator function is, where now K, can be identified as, J 'sl 'so with K=KI=K2. Fromequations (18), (19) and (16) we can see that the tuning of the integrator gain can be carried out by changing IA or vbj (j=1,2,3) of the different transistors. 3. Simulation Results The circuit in Fig.4 has been designed in a 0.8pm CMOS process, with VTn= 0.9V andv =-0.95V, using a supply voltage VDD=IV. Cascode structures have been used as loads and to implement bias current sources. Aspect ratios of 1Opd lptn for transistors MO-M2, 2.5pdpm for M3 and 2.5pd 5pm for MC have been taken. The minimum capacitance at the FGMOS inputs are about I0OfF. HSPICE simulations have been carried out with BSIM transistor models. Figure 5 shows the simulated integrator frequency response for vb3 changing from 0 to IV, the maximum input current used was 40nA. Values for vbl and vb2 are fixed to VDd2, but they could also be used for tuning the integrator time constant. The gain changes more than 40 dB in this vb3 range. On other hand, Figure 6 shows the frequency response for IA changing from TP 1-186 2nA to IOOnA. Gain changes 17dB in this range. The THD measured at 5Khz versus input current peak values, for IDc=50nA, Vb3=0.5v and IA=loonA is presented in Fig.7. These measurements show that the filter has a good linearity. Dynamic range of 55dB has been measured. Main integrator features are in Table 1. The integrator shows a rather large dynamic range considering the low power dissipation and the very low supply voltage. 4. Conclusions A new 1V integrator has been presented. Translinear and companding functional signal processing concepts have been related to obtain a .,& -domain integrator implemented with FGMOS transistors. The feasibility of the proposed circuit has been proved through electrical simulations. Effects of mismatching in transistors and capacitors are being studied and are going to be prove experimentally. This work is supported in part by the Spanish project CICYT No: TIC-97-0648. 5. References [ 11 Y. Tsividis: “Externally Linear, Time-Invariant Systems and Their A lication to Compandin Signal Processors”, IEff Trans. Circuits Sys. II, 1987, 44, No [2] R.W. Adams R.W.: “Filterin in the log domain”. 63rd AES Conj, New York, May f979. [3] D. R. Frey: “Exponential state space filters: A generic current mode design strategy”, IEEE Trans. Circuits Sys. [4] D. R. Frey: “Log-domain filtering: an a roach to current-mode filtenng”. Proceedings IEE V8f. 140, Pt. G, No 6, pp. 406-416, Dec. 1993. 2, pp 65-85. I. 1996, 43, pp.34-42. [5] M. Punzenberger and C. Enz: “A Compact Low-Power BiCMOS Lo8;Domain Filter”. IEEE Int. Journal o Solid-Stated ircuits, Vol. 33 No. 7, pp. 1123-1 129, Surf 1998. [6] D. Perry and G. W. Roberts: “The Design of LogDomain Filters Based on the Operational Simulation of LC Ladders”. IEEE Trans. on Circuits and S stems, Part 11: Analo and Di ita1 Signal Processing. col. 43 No. 11, pp. 7&-774, dv. 1996. [7] M.H. Eskiyerli, A. J. Payne and C. Toumazou: “State Space Synthesis of Integrators Based on the MOSFET s uare law”. Electron. Lett. vol. 32, pp.505-506,Mar. 1396. ‘ [8] J. Mulder, A. C. van der Woerd, W. A. Serdijn and A. H. M. van Roermund: “Current mode com andin Adomain inte rator”. Electronics letters, Vof32, N’. 3 pp. 198-199. Fe%. 1996. [9] J. Mahattanakul and C. Toumazou: “Instantaneous companding and expressing: A dual approach to linear integrator s nthesis’ , Electronics Letters, January 1997 Vo1.33 NO. K, pp 4-5. [lo] T. Shibata and T. Ohmi: “A Functional MOS Transistor Featuring Gate Level Weighted Sum and Threshold 0 erations”. IEEE Trans. on Electronics Devices. Vol. 3fN”. 6 , pp. 1444-1455, Jun. 1992. [l 11 B. A. Minch: ‘‘Analysls, S nthesis, and implementation of Networks of Multi le &put Translinear Elements”, Ph.D. Thesis, Caltech, Sasadena, CA, 1997. 70.0 8 2 10.0 - - 30.0 P -“ -10.0 -30.0 1 I 100 1000 10000 -50.0‘ lo frequency IHzl Figure 5: Magnitude response for VbS from 0 to I V, and vbl=Vb2=0.5v. 1.5 7 I OOnA 20.0 1 100 000 -40.0 10 frequency IHz) Magnitude response for IA=2nA and 1OOnA. ).O Figure 7: THD versus differential-input current. Table 1: Performance parameters for the integrator. Power dissipation DR (THD = 1.2 % @ 5KHz. Vb,=O.SV) 55dB 1-187