1.2V, 1.96mW @ 2.4GHz CMOS-90nm switched-transconductor mixer

1.2V, 1.96mW @ 2.4GHz CMOS-90nm Switched-Transconductor Mixer Alberto Villegas, Diego Váquez and Adoración Rueda Instituto de Microelectrónica de Sevilla – Centro Nacional de Microelectrónica Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC) / Universidad de Sevilla C/ Américo Vespucio s/n – 41092- Sevilla - Spain {villegas, dgarcia, rueda}@imse-cnm.csic.es Abstract—This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance. I. INTRODUCTION Mixers are one of the main blocks in RF systems performing the necessary frequency translation. The Gilberttype mixer has been widely used because of its advantages in terms of gain, noise, port-to-port isolation, linearity, etc [1]. However, it has important limitations in other aspects that make them not suitable for LV-LP applications. Among other issues, the Gilbert Cell requires stacked transistors operating in the saturation region and large LO (Local Oscillator) swings. These aspects limit the required voltage supply, power consumption and output swing. Several techniques have been proposed to overcome such limitations [2]–[4]. For example, the folded structured method [2] reduces the number of stacked transistors allowing lower supply voltages. However, because this method requires more current to flow, power consumption is similar to the conventional Gilbert structure. In [3], low voltage operation using an LC tank is reported; large output swing is achieved at the cost of large are overhead. The switched transconductor mixer topology [6] has been proposed as an alternative to the Gilbert one. They have similar performance in terms of conversion gain and linearity. However, the switched transconductor mixer achieves lower noise figure at high LO frequencies and allows lower voltage operation. In this paper, a low voltage low power fully differential double balanced mixer with programmable gain is presented. It is intended for ZigBee applications in the 2.4GHz band [5]. Low-Voltage and Low Power operation are achieved by exploiting switches connected to the supply voltage and RF transistors in the weak inversion. On the other hand, the fully differential and double balanced topology guarantees good port isolation and linearity. The paper is organized as follows. Section II reviews briefly the basis of the switched transconductor mixer. Section III describes the design of the proposed mixer intended for ZigBee applications in the 2.4GHz band. Section IV shows experimental results from the extracted layout. Finally, some conclusions are given in Section V. II. SWITCHED TRANSCONDUCTOR MIXER Figure 1 shows the simplified scheme of the mixer core. Two NMOS differential pairs biased at voltage VB act as transconductors (represented with transconductances gm1 and gm2 in the figure). Two anti-phase driven CMOS inverters are used to turn on/off the corresponding transconductor accordingly to the anti-phase LO and XLO signals. Notice that the scheme is suitable for low voltage operation while large output swing can be achieved because stacked transistors are avoided. Figure 1. Double balanced switching-transconductor mixer Assuming matched transconductors and instantaneous ideal switching, gm1/gm2 is on/off or off/on. Thus, either Io1 or Io2 is equal to IB+gmVRF (where IB is the current through the on transistors and gm their equivalent transconductance at the bias point) and the other current is zero, just as in the Gilbert mixer. So, the differential conversion gain can then be expressed as, Lm Rg π 2 GC ≈ In terms of thermal noise, the contribution of the transconductance devices is roughly the same as in the Gilbert mixer topology at equal conversion transconductance. This makes sense, as either gm1 or gm2 is active, alternately producing (uncorrelated) thermal noise with a variance proportional to gm. However, there is a significant difference if we consider the noise contribution of the switch devices (inverters). In the proposed topology, the noise current generated by the switches is in common mode, because the two MOS transistors from one transconductor pair are working at the same state. Then the noise is expected to be cancelled by the differential outputs. The approximate SSB NF (Single Side Band Noise Figure) is given aprox. by [6],  s 2 m 2 L mmg 2 SSB Rgc R 1 αg)grγ(2 c α NF ++ +=  where the α and c are LO related parameters, γ, rg and gm denote the noise factor, gate resistance and transconductance respectively and Rs is the resistance of the signal source used for noise figure evaluation (usually 50). III. THE PROPOSED MIXER DESIGN In this section, the design of a mixer based on the scheme in Figure 1 and intended for ZigBee applications in the 2.4GHz band using a 90nm CMOS technology and 1.2V of voltage supply is described. An intermediate frequency fIF equal to 2.5MHz has been chosen as a good compromise between image rejection requirements and channel selection filter specifications (cut-off frequency and selectivity). In order to maximize the transferred signal from the balun to the circuit, the mixer should have 50  input single ended impedance. An RLC network has been used. In this configuration, the resistance Rg generates the real part, inductor Lg and the capacitor Cgs form a tank resonating at 2.4GHz. Figure 7 shows the S11 curve of the mixer. The input return loss is below -20 [email protected]. Figure 2 shows the schematic of the proposed mixer including input matching networks at LO and RF ports. The switching inverters are composed by transistors M1-M4 and the RF transconductance stages by M5-M8. The output load corresponds to a common mode feedback structure composed by resistors RL, transistors M9-M10 and the current source Ib, that is used to set the common mode voltage. Power consumption is directly related to the size and bias voltage of the transconductance transistors (M5-M8). From this point of view, it is desired to keep them in weak inversion. This way, large output swing can also be achieved even for low voltage supply. On the other hand, the W/L ratio of such transistors should be large in order to obtain high conversion gain. These circumstances are desirable from the power point of view, but this is not the case for thermal noise [7]. M5VB-VRF/2 V+ out V- out Io1 Io2 LO Rg Lg Cgs M6 M7 M8 VSS Vdd M1 M2 VSS Vdd M3 M4 RLO LLO CLO Vdd M9 Ib Vdd M10 Gain Controlled RLRL XLO RLO LLO CLO Input Matching Network Input Matching Network VB+VRF/2 Rg Lg Cgs Input Matching Network Input Matching Network Figure 2. Double balanced switched implemented transconductor mixer Thus, the W/L of M5-M8 transistors must be chosen based on a tradeoff between power consumption and noise. Moreover, the RF input matching network modifies the conversion gain described in (1). Namely, it can be shown that the conversion gain now becomes,  oggs Lm ωRC Rg π 2 GC ≈ The LO signals are coupled to the LO input of the mixer by RLC narrowband networks resonating at 2.4 GHz. As can be seen in Figure 2, two scaled CMOS inverters in cascade are used to drive the LO signal. This way, at the output of the buffer inverters, the signal results in trapezium waveforms, with 1.2V amplitude, as shown in Figure 3. Nevertheless, the switches can be directly driven by antiphase sinewave signals, without an additional LO buffer, but in this case, the conversion gain is degraded. Figure 4 shows the comparison of the simulated conversion gain when input matching and LO buffers are used and when the sinewave signals are directly driven to the switches. It can be seen that the input matching and the buffer increases the conversion gain. Moreover, the LO buffer reestablishes the LO levels, keeping the conversion gain in 20 dB when the LO amplitude is decreased. The choice of the ratio WP/WN of the switch transistors affects the ratio between the ON- and OFF-switching time and common-mode output currents. As PMOS transistors have mobility roughly two times lower approximately, WP/WN is chosen to be around two. If the switch width decreases, keeping WP/WN=2, the conversion gain results in a gradual degradation, as shown in Figure 5. The final decision was WN/LN=25u/0.24u and WP/LP=50u/0.24u The ZigBee standard imposes that the system should work properly for input signal power from -20dBm to -85dBm. In order to relax the variable gain amplifier specifications and reduce the overall noise in the whole receiver, the mixer was designed with two gain modes; 12 dB for RL =1k and 20 dB for RL=12k. The common-mode current is absorbed by the two PMOS load transistors, allowing for more conversion gain. The current source Ib shifts the common-mode output voltage to near 0.6V. This current source is adapted to the gain mode, in order to maintain the output common mode voltage around 0.6V when the gain is changed. The selected element sizes and dimensions are listed in Table I. Mixer design has been performed under the Cadence® Design Framework II environment using SpectreRF simulator. Figure 6 shows the S11 curve of the mixer. The input return loss is below -20 [email protected]. Noise Figure (NF) results are shown in Figure 7; values at 2.5MHz are 18.1dB at high gain and 18.9 dB at low gain mode. As expected from (9), NF is higher in the low gain mode because the load resistor is smaller. Input third order intercept point IIP3 is set at RF frequency of 2.4025 GHz and 2.4035 GHz with 1MHz separated. Figure 8 shows the output power of fundamental and 3rd-order inter-modulation. . IIP3 is determined to be -3.1dBm and -3.5dBm while P1dB is - 11.6dBm and -10.5dBm at low and high gain respectively. TABLE I. Device sizes and dimensions M1,3 (m) M2,4 (m) M5-8 (m) M9,10 (m) RL (k) VB (V) 50/0.24 25/0.24 160/0.24 52.8/0.24 1-12 0.5 Rg () Lg (nH) Cgs (pF) RLO () LLO (nH) CLO (pF) 51 2.13 1.60 17 2.13 1.85 11.5 22.5 x 10 -9 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 time (s) Amplitude (V) Figure 3. Waveform at the output of the LO buffer inverters 0.4 0.5 0.6 0.7 0.8 0.9 11.1 1.2 1.3 10 12 14 16 18 20 22 LO Amplitude (V) CG (dB) Without Input Matching With Input Matching Figure 4. Simulated Conversion Gain versus LO amplitude with and without input matching and LO buffer (RL=12K) 20 25 30 35 40 45 50 7 8 9 10 11 12 13 14 Wp (um) CG (dB) Wp/Wn=2 Figure 5. Simulated conversion gain as a function of swicth width (keeping Wp/Wn=2, RL=1K) 00.5 11.5 22.5 33.5 4 x 10 9 -35 -30 -25 -20 -15 -10 -5 0 frequency (Hz) S11 Magnitude (dB) High Gain (Rl=12K) Low Gain (Rl=1K) Figure 6. S11 simulation results for the two gain mode 22.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 x 10 6 17.6 17.8 18 18.2 18.4 18.6 18.8 19 19.2 19.4 19.6 frequency (Hz) NF (dB) High Gain (Rl=12K) Low Gain (Rl=1K) Figure 7. NF simulation results for the two gain mode -40 -30 -20 -10 010 20 -100 -80 -60 -40 -20 0 20 40 60 80 100 RF Power (dBm) Output Power (dBm) IIP3= -3.1 dBm P1dB= -11.6 dBm Figure 8. Simulated IF output power versus RF power. IV. IC IMPLEMENTATION AND MEASUREMENTS Figure 9 shows a photograph of the implemented mixer. The total core silicon area including on-chip matching networks is 1005x855μm2, while the power consumption is 4.1mW and 4.4mW in low and high mode gain respectively (it includes the bias circuitry, LO buffers and ESD circuit protection). The mixer core consumes 1.96mW in both cases because the transconductance stages and the input and output common mode voltage remain identical when the gain mode is changed. Nevertheless, the current Ib is increased at low gain mode, in order to maintain the output common mode voltage around 0.6V. For this reason, power consumption is higher in the low gain mode. The chip has been measured via on-wafer probing of RF and LO ports through G-S-G-S-G probes using baluns for single to differential conversion at the input signals. A differential probe was used to measure the differential output voltage. Figure 10 shows the block diagram of the measure setup. HP8664A and HP81134A signal generators have been used to generate the required RF and LO signals at the 2.4 GHz band. The differential output signal is converted to single in order to be measured using the HP8562E Spectrum Analyzer. Despite the experimental inaccuracies, it can be concluded that the mixer has the expected 12dB and 20dB conversion gain at low and high gain modes respectively. Figure 11 shows the output signal spectrum for an input single tone at 2.4025GHz and a power of -26dBm. LO is centered at 2.4GHz and the mixer is programmed in high gain mode. In order to evaluate the linearity of the mixer, measurements with two input tones separate 1MHz at 2.4025GHz and 2.4035GHz have been carried out. Figure 12 shows the output signal spectrum for high gain mode and LO at 2.4GHz. The two input tones after mixing operation are situated at 2.5MHz and 3.5MHz while the 3rd-order intermodulation tones are at 1.5MHz and 4.5MHz. As it is shown in Figure 12, the intermodulation tones present attenuation with respect the desired tones of 50dB approximately. Figure 9. Layout of the designed mixer Figure 10. Measure Setup Block Diagram TABLE II. Performance summary and comparison to other CMOS mixers Ref CMOS Process RF Frequency [GHz] IF Frequency [MHz] CG [dB] NF [dB] IIP3 [dBm] Power [mW] Chip size [mm2] [8] 0.18 m 2.4 0 15.6 6.9 1.5 7.6 N.A. [9] 0.18 m 2.4 1 13† 18† -1† 7.2† 0.67 [10] 0.13 m 2.4 60 15.7† 15.7† -9† 0.5† 0.8 [11] 0.18 m 2.4 1 16 12.9 1 8.1 0.32 This work 90 nm 2.4 2.5 12 / 20*† 18.9 / 18.1* -3.1/ -3.5* 4.4 / 4.1*† (1.96 core) 0.85 *Low / High gain mode †Experimental Results Figure 11. Output Signal Spectrum spectrum for an input single tone at 2.4025GHz and a power of -26dBm Figure 12. IM3 Test for f1=2.4025GHz and f2=2.4035GHz V. CONCLUSIONS A low voltage and low power switched transconductor mixer in a 90nm CMOS process has been presented. RF and LO input matching networks are included in order to be measured using onwafer probing. Two possible gains of 12dB and 20dB can be set by programming the load resistor. LO signals are driven by CMOS buffer inverters to avoid conversion gain degradation. The RF stage operates in weak inversion for low power consumption; it is 4.1mW and 4.4mW at high and low gain mode respectively from a 1.2V power supply, but the core cell only takes 1.96mW. Simulation and experimental results show a very good performance in terms of linearity and noise when compared to other mixers in the literature. ACKNOWLEDGMENTS This work has been founded in part by the EC through the project SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400- 2008-71), the Spanish Government under project TEC2007- 68072/MIC and the Spanish Regional Government of Junta de Andalucía under the project ACATEX (P09-TIC-5386). REFERENCES [1] B. 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