A low-pass filter with automatic frequency tuning for a bluetooth receiver

A LOW-PASS FILTER WITH AUTOMATIC FREQUENCY TUNING FOR A BLUETOOTH RECEIVER M. Pedro1, J. Galán1, T. Sánchez-Rodríguez1, F. Muñoz2, R. G. Carvajal2, A. López-Martín3 1Dpto. Ing. Electrónica, de Sist. Informáticos y Automática, Universidad de Huelva, Spain 2Dpto. Ing. Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain 3Dpto. Ing. Eléctrica y Electrónica, Universidad Pública de Navarra, Spain ABSTRACT A third-order Gm-C Chebyshev low-pass filter with high linearity and automatic frequency programmability has been designed. The filter is intended to be used as a channel-select filter for a zero-IF Bluetooth receiver. The frequency tuning scheme is simpler and has more relaxed specifications than conventional ones. The filter bandwidth is 0.5 MHz and the overall scheme dissipates 1.1 mA from a 1.8-V supply. The third-order intermodulation (IM3) distortion of the filter for a 1Vpp two-tone signal centered at 350 kHz is −67dB. Index Terms— analog CMOS circuits, Gm-C filters, linear transconductors, frequency tuning, direct-conversion receivers. 1. INTRODUCTION The great demand for wireless communications systems has created new challenges for circuit designers from receiver architecture to cell level. Different requirement tradeoffs must be overcome related to complexity, power dissipation, bandwidth, linearity, integration level, noise and offset. The trend to implement fully integrated receivers with low power consumption has led the research about Gm-C filter strives to yield more efficient solutions than conventional active RC topologies. The stringent requirements for the analog channel filter of the receiver dominate the performance of the overall chain. The targeted application for the low-pass filter presented in this paper is the zero-IF filtering section of a Bluetooth receiver with an on-chip automatic tuning circuit required due to process tolerances [1]-[2]. The design meets the selectivity and linearity requirements of Bluetooth while consuming low power. Low-IF and zero-IF architectures seem to be more suitable for a Bluetooth receiver. The direct conversion receiver avoids the requirement for image rejection but the flicker noise and dc offset can degrade the signal to noise ratio. 2. TRANSCONDUCTOR TOPOLOGY The design has to be concerned with power efficiency but stringent linearity and noise performances are required as well. The need of a tunable transconductor with high linearity requirements [3]-[4] led us to the use of the MOS transistor in its triode region as linear voltage to current conversion since this allows a direct control on the MOS’s transconductance value through its VDS. The first-order expression for the largesignal drain current of an n-MOS transistor operating in strong inversion and the triode region is given by: () 2 μ = −− ⋅ DS D ox GS TN DS V W I CVV V L (1) and the linear dependence of the transconductance on VDS is μ ∂ == ∂ D M ox DS GS IW GCV VL (2) where all parameters have their usual meaning. According to the above equations, a triode transistor achieves ideally perfect linearity between the output current and the input voltage. This linear characteristic can be assumed for long channel MOS transistors. The transconductance cell is shown in Fig. 1. Both input transistors M1 and M2 are in the triode region and cascode transistors M3 and M4 are used to fix the drain voltage. Linearity is highly dependant on VDS of M1-M2 transistors because the large signal transconductance of M1,2 is directly proportional to their VDS. Regulated-cascode transistors must ensure that M1,2 drain voltage remains practically constant despite large input current variations. The feedback loop formed by transistors M5 and M6 and the bias current IB guarantees a very low variation of VDS1,2 around their quiescent value. Transistors M6 and M7 implement a very low impedance node at the common source of M5 and M6 that sets the dc voltage at drain of input transistors M1 and M2 to a value equal to the tuning voltage Vprog. The small signal impedance at the source of M6 is given by rx=1/(gm6 ⋅ gm7 ⋅ r6) where gm6, gm7 are 978-1-4244-8157-6/10/$26.00 ©2010 IEEE 467 ICECS 2010978-1-4244-8156-9/10/$26.00 ©2010 IEEE 467 ICECS 2010 2 the small-signal transconductance gains of M6 and M7, respectively, and r6 is the small-signal output resistance of M6. The solution to control the transconductance ensures power efficiency and simplicity. The feedback loop boosts the transconductor output impedance and maintains the output nodes isolated from the low impedance drain of the input transistor. The boosted output resistance at the drain of M3 is approximately: 35135 ≅⋅⋅⋅⋅ out m m o o o rggrrr , where the feedback loop gain is given by gm5ro5. Io is a voltagecontrolled cascode current source that ensures high output impedance. The programmability of the transconductor requires an adaptive-bias circuit (common-mode feedforward, CMFF) to set the common-mode output current. This circuit has been implemented with a replica of a branch of the transconductance cell. A conventional common-mode feedback circuit (CMFB) fixes the common-mode output voltage. Both CMFF and CMFB control the current source Io, stabilizing the common-mode output over the tuning range which is required for low supply voltage and high linearity, and further increase the CMRR of the pseudo-differential topology. DD V DD V o - I i+ V p rog V 1 M 3 M 5 M 7 M 6 M B I o+ I i - V 2 M 4 M 8 M o - V o + V B I B I DD V Fig. 1. Used transconductance cell. Design considerations: The tuning voltage Vprog of the circuit can be set to near ground. This fact allows to achieve a large tuning range while maintaining a low level of distortion in the output current for a given input voltage range, and requiring a low supply voltage for this kind of transconductor based on input transistors operating in triode region. The upper limit for the tuning voltage Vprog must ensure that M1 is kept in the triode region, and the condition Vprog < Vi,CM-(Vid/2)-VTN must be satisfied for the entire range of the input signal. It is necessary that M5 remains in saturation region for the complete range of Vi and the maximum value of Vprog. To fulfill that VSD5 > VSG5-VTH, the size of M3, M5 (M6) and the bias current IB, must be carefully adjusted. The transconductor was sized according the design parameters of a 0.5 μm n-well CMOS process with nMOS and pMOS threshold voltages of VTN = 0.67 V and VTP = −0.96 V, respectively. The following transistor sizes (in micrometers) were used: M1-M2: 20/3, M3-M4: 100/0.6, M5, M6, M8: 10/2, M7: 30/1.2 and the current bias IB = 10 μA. The circuit was simulated with a single supply VDD = 1.8 V and the commonmode input (output) voltage Vi,CM (Vo,CM) was set to 1.3 V. Fig. 2 shows the simulated transconductance range of approximately one decade between 15 to 165 μA/V for a tuning interval from Vprog = 25 mV to 250 mV. It can be seen that a linear behavior is obtained for a large differential input voltage. For the nominal transconductance (Vprog = 125 mV), the unity-gain frequency is 22 MHz, the quiescent input current is ID1= 43 µA, and the total power consumption about 360 µW. The post-layout simulated output spectrum for a 1- MHz input signal of amplitude of 1 Vpp, featuring −74 dB of THD for the nominal transconductance. Fig. 2. Simulated transconductor behavior. Transconductance versus differential input voltage 3. FILTER DESCRIPTION In order to use the properties of the transconductor, a continuous-time filter with severe linearity requirements and power efficiency for a zero-IF Bluetooth receiver has been designed. The filter specifications are given in Table I. TABLE I. CHANNEL FILTER SPECIFICATIONS Type Chebyshev Order 3th Topology Low Pass Passband ripple 0.5 dB Cutoff frequency 0.5 MHz DC gain 10 dB THD > 60dB For the third-order Chebyshev low-pass filter a Gm-C topology has been chosen as shown in Fig. 3. Vip Vin Vop Von 3 C 2 C 1 C 1m G 2m G 3m G 4m G 5m G 6m G Fig. 3. Third-order low-pass filter The implementation uses differential transconductors and poly-poly floating capacitors. The filter transfer function is given by: 468468 3 b1 I cm V cm ref VV− tune V GM out I out V 4 C 3 C 2 C 1 C 2 Φ b2 I D D V C2 V C3 V p rog V p rog V A V A 2 Φ 2 Φ 1 Φ 1 Φ 1 Φ 1 Φ 3 Φ 3 Φ 3 Φ C1 V p rog V cm ref VV − cm ref VV− cm ref VV − Fig. 4. Frequency tuning circuit for the filter. ( 13 12 5 3 2 63 21 3412 // () / (/) / mm m m mmm GG CC G C Hs s GC sGCsGGCC =⋅ + +⋅+ (3) The required voltage gain of ≈ 10 dB is achieved by adding three Gm1 transconductors in parallel. For the practical design all transconductance values are set to Gm= 64 µA/V (Vprog = 100 mV) giving the capacitor values C1 = C3 = 16.26 pF and C2 = 5.58 pF. The common-mode control has been implemented using a minimum number of adaptive-bias and CMFB circuits decreasing the area and the power consumption. The adaptive-bias circuit has been generated only once and mirrored to all transconductors. Furthermore, a CMFB circuit by filter node has been employed, leading to a more compact filter topology. Frequency tuning scheme Fig. 4 show the automatic frequency tuning circuit of the low pass filter used to compensate for process variations. The frequency tuning scheme uses the Gm/C tuning technique. This method basically uses an extra transconductor in the tuning circuit to generate the control signal for all the transconductors of the filter. Although the use of this technique requires a good matching between the extra transconductor and the filter’s transconductors, its simplicity allows very low power consumption and small silicon area. The frequency tuning circuit is based on a switched capacitor circuit controlled by three non-overlapping clock signals (Φ1, Φ2 and Φ3) and consists of only three capacitors, some switches and a replica transconductor to adjust the pole frequency of the filter. The operation of the tuning circuit is described as follows: During the clock phase Φ1, capacitors C1 and C2 are charged to the following values: 1 21 1C IT Vb C ⋅ = (4) )( 2refcmprogC VVVV −−= (5) where T1 is the period of time in which Φ1 is active, Vcm is the common-mode input voltage of the transconductor, Vref is a reference voltage and Vprog is the theoretical control voltage of the transconductor. In phase Φ2, capacitors C1 and C2 are connected in series and both in parallel with capacitor C3, so a charge transfer takes place between these three capacitors. Finally, the purpose of clock phase Φ3 is to reset the capacitor C1 in order to start in a correct value the next clock phase. In quiescent conditions: progrefcm b Aout VVV C IT VV −−+ ⋅ =− )( 1 21 (6) 1() boutcmref IGmV VV ⎡ ⎤ =⋅ − − ⎣ ⎦ (7) )( progAtune VVAV −⋅= (8) Using the expressions shown above: 11 1 21 21 1 bb b tune b II C Gm ITV I T CA =≈ ⋅+ (9) As it can be noticed from expression (9) the transconductance value is proportional to the value of capacitor C1 that will be affected by process variations in the same way the capacitors of the filter. The term given by Vtune/A is just an error that can be negligible if the amplifier gain is high enough. In our case an amplifier gain of only 20 dB is needed, so that a very simple architecture has been used. The main advantage of the tuning circuit is that the operational amplifier has more relaxed specifications of gain and bandwidth, and no need an extra low-pass filter at the output to stabilize the tuning voltage of the filter as conventional solutions. The frequency tuning topology gives a good tradeoff between simplicity and performance. 469469 4 4. SIMULATION RESULTS The filter and the frequency tuning have been designed in a 1.8-V, 0.5 μm CMOS technology. The filter area is 0.52 mm2, and the tuning circuit area is 0.16 mm2. The circuit operates from a single 1.8-V and draws 1.1 mA. The simulated frequency response is shown in Fig. 5. The automatic tuning loop ensures that the cut-off frequency of the filter remains constant for process variations. The accuracy in the tuning system shows that a ±20% variations on the capacitor sizes results in a tuning error of only a ±1% in the cut-off frequency. Fig. 6 shows the post-layout simulated output spectrum for a 100-kHz signal of peak-to-peak amplitude of 1 V, featuring −72 dB of THD. Distortion is mainly of third order owing to the balanced topology. Fig. 7 illustrates the simulated third-order intermodulation distortion of the filter for a 1-Vpp two-tone signal centered at 350 kHz is –67 dB. Table II summarizes the performance parameters of the filter. Fig. 5. Frequency response. Fig. 6. Output power spectrum for 100 kHz, 1 Vpp signal. 5. CONCLUSIONS A Gm-C filter for zero-IF Bluetooth receiver has been presented. The design uses a pseudo-differential transconductor suitable to operate in low voltage environment with a good tradeoff between performance and compactness. An automatic frequency tuning circuit with more relaxed specifications and simplicity those conventional solutions has been used. The filter achieves a distortion of −72 dB for a 100 kHz, 1 Vpp input voltage at a 1.8 V supply voltage. TABLE II. FILTER PERFORMANCE PARAMETERS Parameter Value Technology 0.5 μm CMOS Threshold voltage VTP = −0.96V, VTN = 0.67V Supply voltage 1.8 V Cut-off frequency 500 kHz THD@100kHz, 1Vpp −72 dB IM3@350kHz, 1Vpp −67 dB Current consumption 1.1 mA Silicon area 0.68 mm2 Fig. 7. Simulated IM3. The intermodulation component is at −67dB for a 1Vpp. Input tones are at 300 kHz and 400 kHz. ACKNOWLEDGMENTS Authors would like to acknowledge financial support from the Spanish CICYT under project TEC2007-67460-C03-02. 6. REFERENCES [1] A. N. Mohieldin and E. Sánchez-Sinencio, “A dual-mode lowpass filter for 802.11b/Bluetooth receiver,” in Proc. ESSCIRC, pp. 423-426, Sep. 2004. [2] D. Chamla, A. Kaiser, A. Cathelin and D. Belot, “A Gm-C Low-Pass Filter for Zero-IF Mobile Applications with a Very High Tuning Range”, IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1443–1450, July 2005. [3] W. Huang and E. Sánchez-Sinencio, “Robust highly linear highfrequency CMOS OTA with IM3 below -70 dB at 26 MHz,” IEEE Trans. Circuits and Systems I, vol. 53, no. 7, pp. 1433– 1447, Jul. 2006. [4] J. Chen, E. Sánchez-Sinencio, and J. Silva-Martinez, “Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 499–510, Mar. 2006. 470470