Overview of carbon-based circuits and systems

Overview of Carbon-Based Circuits and Systems Saul Rodriguez, Ana Rusu Royal Institute of Technology School of ICT, KTH Kista 16440, SWEDEN E-mail: [saul,arusu]@kth.se Jos´ e M. de la Rosa Instituto de Microelectr´ onica de Sevilla IMSE-CNM (CSIC/Universidad de Sevilla) C/Am´ erico Vespucio, 41092 Sevilla, SPAIN E-mail: [email protected] Abstract—This paper presents an overview of the state of the art on carbon-based circuits and systems made up of carbon nanotubes and graphene transistors. A tutorial description of the most important devices and their potential benefits and limitations is given, trying to identify their suitability to implement analog and digital circuits and systems. Main electrical models reported so far for the design of carbon-based field-effect devices are surveyed, and the main sizing parameters required to implement such devices in practical integrated circuits are analyzed. The solutions proposed by cutting-edge integrated circuits and devices are discussed, identifying current trends, challenges and opportunities for the circuits and systems community1. I. INTRODUCTION Carbon-based nanomaterials and nanodevices, such as graphene and Carbon NanoTubes (CNTs), are among the most promising candidates to either replace or complement silicon-based Field-Effect Transistors (FETs) in future beyond- CMOS Integrated Circuits (ICs). The outstanding physical and electrical properties of these nanomaterials, including their – a priori – excellent carrier mobility, current density, transition frequency, near-ballistic transport, thermal conductivity, adjustable bandgap as well as the possibility to use the same material to build diverse IC elements, have prompted the interest of many researchers in both academy and industry for CNT-FETs and Graphene-FETs (G-FETs) in order to continue the technology downscaling toward deep nanoscale level in an efficient way in terms of energy and cost [1], [2]. In spite of the mentioned benefits, after the initial enthusiasm for carbon-based nanoelectronics, a number of inherent physical limitations and device imperfections have been reported that make the use of CNT-FETs and G-FETs to implement competitive chips still far from reality. Among others, the most limiting factors are the poor current saturation, the large contact/access resistances, the influence of synthesis/fabrication process variability (in CNTs); the missing gap, the ambipolar conduction, the difficulty to switch off and the carrier mobility-vs-bandgap trade-off (in G-FETs). As a consequence, state-of-the-art carbon-based ICs mostly consist of small circuits made up of single devices or just a few transistors [3], [4]. 1This work was partially supported by European Commission through a STREP project (GRADE,No.317839) and by the Spanish Ministry of Economy and Competitiveness (with support from the European Regional Development Fund) under contracts TEC2010-14825/MIC and TEC2013- 45638-C3-3-R, and by ”Consejer´ ıa de Econom´ ıa, Innovaci´ on, Ciencia y Empleo de la Junta de Andaluc´ ıa”, under contract P12-TIC-1481. With the aim of addressing these limitations, recent advances in device fabrication techniques as well as appropriate design methodologies are being developed in order to push CNT and graphene technologies forward and to demonstrate the feasibility of carbon-based integrated circuits and systems [5]. These methods are running in parallel with the development of SPICE models to accurately simulate CNT-FET/G- FET circuits and to systematize their analysis and design by following a top-down/bottom-up approach [6]–[14]. In this scenario, the aim of this overview paper and this special session is to present a survey of recent advances in CNT-FET and G-FET circuits and systems. To this end, the fundamental concepts related to carbon-based transistors are reviewed, putting emphasis on their physical structure, electrical properties and main design/sizing parameters. The most relevant electrical models and design methods are discussed in order to show the current state of the art on CNT and graphene technologies, from a circuits-and-systems perspective, by covering the main aspects of the design procedure, physical implementation and applications. Main practical issues and trends are identified as well as the solutions proposed by cutting-edge designers, with emphasis on those applications in which carbon-based nanodevices may be competitive with respect to standard CMOS. All these ingredients are put together as an introduction to this special session, contributed by several selected experts in the field, which present their recent results and developments in the frontiers of the state of the art on carbon-based nanoelectronics. II. SURVEY OF CARBON-BASED TRANSISTORS Carbon-based transistors aim to get advantage of the excellent electronic properties of two allotropic forms of carbon, namely: CNTs and graphene. To this end, different FET devices can be built by replacing the channel of a conventional CMOS transistor by either CNTs or graphene sheets. This is illustrated in Fig. 1, which shows the conceptual structure of some CNT-FETs and G-FETs reported in literature. A. CNT Transistors Fig. 1(a) shows the schematic cross-sectional structure and symbol of a typical CNT transistor. In this device, the channel consists of a number, ntub, of CNTs which connect the drain and source terminals, and its conductance is modulated by the voltage applied at the gate terminal – similarly to Drain Substrate Dielectric Drain LCNT WCNT Wsc Nanotubes Gate Source (b) (c) Dielectric Drain Source Gate Substrate Dielectric Drain Source Gate Graphene LGFET WGFET Drain Gate Substrate Dielectric Graphene Nanoribbons Drain Source Gate LGNR Wsg WGNR G-FET GNR-FETCNT-FET LCNT,s Drain Gate Source n-type (a) Drain Gate Source n-type Fig. 1. Schematic symbol and cross-sectional conceptual view of the physical structure of: (a) CNT-FETs. (b) G-FETs. (c) GNR-FETs CMOS transistors. Indeed, the main sizing parameters are the dimensions of the channel – defined by the length, LCNT, and width, given by WCNT =ntub ·Wsc, with Wsc being the separation between the centres of two adjacent CNTs. Note that WCNT is proportional to the diameter of the CNTs, given by dCNT =a/π ·√m2+m·n+n2, with (m, n)denoting the chirality vector and a= 2.49 ˚ A being the lattice constant [6]. Another important characteristic of CNTs is that their band-gap energy, Eg, is inversely proportional to dCNT. This property makes CNTs a powerful material for electronics, although it strongly depends on the way in which CNTs are synthesized and grown. Typically, CNTs with dCNT = 1.5nm, m= 19, n = 0 (zigzag CNT), Wsc = 4-5nm are fabricated with densities of 200-250 CNTs/µm [5], [10]. The CNT transistor in Fig. 1(a) can be modeled at electricallevel for circuit design and simulation purposes. One of the most successful and accurate SPICE models was developed by Deng et al at Stanford University [6], [7]. Based on this model, the following simplified expression of the drain-source current, IDS-CNT, can be derived as [10]: IDS-CNT =ntub ·gCNT ·(VDD −Vth,CNT) 1 + gCNT ·LCNT,s (1) where VDD is the supply voltage, gCNT is the transconductance per CNT, Vth,CNT is the threshold voltage and LCNT,s is the length of the doped source region of the CNT (see Fig. 1(a)). Although the above expression may be useful for some hand calculations, the complete SPICE model [6], [7], is used for a precise simulation. An alternative model can be derived using the Landauer formula [15]. However, this procedure requires using numerical methods to obtain closed-form solutions, what makes it difficult its use in circuit design [16], [17]. B. Graphene Transistors A G-FET can be built by using a graphene sheet to implement the transistor channel, as conceptually depicted in Fig. 1(b). The potential use of this device in ICs has prompted the interest of a number of researchers for finding out electrical models which can be used for circuit design and simulation [12], [14], [18], [19]. Among others, the model proposed by Fr´ egon` ese et al at the University of Bordeaux [12] provides an accurate description of the device operation, including its main non-ideal and second-order phenomena, and can be coded in SPICE or Verilog-A for circuit simulation. Based on this model, the drain-source current of a G-FET can be expressed as [14]: IDS-GFET =µWGFET ·RVDSi 0(|Qnet|+e·npuddle)dV LGFET +µ·  RVDSi 0 1 vSAT dV    (2) where µis the electron mobility, Qnet is the net mobile charge density per unit area, eis the electron charge, VDSiis the internal drain-source voltage, vsat is the saturation velocity and npuddle = ∆2/π¯h2v2 f, with ∆being the spatial inhomogeneity of the electrostatic potential, ¯his the reduced Planck constant, and vfis the Fermi velocity. Note from (2) that the basic sizing parameters of a G-FET are the length, LGFET, and the width, WGFET, of the graphene sheet, i.e. the channel dimensions – similar to CMOS. However, if the graphene sheet is not narrow enough, Eg= 0. This property has two critical consequences for the operation of G-FETs. First, the transistor does not switch off completely. Instead, a minimum off drain-source current is found in the inflection point (also called Dirac point) resulting in low on/off current ratios which limit their application for digital circuits. Second, the device presents an ambipolar conduction, behaving as either an n-type or p-type FET, depending on the polarity of the voltage applied at the gate [3]. This is illustrated in Fig. 2(a), where IDS-GFET is plotted versus VGS, by using HSPICE®for different sizings compared to 32-nm CMOS. Both CNT-FETs and G-FETs have shown saturation regions which are an important requirement to build amplifiers. Indeed, under specific biasing conditions, G-FETs exhibit negative differential resistance which can be very useful for oscillators and latch-based circuits design. This is illustrated in Fig. 2(b), which compares the IDS-vs-VDS curves of G-FETs and CNT-FETs for different technology nodes. An alternative to solve the switching problem of G-FETs consists of replacing the large-area graphene sheet by a (a) (b) Fig. 2. Characteristics of carbon FETs: (a) IDS-vs-VGS. (b) IDS-vs-VDS. number of graphene ribbons with narrow widths (typically < 10nm). This way, as Egis inversely proportional to the ribbon width, the resulted transistors, named Graphene NanoRibbon FETs (GNR-FETs), open the bandgap of graphene, and hence, can be switched off and used for digital logic purposes [3]. Fig. 1(c) shows the conceptual structure of a typical GNRFET, where main design parameters are highlighted – based on the SPICE model presented in [13] and available in [20]. According to this model, the channel length, LGNR, is the length of one of the graphene nanoribbons, while the channel width can be expressed as WGNR =nrib ·(Wsg + 2 ·Wc)[13], where nrib is the number of nanoribbons, Wsg is the spacing between two adjacent nanoribbons and Wc=√3dcc ·(N+ 1)/2, with dcc = 0.142nm being the carbon-carbon bond distance and Nis the number of dime lines [13]. As shown in Fig. 2(a), the transfer characteristic of a GNR-FET is similar to that of CMOS, although GNR-FETs feature a more resistive behavior. III. STATE OF THE ART ON CNT-BASED ICS CNT-FETs are – a priori – excellent candidates for building highly energy-efficient digital systems, in which are projected to achieve an order of magnitude improvements in energydelay product compared with silicon-based CMOS at highly scaled technology nodes [2], [5]. However, since the first experimental demonstrations of CNT-FETs, the majority of reported ICs have been based on device-level measured results [21]. The implementation of more complex CNT-FET ICs has not been possible due to inherent CNT imperfections and variations, among others: mispositioned CNTs, presence of metallic CNTs, ntub/CNT-FET density variations, etc [10]. These limitations may severely degrade the performance of CNT-FET based ICs, what has motivated the development of suitable design methodologies to overcome them. One of the most successful approaches is the so-called imperfectionimmune design paradigm (IIDP) proposed by Zhang et al. [11], which is based on CNT-specific aligned-active layout techniques to control and minimize the mentioned CNT variations. This methodology can be combined with the so-called VLSI-compatible Metallic CNT Removal (VMR) technique to improve the ratio of semiconductor and metallic CNTs up to 99.99% [9]. Based on these strategies, the authors in [8] presented a technique for designing CNT-FET logic circuits with a number of misaligned and mispositioned CNTs. The implemented CNT-FET immune logic ICs demonstrated to be 13 times more efficient than their 32-nm CMOS counterparts, in terms of energy-delay product. Indeed, the use of IIDP and VMR techniques enabled the first experimental demonstration of several functional CNFET logic circuits, namely: VLSI- compatible CNFET full adders and other arithmetic elements and latches [9], [22] as well as monolithic 3D ICs using CNFETs [23]. Other CNFET circuit demonstrations include ring-oscillators [24] and adder circuits on a single CNT [25]. Apart from their use in digital applications, more recently, a group of researchers from Stanford University and Katholieke Universiteit Leuven (KUL) has successfully demonstrated a complete sensor interface IC made up of CNT-FETs [5]. All these demonstrators, fueled by the development of appropriate design methodologies and fabrication techniques, are making possible the implementation of more and more complex CNTFET based ICs, which are expected to outperform technologies based on other alternative nanodevices – like FinFETs and silicon-nanowire transistors – at highly scaled nodes (<9nm) with reduced operating voltage (<0.5V) [5], [26]. IV. STATE OF THE ART ON GRAPHENE-BASED ICS One of the big advantages of graphene with respect to silicon CMOS is its superior electron mobility. It has been shown that carrier mobilities of graphene in SiO2substrate supported devices can be µ= 2 ×104cm2V−1s−1[27]. As a comparison, a standard 65-nm RF CMOS process – commonly used in today’s consumer electronics – has a low-field mobility of barely µ= 350cm2V−1s−1. In practice, charged impurities in the dielectrics degrade the electronic properties of graphene, and particularly its mobility. This problem can be tackled by using other dielectrics such as h-BN, leading to µ= 6 ×104cm2V−1s−1[28]. These high mobilities are directly reflected in high intrinsic transit frequencies, fT. Indeed, cutting-edge G-FET devices feature fT= 210 GHz for LGFET = 210nm [29], fT= 280 GHz for LGFET = 40nm [30], and fT= 300 GHz for LGFET = 144nm [31]. Based on their outstanding mobilities, the state-of-the-art shows the potential of G-FETs for ultra-high-data rate mobile communications systems. In addition, G-FETs present very high linearity performance which is fundamental in RF frontends [32]. Indeed, one promising approach is an all-graphene based mm-wave radio module, which can be connected to silicon-based digital baseband processors in next-generation (5G) mobile communication systems as conceptually illustrated in Fig. 3. These systems will require circuits operating in the mm-wave range, i.e. 10GHz-100GHz. Although latest nanometer CMOS technologies can potentially provide a costeffective solution if products enter mass-production stage, the use of G-FETs may become more energy-efficient. Indeed, although current graphene technology is not mature enough, ultra-high-frequency/RF G-FET ICs have been successfully demonstrated. Thus, a broadband mixer working up to 10 GHz has been reported in [33], an harmonic mixer operating at 30 GHz in [34] and a ring oscillator working at 1.28 GHz in [35]. Apart from being used in transistors, the outstanding electric and mechanic characteristics of graphene Fig. 3. Conceptual illustration of G-FET-based 5G telecom systems. have also attracted attention in other related fields. Thus, suspended graphene membranes which can be mechanically actuated by an external electric field have been used in RF MEMs. These devices can be applied to build RF switches, variable capacitors and resonant cavities, among others [36]. All these results – comparable or even outperforming similarly sized CMOS transistors – are extremely encouraging considering that the first G-FETs appeared only a few years ago. V. CONCLUSIONS AND SPECIAL-SESSION OVERVIEW An overview of the state of the art on carbon-based circuits and systems has been presented, giving a tutorial survey of CNT-FETs and G-FETs, their main electrical characteristics, potential advantages and limitations. Cutting-edge ICs has been revised, which demonstrate that by using suitable design methodologies and implementation strategies, successful and even outstanding performance can be achieved in both analog and digital applications. The versatility of graphene and CNT materials to implement different types of circuit elements in an IC, together with their benefits with respect to silicon-based CMOS transistors, demonstrate the strong potential of G-FETs for future energy-efficient digital logic and ultra-high-speed analog/RF ICs in the post-CMOS era. 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