Low-Power Artifact-Aware ImplantableNeural RecordingMicrosystem for Brain- Machine Interfaces

Doctoral Thesis Low-Power Artifact-Aware Implantable Neural Recording Microsystems for Brain-Machine Interfaces Author: Norberto Pérez Prieto Advisors: Manuel Delgado Restituto Ángel Rodríguez Vázquez Tutor: Ángel Rodríguez Vázquez Sevilla 2021 Low-Power Artifact-Aware Implantable Neural Recording Microsystems for Brain-Machine Interfaces Norberto Pérez Prieto PROPUESTA DE TESIS DOCTORAL PARA LA OBTENCIÓN DEL GRADO DE DOCTOR EN CIENCIAS Y TECNOLOGÍAS FÍSICAS Advisors: Manuel Delgado Restituto Ángel Rodríguez Vázquez Tutor: Ángel Rodríguez Vázquez Sevilla, 2021 Low-Power Artifact-Aware Implantable Neural Recording Microsystem for Brain- Machine Interfaces Doctoral Thesis Universidad de Sevilla Author: Norberto Pérez Prieto Master in Microelectronics Advisor: Manuel Delgado Restituto Senior Scientist Instituto de Microelectronica de Sevilla Consejo Superior de Investigaciones Advisor and Tutor: Ángel Rodríguez Vázquez Full Professor Electronics and Electromagnetism Department Universidad de Sevilla Universidad de Sevilla Consejo Superior de Investigaciones Científicas Centro Nacional de Microelectrónica Instituto de Microelectrónica de Sevilla Calle Américo Vespucio, 28. Parque Científico y Tecnológico Cartuja. 41092 Sevilla Author e-mail: norber[email protected] This work is licensed under a Creative Commons Attribution-Non Commercial- No Derivatives 4.0 International License. A todos los que creyeron en mí y me apoyaron durante este viaje. Acknowledgements Desde el momento en que comencé a redactar este documento fui posponiendo la escritura de este apartado. No porque lo considere de menor importancia al resto, sino porque resumir en unas líneas que realmente hagan justicia a todo el apoyo y confianza que se ha depositado en mí durante estos años me parece imposible. Agradecer a cada persona que ha puesto su grano de arena para que esta tesis siquiera llegara a ser, me tomaría, tal vez, otro documento de al menos la extensión de este. Por ello, por todo mi desarrollo tanto personal como profesional, gracias a todas y cada una de las personas que incluso inconscientemente han hecho que esta tesis sea posible. Gracias de corazón a todos. En primer lugar quisiera agradecer especialmente al Dr Manuel Delgado Restituto por su apoyo y supervisión durante toda esta etapa. Sus conocimientos y experiencia en una temática tan multidisciplinar como la englobada durante esta tesis han permitido, sin duda alguna, que este trabajo sea posible. Además, sería banal no agradecer todo lo compartido durante este tiempo más allá de los circuitos integrados. Esto también se extiende al Dr Ángel Rodríguez Vázquez, quién allá por 2016, teniendo más fe en mí de la que yo tenía por aquel entonces, me propusiera emprender esta aventura y por la que siempre le estaré agradecido. La pasión y consejos de ambos han sido de un valor incalculable y me han permitido un crecimiento que nunca hubiera imaginado, tanto a nivel profesional, como personal. Gracias, no puedo estar más agradecido. Agradecer al Ministerio de Ciencia e Innovación por dotarme con un contrato FPI (BES-2017-081603) que me ha permitido llevar a cabo esta tesis. En tercer lugar, agradecer a cada uno de los compañeros con los que he compartido grupo de investigación durante estos años: Rafaella, José Luis, David y James. La ayuda prestada por ellos en cada uno de los proyectos llevados a cabo durante esta tesis es inestimable. Más allá de lo laboral, siempre agradeceré ese apoyo recibido y esa ayuda que me habéis dado para encarar todas las xii LIST OF FIGURES 3.6 Example of the signal folding technique [ 9 ]. (a) Output signal (a) without applying the signal folding technique. (b) applying the signal folding technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.7 Example of the performance of the PGA tuning technique [10]. . . . 32 3.8 Example of the performance of the ∆ -Encoding technique along with template-based artifact subtraction [11, 12]. . . . . . . . . . . . . . . . 33 3.9 CM artifacts-suppresion techniques. (a) CM cancellation path. (b) Switched-capacitor (SC) CM cancellation scheme. . . . . . . . . . . . 34 3.10 Artifacts-suppression techniques. (a) Artifacts suppression feedback front-ends. (b) Post-processing artifacts suppression front ends. . . . 36 3.11 Example of the performance of a mixed-signal adaptive stimulation cancellation technique [13]. . . . . . . . . . . . . . . . . . . . . . . . . 37 3.12 Example of the performance of the Adaptive Stimulation Artifact Rejection (ASAR) technique [14]. . . . . . . . . . . . . . . . . . . . . . 38 4.1 (a) Conventional neural recording front-ends for multiple channels. (b) Time-multiplexed neural recording front-end for multiple channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 Time-division multiplexing technique. . . . . . . . . . . . . . . . . . . 40 4.3 (a) MOSFET device as a switch. (b) Simplified equivalent circuit model for MOSFET as a switch. (c) Equivalent circuit model for crosstalkanalysis of a M -channels multiplexer. (d) Equivalentimpedance model for multiplexing at the electrode interface. . . . . . . . . . . . 42 4.4 Multiplexer crosstalk for TDM at the electrode interface against electrode impedance for (a) a 2-channel multiplexer. (b) a 64-channel multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 Multiplexer crosstalk for TDM before the PGA against the IA’s output resistance for (a) a 2-channel multiplexer. (b) a 64-channel multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6 (a) Non-multiplexed AFE topology. (b) PGA sharing AFE topology. (c) ADC sharing AFE topology. (d) Switch array AFE topology. (e) Time-division-multiplexing AFE topology. . . . . . . . . . . . . . . . 45 4.7 Simplified block diagram of the PGA sharing topology presented in [15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.8 Simplified block diagram of the switch array AFE topology presented in [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.9 NEB against the number of multiplexed channels in VS-based and CS-based TDM AFEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.10 Noise folding problem in (a) VS-based multiplexing circuits. (b) CS-based multiplexing circuits . . . . . . . . . . . . . . . . . . . . . . . 52 4.11 Block diagram of the reported TDM AFE topology in (a) [ 17 , 18 ]. (b) [12]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.12 (a) Scheme of the TDM AFE proposed in [ 17 , 18 ]. (b) Timing diagram of the presented scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LIST OF FIGURES xiii 4.13 (a) Scheme of the TDM AFE proposed in [ 11 , 12 ]. (b) Timing diagram of the presented scheme for no CM signals supression. Note that φAZ2and φT IE are not shown and open for the whole period. . . . . 57 5.1 Block diagram of the proposed neural recording system. . . . . . . . 60 5.2 (a) Input multiplexer and spatial delta coding generation. Timing diagram of the (b) monopolar and (c) bipolar sensing modes. . . . . 62 5.3 Noise folding in multiplexing circuits applying a narrow-band CDS architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.4 (a) Instrumentation amplifier IA1 . The inset shows the schematic of the two 8-b DACs used for closing the feedback loops in Figure 5.1. Amplifier IA2 uses the same structure, excluding the input multiplexer, capacitors Cib and DACs. Unparenthesised clock phases hold for IA1 , while parenthesized phases are for IA2 . (b) Timing diagram of the amplifiers and the SAR ADC. . . . . . . . . . . . . . . . . . . . . 65 5.5 Current-reuse OTA topology used in the instrumentation amplifiers. 66 5.6 Total settling error of the IA1against the sampling frequency. . . . . . 67 5.7 Illustration of the output of IA2 along with timing information. Time unit Tm is the period of the master clock. A similar settling behavior is also observed with IA1, although with smaller voltage excursions. . 67 5.8 Normalised transfer function of the CDS instrumentation amplifier for different gain settings. The IA1bandwidth is marked in red. . . . 68 5.9 Output noise spectral density comparison between simulation results and the proposed model. . . . . . . . . . . . . . . . . . . . . . . . 68 5.10 System scalability in terms of the number of multiplexed channels: (a) Power consumption per channel; (b) in-band IRN; and (c) area per channel occupation (only analog circuitry). . . . . . . . . . . . . . 70 5.11 System scalability in terms of bandwidth: (a) AFE power consumption per channel; (b) in-band IRN; and (c) area per channel occupation (only analog circuitry). . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.12 Block diagram of 2nd-Order CIC filter with decimation. . . . . . . . . 71 5.13 Block diagram of the Binary Search DC Servo Loop. . . . . . . . . . . 72 5.14 Illustration of the different operation modes of the binary Search block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.15 Block diagram of the auto-ranging circuit. . . . . . . . . . . . . . . . . 74 5.16 Attenuation of sinusoidal artifact versus tone frequency. . . . . . . . 76 6.1 (a) Die photograph of the ASIC prototype. (b) PCB for the testbench. 78 6.2 System’s power budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 (a) Measured AFE transfer function. (b) Input referred noise of the AFE. (c) Output spectrum of the AFE with input tone of 5m Vpp at 27Hz. (d) CMRR and PSRR. . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 Measured AFE input-referred noise for different DAC settings. . . . . 80 xiv LIST OF FIGURES 6.5 Measured transient response to large input signal (a) after filtering and decimation (Mode-1). (b) after signal reconstruction (Mode-2). . 81 6.6 SNDR versus input amplitude for (a) Mode-1 and (b) Mode-2. . . . . 82 6.7 Signal set from channels #1-#4 to illustrate the spatial delta encoding techniques implemented in the ASIC: (a) Input signals, (b) inputreferred signals using bipolar sensing mode, (c) input-referred signals after decoding, (d) same with residual offsets removed with the HPF in the micro-controller and (e) Input-referred decoding error. . 83 6.8 ADC output w/out (a) and with (b) bipolar sensing. . . . . . . . . . . 84 6.9 Output code range histograms for signals from Figure 6.8 w/out (a) and with (b) bipolar sensing. . . . . . . . . . . . . . . . . . . . . . . . . 84 6.10 Average decoding output error obtained by the monopolar and bipolar spatial delta-encoding in terms of the channel index i. . . . . . . 85 6.11 (a) Pre-recorded in vivo signals containing APs captured at 30kS/s. (b) Signal captured by the proposed circuit in Mode-2 at 6kS/s. . . . 86 6.12 Experimental setup for in-vitro measurements. . . . . . . . . . . . . . 86 6.13 (a) Pre-recorded motion artifact plus in-band 1.5 mV pp tone applied to the saline solution, (b) output with ARL disabled, (c) Mode-1 output signal, (d) artifact compression code and (e) reconstructed signal in Mode-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.14 (a) Voltage in the saline solution after applying a biphasic stimulation current pulse, (b) output with ARL disabled, (c) Mode-1 output signal, (d) artifact compression code and (e) reconstructed signal in Mode-2. 88 LIST OF TABLES 1.1 Neural Recording Techniques Comparison . . . . . . . . . . . . . . . 4 2.1 Required Specifications for Multi-Channel Neural Recording AFEs . 11 2.2 High-Performance Neural Front-End Comparison. . . . . . . . . . . . 20 2.3 State-of-art of Neural AFEs (1). . . . . . . . . . . . . . . . . . . . . . . . 24 2.4 State-of-art of Neural AFEs (2). . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 Power-area State-of-art of Multi-channel Neural Recording Systems. 49 5.1 Summary of Frequency Parameters . . . . . . . . . . . . . . . . . . . . 61 6.1 Comparison with State of the Art . . . . . . . . . . . . . . . . . . . . . 90 6.2 Time-multiplexed Amplification-Filtering Stages Comparison . . . . 91 A.1 Instrumentation Amplifier Parameters . . . . . . . . . . . . . . . . . . 98 xv ACRONYMS ADC Analog-to-Digital Converter. AFE Analog Front-End. ALS Amyotrophic Lateral Sclerosis. AP Action Potentials. ARL Auto-Ranging Loop. ASAR Adaptive Stimulation Artifact Rejection. ASIC Application Specific Integrated Circuit. AZ Autozero. BCIs Brain-Computer Interfaces. BLE Bluetooth Low-Energy. BMIs Brain-Machine Interfaces. CCO Current-Controlled Oscillator. CDS Correlated Double Sampling. CIC Cascaded Integrator–Comb. CM Common-Mode. CMFB Common-Mode Feedback. CMRR Common-mode Rejection Ratio. CS Charge-Sampling. CT Continuous-Time. DAC Digital-to-Analog Converter. xvii xviii ACRONYMS DBS Deep Brain Stimulation. DM Differential-Mode. DSL DC Servo Loop. DT Discrete-Time. ECoG Electroencephalographic. EEG Electroncephalogram. FIR Finite-Impulse-Response. FPGA Field-Programmable Gate Array. HB LNA High-Bandwidth LNA. HPF High-Pass Filter. IA Instrumentation Amplifier. IBL Impedance Boosting Loop. IC Integrated Circuit. IIR Infinite-Impulse-Response. IRN Input-referred Noise. LFP Local Field Potentials. LMS Least Mean Square. LNA Low-Noise Amplifier. LSB Least Significant Bit. LUT Look-Up Table. MSB Most Significant Bit. NEB Noise Equivalent Bandwidth. NEF Noise Efficiency Factor. NLMS Normalized Least Mean Square. OS ADC Oversampled ADC. ACRONYMS xix OSR Oversampling Ratio. OTA Operational Transconductance Amplifier. PBS Phosphate Buffered Saline. PGA Programmable Gain Amplifier. PR Pseudoresistors. PSD Power Spectral Density. PSRR Power Supply Rejection Ratio. SAR Successive Approximation Register. SC Switched-capacitor. SNR Signal-to-Noise Ratio. TDD Time-Division Demultiplexing. TDM Time-Division Multiplexing. THD Total Harmonic Distortion. VCO Voltage-Controlled Oscillator. VS Voltage-Sampling. WIS Windowed Integration Sampling. RESUMEN La neurociencia encargada de investigar sobre cómo se implementan las funciones cerebrales complejas a nivel celular requiere de interfaces de captación neuronal in vivo, incluyendo electrodos y circuitos de adquisición de señal con la mayor capacidad de observación y mayor resolución espacial. La tendencia de los dispositivos de captación de señal neuronal a emplear sondas de gran número de canales o mallas 2D con puntos de medición densamente espaciados para registrar grandes poblaciones neuronales dificulta el ahorro de recursos. Las especificaciones de bajo ruido y bajo consumo de la interfaz de registro del front-end analógico suelen requerir una gran ocupación de silicio, lo que hace que el problema sea aún más difícil. Un enfoque común para aliviar esta carga de consumo de área se basa en las técnicas de multiplexación por división de tiempo en las que la electrónica de lectura se comparte, parcial o totalmente, entre los canales preservando la resolución espacial y temporal de las grabaciones. En este enfoque, los elementos compartidos tienen que operar en un intervalo de tiempo más corto por canal, y la ocupación del área se reduce a cambio de mayores frecuencias de funcionamiento y anchos de banda. Como resultado, el consumo de energía sólo se ve ligeramente afectado, aunque otras métricas de rendimiento como el ruido en banda, el crosstalk o el CMRR pueden verse degradadas, especialmente si todo el circuito de lectura está multiplexado en la interfaz del electrodo. Además, estas interfaces de registro neural suelen emplearse en dispositivos neurales de bucle cerrado que también incluyen circuitos de estimulación. Las grandes interferencias, o artefactos, evocadas por la estimulación hacen necesario el desarrollo de técnicas y arquitecturas que garanticen que el sistema de detección es capaz de registrar la señal neuronal de interés en presencia de estos artefactos. En esta tesis se revisan, en primer lugar, las diferentes alternativas de implementación reportadas para los sistemas de captación neuronal multiplexados en el tiempo, incluyendo técnicas de detección de artefactos, se analizan sus ventajas e inconvenientes y se sugieren estrategias para mejorar el rendimiento. A continuación, basándose en la revisión presentada, esta tesis presenta un front-end de señal mixta de alto rango dinámico, baja potencia y bajo ruido para la adquisición de potenciales de campo locales o señales electroencefalográficas con implantes neuronales invasivos. El sistema incorpora multiplexación temporal de 32 canales en la interfaz del electrodo para ahorrar superficie y xxi 1. INTRODUCTION Table 1.1 summarizes the main characteristics of neural recording techniques and the acquired neural signals [ 25 ].It is worth observing how lowfrequency signals present a Power Spectral Density (PSD) similar to 1/f. This spectral distribution has been exploited by data compression algorithms [ 32 ] and by low-noise design processes [33]. Table 1.1: Neural Recording Techniques Comparison EEG ECoG Intracortical LFP AP Bandwidth 0.5-50Hz 0.5-500Hz 0.5-500Hz 0.5-10kHz Amplitude 1-10µV 1-100µV 0.01-1mV 0.01-1mV PSD 1/f 1/f 1/f Constant Spatial resolution 3-5cm 0.2-10mm 0.1-1mm 0.1-1mm Invasive No High Highest Highest Neural damage No No Yes Yes Area coverage Whole Brain ∼cm2, whole brain ∼mm2∼mm2 1.2 Thesis Contributions This work provides two main contributions to the field of neuroscience, related to implantable neural recording microsystems. Firstly, a complete review of multi-channel neural recording interfaces is presented. This review not only includes neural front-ends but also contains considerations related to the electrode interface and its integration along with the Analog Front-End (AFE). Analyses have been also provided in order to evaluate the impactof these techniques on the overallperformance of the sensor. Neural sensing architectures have been reviewed and classified together with the new trends in the design of neural recording devices, specially intended for area and power saving. An exhaustive state-of-art comparison including more than 50 high-performance neural front-ends is provided to ease the evaluation of each different architecture. Time-division multiplexing has been studied due to its promising results in terms of area and power saving over the last years. A classification of recording structures regarding the location of the multiplexer in the signal path is introduced along with the advantages and disadvantages of applying this technique at the electrode interface. The presence of large interference signals in bidirectional interfaces has been addressed through the examination of different techniques and architectures. The presented artifact-aware front-ends offer promising solutions to overcome this issue for differential and common-mode artifacts. This study of neural recording techniques has led to the design of a 32- channel low-noise, high-dynamic range recording front-end, which constitutes 4 1.3. Thesis Outline the second main contribution of this thesis. This CMOS prototype intended for LFPs or ECoG recording is based on a novel alternative to overcome the noise issues regarding time-division multiplexing architectures. A new low computational cost artifact-aware technique is proposed to largely increase the dynamic range of the system, which makes this design suitable forits integration in a low-power bidirectional interface. Finally, a compression technique that relies on the spatial correlation of the neural signal is also employed to reduce the input range and the raw data to process and transmit. The prototype has been in-vitro verified providing state-of-art specifications, specially interesting in terms of input-referred noise and dynamic range. 1.3 Thesis Outline This thesis is structured as follows: • Chapter 2 presents the design considerations of multi-channel neural recording interfaces along with a brief review of high-performance neural recording architectures. Furthermore, an exhaustive state-of-art revision of neural front-ends is also provided at the end of this Chapter. • Chapter 3 introduces the problem related to the large interference signals evoked by stimulation in bidirectional interfaces and disclosed some of the most significant reported artifact-aware techniques and architectures. • Chapter4 reviews the main advantages and drawbacks of the time-division multiplexing technique in neural recording front-ends. Moreover, a classification of the different architectures depending on the location of the multiplexer along with a state-of-art comparison is provided. Finally, the benefits and disadvantages of multiplexing at the electrode interface have been analyzed. • Chapter 5 presents a 32-channel low-noise CMOS prototype of a neural recording front-end. Detailed design analyses, specially those regarding the noise contribution have been also included in this Chapter. • Chapter 6 shows the experimental results of the prototype presented in the previous chapter. Herein, the Integrated Circuit (IC) is firstly electrically characterized and, then, verified by in vitro measurements. A brief discussion about the obtained results during this work is addressed at the end of this Chapter. • Finally, Chapter 7 presents the conclusions of this work and highlights the contributions of this thesis. Future research works are also disclosed. While the first 4 Chapters mainly constitute an exhaustive review of the reported multi-channel artifact-aware neural recording devices, Chapters 5 and 6 5 1. INTRODUCTION present and verify a CMOS prototype of a low-power artifact-aware implantable neural recording microsystem intended for low-amplitude low-frequency signals acquisition whose major applications are related to brain-machine interfaces. 6 CHAPTER 2 MULTI-CHANNEL NEURAL RECORDING INTERFACES C losed-loop neural prostheses have largely proven their effectiveness in treating brain disorders [ 19 , 20 ] and in their application in BMIs [ 23 , 21 ]. To develop such therapies and devices, the spatial resolution of neural recording interfaces needs to be increased. In recent years, therefore, and in line with the well-known Moore’s law for transistor count scaling in dense integrated circuits, we have seen gradual increases in the number of simultaneous recording channels incorporated into neural interfaces, either by penetrating probe shanks or through the use of surface 2D microelectrode meshes. The number of active sites in probe shanks, for example, has increased from about 100 in the most advanced systems available a decade ago to the approximately 3,000 simultaneously recorded channels reported nowadays. Similarly, the density of recording channels has risen from some 5-6channels/mm 2 to more than 80channels/mm 2 in the current state-of-the-art. Figure 2.1 illustrates how the number of simultaneously recorded neurons has largely incremented over the years [3]. Figure 2.2 shows the most commonly used electrodes in multi-channel neural recording devices: i) Utah intracortical electrode array [ 4 , 34 ] (Figure 2.2 (a)); ii) parallel microwire arrays [ 5 ] (Figure 2.2 (b)); and iii) probes on silicon [ 35 , 6 ] (Figure 2.2 (c)). While the Utah intracortical electrode array and the microwire arrays are able to capture the information from various neurons in a specific region of the brain, the probes on silicon are usually employed to record the activity in a specific spot. In these electrodes, the base houses the main CMOS signal conditioning circuitry and the shank is mainly made up of pixels and the interconnecting wires between the pixels and the base. These pixels 7 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES 1990 1995 2000 2005 2010 2015 2020 Publication Year 100 101 102 103 104 Fitting Curve (N=108): exp(0.133 · Year + Q) Simultaneously Recorded Neurons Q=2.33± 2.11 Figure 2.1: Number of simultaneously recorded neurons over the years [3]. are the minimum recording unit in neural probes and comprise electrodes and interconnection wires. They may also include active devices such as switches or amplifiers. The conventional multi-channel neural sensor interface is shown in Figure 2.3. The M -channel electrode array is connected by the interconnection wires to the neural recording IC. It is worth commenting that other main blocks of the neural recording IC, such as the power management, are not included in the Figure. In this architecture, each electrode is recorded by an independent AFE, which amplifies, filters and converts to the digital domain the neurological signals. The AFE usually comprises a Low Noise Amplifier (LNA), also known as Instrumentation Amplifier (IA), which generally embeds a bandpass filter, a Programmable Gain Amplifier (PGA) which maximize the output swing of the analog signal and an Analog-to-Digital Converter (ADC). Then, the data from the M parallel readout channels is serialized, digitally processed and wirelessly transmitted to an external unit. In the case of standalone closed-loop systems, this wireless transmission is not required and the processed data is directly transmitted to the stimulator. 2.1 Considerations for multi-channel Neural Recording Systems Implantable devices for neural sensing have to satisfy some design constraints from the point of view of medical safety and to ensure the longevity of the implant. Firstly, the system will function inside the human body, therefore 8 2.1. Considerations for multi-channel Neural Recording Systems (a) (b) (c) Figure 2.2: Electrode devices for multi-channel neural recording systems. (a) Utah intracortical electrode array [ 4 ]. (b) Example of microwire array-based device [ 5 ]. (c) Example of probe on silicon [6]. the used materials must be biocompatible [ 36 ]. The form factor of the device has to be minimized to avoid producing perturbations in the body where it is placed and it can not increase the temperature above 1 º C to not damage the neural tissue [ 37 ]. This point is directly related to the power consumption of the system. Finally, the recorded data has to be sent to the external processing unit by wireless transmission to avoid employing wires across the skull and the brain surface. The electrodes, in addition to be biocompatible, have to be minimized to maximize the spatial resolution of the implant, which leads to an increment in the number of sensing channels. However, the impedance of each electrode ( Ze ), which also depends on the electrode material and the environment where the electrodes are allocated, is inversely proportional to the area of the electrode. For instance, for intracortical electrode arrays, the electrode impedance at low frequencies can reach up to tens of M Ω [ 17 ]. Herein, the thermal noise contri- 9 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES Ch #M LNA PGA ADC Wireless Tx Electrode Array Digital Processing Ch #2 Ch #1 Interconn. wires Neural Recording IC AFE Parallel to Serial Figure 2.3: Conventional multi-channel neural recording sensor interface. bution of the electrodes which is proportional to their impedance, can strongly degrade the noise performance of the system. This establishes a trade-off between noise and area when selecting/designing the electrode interface. Due to the low magnitude of the neural signals, the recording front-end plus the noise contribution of the electrodes have to provide an Input-referred Noise (IRN) below 10 µVr ms to obtain high enough Signal-to-Noise Ratio (SNR) to properly record and process the neural activity. The demanded SNR will depend on the specific application of the neural device. Increasing the number of sensing channels while maintaining the size of the electrode interface could involve a smaller gap between the interconnection wires, increasing the crosstalk between channels. This turns the electrical crosstalk into one of the most significant scaling limitations of multi-channel recording devices. For neural applications, the crosstalk level has to be below 1% of the recorded signal level to make it negligible compared with the background noise [6]. Neural front-ends present design constraints which are related to the electrodes properties, characteristics of the neural signals, multi-channel scaling limits and the aforementioned implantable device needs. In terms of the electrode properties, to avoid signal attenuation of more than the 10%, the input impedance of the AFE has to be at least 50 times larger than the electrode impedance [ 38 ]. This results in an input impedance requirement of about hundreds of M Ω . Moreover, electrodes also present mismatch problems regarding to the fabrication non-idealities. This increases the effect of large Common- Mode (CM) interferences at the input of the system, demanding of a high Common-mode Rejection Ratio (CMRR) to palliate this problem. Additionally, an offset rejection mechanism is required to avoid the saturation of the signal path due to the DC offset of tens of mV evoked by the contact between the electrode and the tissue [39]. Low power is one of the main features of neural recording devices because of: i) the need to avoid feeding the implant with large batteries, demanding energy harvesting schemes or large coils in wireless inductive links; ii) avoid increasing the brain tissue heating. In this regard, scaling the number of channels could compromise the miniaturization, security and longevity of the implant, making the power consumption one of the most critical specifications of the front-end. 10 2.2. Electrode-AFE interface In high-channel recording devices, the number of simultaneous recording electrodes is restricted by the interconnection wires, the size of the active silicon area, and the number of parallel read-out channels. The form factor requirement of employed AFE, demands silicon areas of less than 0.16 mm 2 per channel because an inter-electrode spacing of 400- µ m provided a large enough spatial resolution [ 40 ]. Additionally, increasing the number of readout channels also scales the amount of raw data to be processed and transmitted, which can create a bottleneck on the recording interfaces and significantly increase the dynamic power consumption of the digital part [ 32 ]. Herein, compression algorithms have to be implemented to counteract this problem. Finally, neural recording systems have to be able to handle large interferences, or artifacts, from dozens to hundreds of mV. This has special relevance for artifacts produced by stimulation current pulses in closed-loop interfaces [ 13 , 41 ]. This increases the requirement of the input differential range that the system is able to tolerate without saturating the signal path (as detailed in Chapter 3). Stimulation artifact evokes a response of the brain (for instance, m-waves [ 42 ]) reaching up to a few of mV. This demands a larger dynamic range of the system. Table 2.1 summarises the main requirements of multi-channel neural recording AFEs. Some of these needs can be relaxed regarding the employed electrode interface, the specifications of the complete recording device and the specific application of the system. The designer has to take into account the tradeoffs between all presented specifications to meet all the design considerations without penalizing each other. Table 2.1: Required Specifications for Multi-Channel Neural Recording AFEs AFE specifications Required value Imposing constraint Input impedance >50·ZeElectrode impedance CMRR >60 dB Electrode mismatch and CM interferences DC offset rejection >50 mV DC offset from the electrodes Low-noise <10 µVr ms Neural signal amplitude Bandwidth 0.5-200/500 Hz for LFP 300-5/10 kHz for AP Neural signal frequency Power consumption per channel <10 µW Reduce power supply circuitry and heating Area per channel <0.16 mm2Number recording channels Maximum tolerable input signal >20 mVpp Large interference signals Dynamic range >60 dB Evoked signal from stimulation 2.2 Electrode-AFE interface AFEs in multi-channel systems are usually placed relatively far from the recording electrodes. The interconnection wires between the electrode array and the AFEs severely limit the electrode density and reduce the efficiency of the device’s area occupation. However, some silicon-based devices make it possible 11 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES to integrate one or more AFE stages along with the electrodes. The most suitable stage to be integrated adjacent to the electrodes is the IA. Therefore, the main advantages and disadvantages of employing or not this active circuitry along with the electrode have to be considered. These effects can be disclosed in its impact on the electrode crosstalk and its noise contribution to the system. 2.2.1 Crosstalk in Electrode-AFE Interfaces The electrode crosstalk can be defined as the crosstalk from the electrode interface (including the active circuitry) to the input of the AFE. (a) (b) Cpass Rmet Camp RsZe RsZe Cmet Vin Cpass Rmet Camp Vout,2 Vout,1 Cpass Rmet Cpga Ze Cmet Cpass Rmet Cpga Vout,2 Vout,1 Zin Rs Av Rout Ze Zin Rs Av Rout Vin Figure 2.4: Equivalent circuit model for electrode crosstalk analysis (a) without active electrode-AFE interface. (b) with active electrode-AFE interface. In multi-channel neural sensing devices, the space between adjacent electrodes and between interconnection wires is largely reduced while the dielectric layers below and above the electrodes remain constant. The coupling capacitance between electrodes thus increases because of the reduced space, thereby increasing the electrical crosstalk. A simplified scheme modeling crosstalk from electrodes to the AFE was proposed in [ 6 ] and further developed in [ 43 , 44 ] (see Figure 2.4 (a)). It should be noted that [ 44 ] also shown that the switches placed at the electrode interface have a negligible effect on crosstalk, so this was not included in the model. For the AFE to be integrated within the neural 12 2.2. Electrode-AFE interface probe, the capacitive coupling between metal lines in the external wire [ 43 ] was also excluded. To further develop this approach, Figure 2.4 (b) shows a model including an amplifier adjacent to the electrodes, similar to [ 45 ]. The employed circuit elements with their corresponding values used to simulate the model (taken from [44, 43]) are described as follows: •Rs is the spreading resistance encountered by the current propagating out into the fluid near to the electrode. It has been reported to be about 10 kΩ[43]. •Ze represents the equivalent impedance of the electrode. This impedance is a frequency-dependent parameter because it is formed by a resistance in parallel with a capacitor. For the analysis purpose, which was carried out for a 1 kHz sine wave input signal, the value of Ze has been set to 2 MΩ, corresponding to a 20 µm diameter Pt electrode. •Cmet describes the capacitive coupling between adjacent lines. It was estimated as 0.3 pF. •Cpass is the estimated capacitance of the metal lines with the extracellular fluid. This value was set as 0.6 pF. •Rmet represents the equivalent resistance between the metal traces to the amplifier (PGA, in the case of the active electrode-AFE interface) input. Its value was about 180 Ω. •Camp (only for non-active electrode-AFE interfaces) models the input capacitance of the AFE and was set at about 10 pF. •Cpg a (only for active electrode-AFE interfaces) represents the input capacitance of the PGA and was taken as about 10 pF. •Zin (only for active electrode-AFE interfaces) is the input impedance of the IA. It was selected to be above 70 MΩ. •Rout (only for active electrode-AFE interfaces) describes the output resistance of the amplifier next to the electrode. This value was set as 50 kΩ. Crosstalk simulations, where crosstalk was defined as Vout,2 / Vin , were carried out in standard CMOS 0.18 µ m technology (Figure 2.5). Figure 2.5 (a) represents electrode crosstalk against electrode impedance. It can be observed how while in the active configuration crosstalk remained constant, for the passive electrode-AFE model it largely increases with the electrode impedance. For impedances above 6 M Ω , the electrical crosstalk theoretically surpasses the background noise of the recorded signals, significantly reducing the SNR. This imposed a severe constraint in terms of the size and the material of the electrodes. For the active electrode-interface scheme, crosstalk is affected by the 13 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES Table 2.2: High-Performance Neural Front-End Comparison. Continuous-Time Chopper-stabilized Chopper-∆ ∆ Σ VCO - ∆ Σ Input impedance 1 2πCin f 1 2πCin fch ∗1 2πCin fch 1 2πCpf 1 2πCin f Main noise contributor Flicker Thermal Thermal Flicker / Thermal Flicker High-pass Filter Embedded within the IA Analog/Digital DSL ∆-modulation ∆-modulation ∆-modulation Pros High and accurate gain Input impedance Flicker reduction Flicker reduction Area and power saving Input impedance DC offset removal Area and power saving Input impedance DC offset removal Area and power saving Cons Flicker contribution Area Dynamic range Input impedance Limited DC offset removal Input impedance Flicker contribution Linearity Flicker contribution ∗Without IBL. 20 2.3. Neural Recording Front-ends 2.3.1 State-of-art Comparison A state-of-art comparison of the employed LNA topologies is shown in Figure 2.9 and 2.10. Herein, Figure 2.9 (a) illustrates the Noise Efficiency Factor (NEF) against the area per channel. Note that the green-red scale of the symbols shown indicates the IRN value of each reported scheme, the green ones being the lowest IRN values and the red ones the highest IRN values. In Figure 2.9 (b), all the front-ends presented in Section 2.3 are denoted as digitally-assisted except for those shown in Figure 2.8 (a). It can be seen how chopper-stabilized LNAs offer the lowest IRN at the cost of increasing the area per channel. Proposed solutions based on ∆ Σ AFEs and mixed-signal feedback offer some of the best performances in terms of noise and area per channel. Figure 2.10 (b) compares the LNA supply current with the normalized IRN. In this comparison, CT LNAs show better results than digitally-assisted front-ends, due to their employment of low-power analog blocks instead of complex mixed-signal loops. Moreover, CT LNAs usually present higher bandwidths than digitally-assisted front-ends, especially those using the chopper-stabilization technique requiring high chopper frequencies. Finally, Tables 2.3 and 2.4 summarises the state-of-art of neural recording AFEs. In these tables, the main specifications of the reported front-ends are compared in order to provide a clear view of the evolution of these devices over the years and the pros and cons of the presented architectures. It is significant to point out some considerations about the tables: i) most of the ac coupled / dc coupled topologies are CT topologies. ii) MS loop refers to mixed-signal loop. iii) CTSD represents continuous-time sigma-delta topologies. iv) Mux structures define Time-Division Multiplexing (TDM) AFEs (detailed in Section 4.3). 21 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES 10-2 10-1 100 0 1 2 3 4 5 6 7 8 9 10 CT Low Noise Amplifiers Area per channel (mm2) NEF [Harr'03] [Goss'07] [Watt'11] [Liew'09] [Liew'11] [Maji'11] [Rai'09] [Zhan'12] [Yin'13] [Shah'10] [Shoa'14] [Qian'11] [Han'13] [Rodr'13] [Zou'13] [Shul'15] [Bied'15] [Kuhl'15] [Wang'15] [Harp'15] [Lope'14] [Lee'17] [Ng'16] [Chen'14] [Yang'15] [Park'17] [Park'18] [Liu'17] [Shen'18] [Lee'17] [Lee'18] [Kim'14] 10-3 10-2 10-1 100 0 1 2 3 4 5 6 7 8 9 10 Digitally-Assisted Front-Ends Area per channel (mm2) NEF TDM AFE [Mull'12] [Yaul'17] [Chen'14] [Fan'11] [Alta'15] [Yazi'08] [Xu'15] [Xu-B'14] [Chen'15] [Deni'07] [Verm'10] [Chan-A1'17] [Chan-A2'17] [Chan-B1'17] [Chan-B2'17] [Bagh'17] [Kass'17] [Yang'16] [Mull'15] [Mond'20] [Jian'19] [Ha'16] [Mond'17] [Kim'18] [O'Lea'18] [Luo'19] [Uehl'20] [Huan'18] [Tu-A'17] [Zhao'20] IRN > 8 Vrms 6 Vrms < IRN < 8 Vrms 5 Vrms < IRN < 6 Vrms 4 Vrms < IRN < 5 Vrms 3 Vrms < IRN < 4 Vrms IRN < 2 Vrms 2 Vrms < IRN < 3 Vrms Chopper Stabilization ΔΣ AFE or Mixed-Signal Feedback Time/Frequency based AFE Combination + Continuous-Time LNA (a) (b) Figure 2.9: LNA’s state-of-art NEF vs area per channel comparison.(a) CT LNAs. (b) Digitally-Assisted Front-ends. 22 2.3. Neural Recording Front-ends 10-3 10-2 10-1 100 Area per channel (mm2) 10-2 10-1 100 101 102 103 Channel FoM (pJ/C-s) 1 fJ/C-s mm 2 10 fJ/C-s mm 2 100 fJ/C-s mm 2 1 pJ/C-s mm 2 10 pJ/C-s mm 2 10-8 10-7 Input referred noise/sqrt(BW) (µVrms/sqrt(Hz)) 100 101 102 Supply Current (µA) NEF = 1 NEF = 3 NEF = 10 NEF = 40 Area > 0.5mm2 0.4mm2< Area < 0.5mm2 0.3mm2< Area < 0.4mm2 0.2mm2< Area < 0.3mm2 0.1mm2< Area < 0.2mm2 Area < 0.01mm2 0.01mm2< Area < 0.1mm2 IRN > 8 Vrms < IRN < 8 Vrms 5 Vrms < IRN < 6 Vrms 4 Vrms < IRN < 5 Vrms 3 Vrms < IRN < 4 Vrms IRN < 2 Vrms 2 Vrms < IRN < 3 Vrms (a) (b) 6 Vrms Chopper Stabilization ΔΣ AFE or Mixed-Signal Feedback Time/Frequency based AFE Combination + Continuous-Time LNA Figure 2.10: LNA’s state-of-art (a) channel FoM vs area per channel comparison. (b) supply current vs normalized IRN comparison. 23 2. MULTI-CHANNEL NEURAL RECORDING INTERFACES Table 2.3: State-of-art of Neural AFEs (1). Reference Year Topology Process (µm) Application Gain (dB) Bandwidth (Hz) Noise floor nV/(Hz)1/2 IRN (µVr ms)Power (µW) Supply (V) Dynamic range (THD <1%) (dB) NEF / PEF Input range (mV) THD 1% (mVpp) CMRR (dB) / PSRR (dB) DC offset rejection (mv) Area (mm-sq) Input impedance @ 1Khz (MΩ) [50] 2003 ac coupled 1.5 LFP-AP 39.5 0.025-7.2k 21 2.2 80 5 69 4 / 80 - 16.7 83 / 85 full 0.16 7.96 [65] 2004 dc coupled 1.5 LFP-AP 39.3 0-9.1k - 7.8 114.8 3 47.1 19.4 / 1129.08 -15 - 15 5 - / - 50 0.107 [66] 2007 CT dc coupled 0.18 AP 49.52 98.4-9.1k 55 5.6 8.4 1.8 45 4.9 / 43.2 - 2.4 52.68 / 51.93 450 0.05 NA [67] 2011 ac coupled 0.18 LFP-AP 49-66 350-11.7k - 5.4 16.6 1.8 - 5.9 / 62.65 - - 62 / 72 full 0.03 [68] 2009 ac coupled 0.35 LFP-AP 45.7-60.5 217-7.8k - 4.43 1.26 1 - 2.16 / 4.67 - 0.53 (full swing) 58 / 40 full 0.25 [69] 2011 ac coupled 0.13 AP 48-54 40-7.5k - 5.32 0.86 0.5 - 3.09 / 4.77 - - - / - full 0.059 [70] 2011 ac coupled 0.18 AP 39.4 10-7.2k - 3.5 7.92 1.8 58.4 3.35 / 20.2 - 5.7 70.1 / 63.8 full 0.0625 7.96 [71] 2009 ac coupled 0.13 LFP-AP 38.3 23m-11.5k - 2.2 12.5 1 - 2.48 / 6.15 - 1 63 / 63 full 0.26 [72] 2012 ac coupled 0.13 LFP-AP 40 50m-10.5k - 2.2 12.1 1 - 2.9 / 8.41 4 1 80 / 80 full 0.072 4 [73] 2013 ac coupled 0.6 LFP-AP 46 1-7.8k - 2.83 60 3 - 3.3 / 32.67 - - 50 / 60 full 0.25 [74] 2010 ac coupled 0.35 LFP-AP 33 0.5-10k - 6.08 8.4 3 - 5.55 / 92.40 - - 60 / - full 0.02 35.39 [75] 2014 ac coupled 0.18 AP 29.8 28-144k - 4.2 8.4 1.2 - 4.12 / 20.37 - 2 (0.24% THD) 59.8 / - full 0.04 [76] 2011 ac coupled 0.6 Fast-ripples 39.4 0.36-1.3K 60 3.07 2.4 2.8 54 3.09 / 26.73 - 10 66 / 80 full 0.13 [77] 2013 ac coupled 0.18 LFP-AP 49 0.25-(2.5-10)k 29 3.2 0.73 0.45 56 1.57 / 1.12 - 2.8 (0.53% THD) 73 / 80 full 0.16 [78] 2013 ac coupled 0.18 LFP-AP 54.8-60.9 0.38-5.1k 40 4 0.81 1 - 1.9 / 5.6 - 0.9 60 / 70 full 0.04 7.96 [79] 2015 ac coupled 0.35 LFP-AP 32 0.1-10 to 500-10k - 7.99 12.9 3 - 8.9 / 237.6 - 1 (0.8% THD) 60 / - full 0.035 [80] 2015 ac coupled 0.065 LFP-AP 26 10-1k to 3k-8k - 7.5 1.2 1 - 3.6 / 12.9 - - - / - full 0.0258 [81] 2015 ac coupled 0.18 AP 26 140-20k 60 11.9 14.76 1.8 - 6.1 / 67 - 11 59.2 / 53.5 full 0.0098 [82] 2015 ac coupled 0.35 LFP-AP 40.3 0.01-10k - 2.81 9 2.5 63.7 2.05 / 10.50 3 4.3 (0.1%) 82 / 82 full 0.12 [83] 2015 ac coupled 0.065 ECG 32 1.5-370 1400 26 0.0015 0.6 - 2.1 / 2.64 - - 60 / 63 full 0.12 [45] 2014 ac coupled 0.18 AP 30-72 300-6k - 3.2 7.02 1.8 - 3.08 / 17.13 - 18 60 / 76 full 0.092 [84] 2012 dc coupled MS loop 0.065 AP 32 300-10k 48 4.9 4.79 0.5 - 5.99 / 17.96 - 0.1 (2%) 75 / 64 20 0.013 1000 [25] 2015 chopper 0.065 ECoG. LFP 30 1-400 58 1.25 2.3 0.5 - 4.76 / 11.3 - 1 (0.4%) 88 / 67 50 0.025 28 [85] 2017 CT dc coupled 0.13 AP 44 20-15k - 3 11 1 - 2.95 / 8.68 2.2 1 (0.8%) - / 41 -200 - 100 0.12 61 [86] 2016 ac coupled 0.065 LFP-AP 52.1 1-8.2k - 4.13 3.28 1 - 3.19 / 10.2 220 1.4 90 / 78 full 0.042 21 [9] 2014 ac-coupled 0.18 AP 54.2 0.0-5.7k - 3.83 2.52 1 66 3.09 / 9.72 - 1.54 (0.2%) 65 / 67 - 0.109 NA [87] 2017 chopper 0.18 LFP 57.8 0.0-670 36 0.94 0.79 0.2/0.8 - 2.1 / 1.6 2.1 1.6 (0.33%) 85 / 74 NA 0.32 100 [52] 2011 chopper 0.065 LFP 40 0.5-500 60 6.7 1.8 1 - 3.3 / 10.89 - - 134 / 120 NA 0.1 30 [88] 2015 chopper 0.18 EEG. LFP 40 0.07-1k 0.9 1.62 1.8 - 3.29 / 19.49 - - 97 / - 240 0.6 >500 [89] 2008 chopper 0.18 EEG. LFP 46 0.5-315/675 55 0.59 6.9 3 - 4.1 / 50.43 45 1.65 120 / 89 45 0.45 1000@1Hz [90] 2015 (dc) chopper 0.18 EEG. LFP 36.9 0.5-100 60 0.65 13.32 1.8 - 6.8 / 83.23 0.5-1.2 - 102 / - 350 0.58 1000@1Hz [91] 2018 chopper 0.04 EEG. LFP 30 2-150 145 1.85 3.8 0.6 - 14.71 / 129.83 400 - 87 / - 300 0.16 140.00 [92] 2015 chopper 0.065 LFP 51-96 0.5-250 253 6.52 0.017 0.6 48.6 2.64 / 4.18 - 0.5 (2.87%) 55 / 67 - 0.81 110.00 [93] 2007 chopper 0.8 LFP 50.5 0.05-120 100 1.1 2 1.8 - 4.6 / 38.1 - 5 (0.1%) 100 / - 50 0.8 8 [94] 2010 chopper 0.18 LFP 36 0.1-100 130 1.3 3.5 1 - 9.37 / 87.7969 - - 60 / - 1000 0.3 700 24 2.3. Neural Recording Front-ends Table 2.4: State-of-art of Neural AFEs (2). Reference Year Topology Process (µm) Application Gain (dB) Bandwidth (Hz) Noise floor nV/(Hz)1/2 IRN (µVr ms)Power (µW) Supply (V) Dynamic range (THD <1%) (dB) NEF / PEF Input range (mV) THD 1% (mVpp) CMRR (dB) / PSRR (dB) DC offset rejection (mv) Area (mm-sq) Input impedance @ 1Khz (MΩ) [47] 2017 chopper 0.04 LFP 25.7 0.12-5k 80 1.8 2.8 1.2 81 7.4 / 65.71 40 40 (-76dB THD) 78 / 76 650 0.069 1600 [95] 2017 chopper 0.04 LFP-AP 25.7 0.12-5k 80 5.3 2.8 1.2 74 4.4 / 23.23 40 40 (-76dB THD) 78 / 76 650 0.069 1600 [39] 2018 chopper + CTSD 0.04 LFP - 1-200 - 2.9 4.5 1.2 108.4 15.3 / 280.9 - (102.5 SFDR) 81.2 / - - 0.053 20 [96] 2015 ac-coupled 0.09 LFP-AP 58.7 0.49-10.5k - 3.04 2.85 1 1.93 / 3.72 - 1(1.6%) 50 / 45 - 0.137 - [97] 2017 chopper 0.13 LFP-AP 50.7-54 1-5k - 5 9.9 1.2 - 7 / 58.8 50 1 65 / - 50 0.018 1000 [57] 2017 Sigma-Delta 0.13 LFP - 0.01-500 - 1.13 0.63 1.2 - 2.86 / 9.81 - - 90 / 95 rail-to-rail 0.013 1 [98] 2016 chopper 0.13 AP 45-71 1-7k 34 2.93 5.9 1.2 - 3 / 10.8 - 1 95 / - - 0.4 100 [99] 2020 chopper 0.18 ECoG. LFP 36 0.1-240 158 2.84 0.0187 1.35 - 0.86 / 0.99 - 1000(-57dB THD) 95 / 68 - 0.24 87 [32] 2018 ac-coupled 0.18 LFP-AP 38.5 0.4-10.9k - 3.32 3.05 0.5 - 3.02 / 4.56 - 3(74SFDR) 60 / - - 0.058 20 [100] 2019 chopper + CTSD 0.18 LFP 40 0-1k 3.7 0.12 2160 1.8 - 5 / 44 10 - 134 / 100 0.73 1 [101] 2014 ac-coupled 0.18 LFP-AP 60 1-6.8k - 5.4 0.88 0.5 - 3.34 / 5.57 - - - / - - 0.16 - [102] 2018 Sigma-Delta 0.065 LFP 5.95 1-500 44 0.99 0.8 0.8 92 1.81 / 2.62 - - 81 / - 260 0.024 26 [103] 2018 Sigma-Delta 0.13 LFP - 0.01-1k - 1.6 1.26 1.2 70 2.86 / 9.8 rail-ro-rail - - / - rail-ro-rail 0.023 - [104] 2019 chopper 0.18 LFP 40 0.35-5.4k 39 0.65 3.24 1.8 - 2.37 / 10.11 - 5 (-61dB THD) 100 / - 50 0.2 440 [12] 2020 Mux Gm-C SAR 0.065 LFP 60 1-1k 80 2.78 2.98 2.5 96.27 2.35 / 13.80 110 - 76 / 82 - 0.0023 92 [105] 2018 ac-coupled 0.18 LFP-AP 25.6 4-10k - 5.6 0.25 1 - 1.07 / 1.14 Inf - 81 / 81 - 0.097 - [106] 2018 chopper + CTSD 0.18 LFP - 0-300 - 4.6 6.5 1 84.3 26.03 / 677.5 360 180 (104.7 SFDR) 84 / - - 0.55 39 [107] 2018 chopper 0.065 EEG. LFP 40 0.5-250 - 4.5 5.4 1.2 - 3.59 / 15.46 - - 110 / - 350 3.75 1000 [108] 2018 chopper T-ADC 0.065 LFP - 0.1-500 2.2 3.2 0.6 51 8.7 / 45.41 47 62dB SFDR 77 / 65 47 0.01 500 [60] 2017 VCO-ADC 0.04 LFP - 1-200 - 5.2 7 1.2 79 34.23 / 1406.0 50 - 66 / - 50 0.135 Inf [109] 2017 chopper T-ADC 0.04 LFP-AP - 0-5k 32 2.3 17 1.2 61.8 4.71 / 26.62 8 4 (70.8 THD) 97 / 91 - 0.0145 70 [110] 2017 chopper T-ADC 0.04 LFP - 1-150 600 7.8 3.3 0.6 56 57.61 / 1991.3 150 40 60 / - 50 0.015 50 [111] 2019 VCO-ADC 0.04 LFP - 1-250 100 2.2 8.2 1.2 81 14 / 235.2 100 - - / - 100 0.12 Inf [112] 2020 VCO-ADC 0.04 LFP-AP - 0-10k 36 3.58 4.68 0.8 79 3.33 / 8.87 100 (91dB SFDR) 83 / 80 100 0.025 - 25 CHAPTER 3 ARTIFACT-AWARE TECHNIQUES FOR ANALOGUE/MIXED-SIGNAL NEURAL FRONT-ENDS S ome of the most common applications for neural recording systems require the implementation of a closed-loop sensor/actuator mechanism to interact with the brain and, hence, neural recorders have to co-exist with stimulators, often integrated on the same silicon die. Neural stimulation typically induces strong reactions (artifacts) in the tissue [ 113 , 114 , 115 ]. These artifacts may last for tens of milliseconds and may reach up to tens of mVs and depend on the stimulator architecture and performance, the stimulation waveform and the electrode configuration. Further, the amplitude of the artifacts increases with the proximity between the stimulation and the recording electrodes and, hence, the problem is more acute in dense multi-electrode arrays if both operations, stimulation and recording, are jointly implemented in the probe (as illustrated in Figure 3.1). These interferences not only corrupt the captured neural signals but it may also lead to the saturation of the recording front-end. An example of the PSD of a contaminated recorded LFP by a stimulation artifact is shown in Figure 3.2 [ 7 ]. It is worth seeing from Figure 3.2 how the spectral components of the stimulation artifact overlap the information contained by the LFP signal. Hence, in these closed-loop devices, neural recording systems not only should exhibit low noise, low power and low area occupation [ 10 , 47 ] but they should also render tolerant to the large artifacts generated by the stimulation pulses. Together with neural stimulation, other large interfering signals may also contaminate recording, for instance, by sudden alterations of the tissue-electrode interface due to motions [ 47 ], [ 13 ]. As long as these interferences have a similar 27 3. ARTIFACT-AWARE TECHNIQUES FOR ANALOGUE/MIXED-SIGNAL NEURAL FRONT-ENDS effect on the recorded data as stimulation artifacts, in this work, we will regard both cases as artifacts and simply distinguish between CM and Differential- Mode (DM) artifacts, depending on the kind of perturbation received by the neural signal. Neural Recording AFE Control Unit Stimulator Closed-Loop Neural SystemTissue Neural Recording AFE Neural activity Evoked artifact Figure 3.1: Simultaneous stimulation and recording in a closed-loop neural system. Figure 3.2: LFP signal contaminated by the stimulation artifact [7]. Figure 3.3 illustrates the amplitude and frequency ranges of neural signals (only LFPs and APs are shown) as compared to CM and DM artifacts [ 47 ]. As can be seen, while frequencies overlap, amplitude differences may be orders of magnitude different. The use of fully-differential structures with large CMRR allows reducing the impact of CM artifacts. However, residual CM components in the differential signal path may still degrade system performance. To cope with this problem, CT [ 47 ] and Discrete-Time (DT) [ 11 , 12 ] solutions applied at the input of the recording front-end have been proposed. DM artifacts are typically smaller than CM artifacts, however, their effect is more deleterious because they superpose 28 3.1. DM Artifacts-Aware Techniques on the neural signal component which conveys useful information. DM artifacts could be handled by increasing the input dynamic range of the neural recorder and raising the resolution of the following ADC so as to convert both neural signals and artifacts. For example, the resolution of an DM intended for LFP recording should be increased from 10-12 bits to some 14-15 bits if artifacts have to be covered as well [ 14 ]. Obviously, this would significantly increase the area and power consumptions of the recording system and, for this reason, other artifact-aware front-end topologies have been recently proposed. In this work, we will make a brief review of these artifact-aware algorithms and structures and analyze their pros and cons. Frequency (Hz) Amplitude (V) 600m 100m 10m 1m 100µ 10µ 1µ 110 100 1k 10k Local Field Potentials Action Potentials Artifacts DM CM 80 dB 100 dB ECoG Figure 3.3: Specifications of recorded neural signals. 3.1 DM Artifacts-Aware Techniques Artifact-aware topologies are aimed to relax the performance requirements of the neural recording system in terms of input dynamic range and/or converter resolution even when artifacts contaminate neural signals [ 116 ]. Some of these topologies are analyzed below and illustrated in Figure 3.4. 3.1.1 Channel Blanking Figure 3.4 (a) illustrates the basic structure of the channel blanking technique [ 117 ]. The operation principle consists in disconnecting the recording channel from the tissue when an artifact is present. This disconnection has many alternatives: electrode disconnection, PGA isolation, high-pass pole shifting, etc. However, this only works when intentional stimulations are applied to the brain but it is useless for unpredictable interferers. Further, the technique carries out 29 3. ARTIFACT-AWARE TECHNIQUES FOR ANALOGUE/MIXED-SIGNAL NEURAL FRONT-ENDS Amp ADC DAC Artifact Learning algorithm Stimulation flag d(n) e(n) s(n) a(n) a(n) Residual Artifact Suppression Optional threshold s(n)Amp ADC a(n) d(n) Statistics calculation Off-line Training Template detection Adaptive filtering (NLMS) s(n) u(n) (a) (b) Figure 3.10: Artifacts-suppression techniques. (a) Artifacts suppression feedback frontends. (b) Post-processing artifacts suppression front ends. shortcoming, oversampling techniques can be used [ 25 ]. Furthermore, the clock of the circuit has to be fast enough to detect the artifact and inject the correction signal before the artifact saturates the signal path. Two of the most significant artifact suppression feedback techniques are the averaged template subtraction [124] and the adaptive stimulation filter [13]. In the first case, an artifact template is subtracted from the input of the recorder every time a new neural stimulation cycle turns on [ 124 ]. The template is calculated by means of a learning algorithm, based on recordings obtained from previous stimulation cycles. After template subtraction, a residual artifact waveform may persist in the signal path. To further enhance the artifact suppression, a post-processing digital circuit can be used to calculate the average amplitude of such residue and subtract it from the signal. One of the main drawbacks of this approach is the high computational complexity cost and the need for offline training required for both generating the templates and calculating the artifact residues. Further, if there are substantial differences between the artifact and the stored template, the resulting residue can eventually saturate the signal path, unless a wide input range amplifier is used. In the second case, an adaptive stimulation filter recreates the response of the neural tissue in order to subtract the artifact from the neural signal [ 13 ]. The approach takes advantage of the close correlation between the stimulation pulse, e ( t ), and the neural tissue response, b ( t ). Denoting by s ( t ) and a ( t ) the unaffected neural signal and the artifact, respectively, the recorded signal at instant ncan be expressed as: y(n)=s(n)+a(n)=s(n)+b(n)∗e(n) (3.1) 36 3.3. DM Artifacts-Suppression Techniques The objective is to generate a signal ˆ a ( n ) =ˆ b ( n ) ∗e ( n ) such that, when subtracted to the input, gives an estimate ˆ s(n)=y(n)−ˆ a(n)=s(n)+[b(n)−ˆ b(n)]∗e(n) (3.2) close to the original unaffected neural signal. The recreated response ˆ b ( n ) can be obtained through an adaptive filter where coefficients are updated by a Least Mean Square (LMS) learning algorithm [ 13 ]. This algorithm uses a steepest gradient descent approach to minimize errors in ˆ s ( n ). A simplified version of the LMS algorithm, the sign-sign LMS, facilitates hardware implementation by using a sign-bit signal representation as follows [125]: ˆ b(n)=ˆ b(n−1)+µ∗[e(n)×sgn(ˆ s(n))] (3.3) Finally, Figure 3.11 illustrates the performance of the mixed-signal technique [13]. When the stimulation occurs without enabling the feedback cancellation block, artifacts largely contaminate the signal of interest. On the other hand, by applying the proposed scheme the artifacts are reduced with an attenuation of up to 24 dB. Figure 3.11: Example of the performance of a mixed-signal adaptive stimulation cancellation technique [13]. 3.3.2 Post-Processing Artifacts Suppression Front-Ends In these structures, artifacts are suppressed in digital domain with no feedback to the recorder front-end (Figure 3.10 (b)). This avoids any degradation in the noise performance, although, it demands a high dynamic range for the mixed-signal circuitry. 37 3. ARTIFACT-AWARE TECHNIQUES FOR ANALOGUE/MIXED-SIGNAL NEURAL FRONT-ENDS Herein, we will briefly review the blind ASAR proposed in [ 14 ], as a representative example of post-processing cancellation. Interestingly enough, the approach works with any arbitrary artifact with no prior knowledge about its structural and temporal shape. It relies on obtaining an artifact template u ( n ) from an adjacent electrode. This template is detected when a threshold value, obtained from a previous statistics calculation phase in the absence of artifacts, is exceeded. If an artifact is detected in the recorded signal y ( n ), the template u ( n ) is applied to a Normalized Least Mean Square (NLMS) adaptive filter which updates the weighting factor, w(n), as follows: w(n)=w(n−1)+µ ||u(n)||2+²u(n)T[y(n)−u(n)w(n−1)] (3.4) where µ is the algorithm step-size and ² is a small positive parameter. To obtain a clean neural signal ˆ s ( n ), the estimated artifact is subtracted from the measured signal: ˆ s(n)=y(n)−u(n)w(n) (3.5) This approach obtains very fast convergence times and skips any modeling of the brain response in the presence ofartifacts [ 14 ]. The effect of this technique is illustrated in Figure 3.12. Herein, up to 37 dB of artifact attenuation is achieved by applying this proposed method. Figure 3.12: Example of the performance of the ASAR technique [14]. 38 CHAPTER 4 TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS A s aforementioned in Chapter 2, form factor and power consumption are two of the main concerns in multi-channel neural recording interfaces. A technique that copes with these issues is the TDM technique. In this method, the same AFE block, or blocks, is shared among all the recording channels. The number of shared stages is, thereby, defined by the location of the multiplexer in the signal path. The application of this technique at the electrode interface is a promising approach to further exploit the advantages of this method [ 126 , 17 , 18 , 11 , 12 ]. While in conventionally recording channels there is a one-to-one correspondence between electrodes and AFEs [ 47 , 95 , 103 , 127 ] (Figure 4.1 (a)), in input TDM recording systems a single AFE is shared among all electrodes (Figure 4.1 (b)). This technique clearly reduces the area occupation per channel, which roughly scales down with the number of multiplexed electrodes thus leading to a noticeable area saving in multi-channel devices [ 12 ], and, eliminates the mismatch problem of these interfaces [ 86 ]. Nevertheless, this approach demands of AFEs with much larger bandwidth which may produce a significant increase of the in-band noise due to aliasing. This issue has to be carefully addressed when designing multiplexed front-ends. 4.1 Time-Divison Multiplexing TDM is a widely employed technique in communication systems. The basic concept of TDM is illustrated in Figure 4.2: a clock-driven multiplexer converts M parallel input channels into a single output by splitting each input signal into 39 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS IA LPF PGA ADC IA LPF IA LPF PGA ADC IA PGA ADC MUX (a) (b) Figure 4.1: (a) Conventional neural recording front-ends for multiple channels. (b) Time-multiplexed neural recording front-end for multiple channels. different time slots while keeping the same throughput rate per channel. Then, a demultiplexer performs the inverse operation, Time-Division Demultiplexing (TDD). Thus, this technique works essentially the same as the serial-parallel registers. After multiplexing, the signal from the M channels is shared by the same AFE block/s, reducing the number of instances of each multiplexed block by M− 1. This results in area per channel saving, scaling with the number of multiplexed stages. When this technique is carried out in the analog domain by an analog multiplexer, the bandwidth of the subsequent block/s has to be at least M times larger than in non-multiplexed topologies, leaving the power consumption per channel about the same as in conventional architectures. MUX DEMUX s1(n) s2(n) sM(n) t s2(n+1) s3(n+M-1) s1s2sM s1(n) clk TDM Figure 4.2: Time-division multiplexing technique. This approach presents two major drawbacks: i) crosstalk in the analog multiplexer; ii) noise folding. Employing larger bandwidth blocks increases in-band noise, which will be folded into the baseband. Although anti-aliasing filters are used to deal with this spectral folding, if the multiplexer is located in one of the first stages of the AFE, this filter becomes more difficult to implement 40 4.1. Time-Divison Multiplexing and a different alternative has to be adopted. This problem is detailed in section 4.3. 4.1.1 Crosstalk in Time-Division Multiplexers Crosstalk in TDM architectures can be seen as a noise source at the input of the analog multiplexer. This crosstalkcan be disclosed in four different components: i) capacitive coupling between the input metal lines of the multiplexer; ii) the finite off-resistance of the switches; iii) time-adjacent channel crosstalk; iv) capacitive coupling through the parasitic capacitance of the transistor used as a switch. Firstly, the impact of the capacitive coupling can be avoided by applying layout techniques such as careful shielding of each input line. In the second case, the subthreshold conduction of the switches is negligible due to the large back-bias effect in low-voltage topologies. Thus, the off-resistance is in the order of hundreds of G Ω , avoiding the crosstalk between channels. The time-adjacent channel crosstalk reveals the multiplexer’s ability to charge/discharge the load capacitors during the active period of a channel. If the multiplexer response is slow, a residual charge will appear between two time-adjacent channels, resulting in crosstalk noise. The on-resistance of the switches should therefore be designed to be as small as possible, in order to suppress this crosstalk source. Therefore, the first three crosstalk sources mentioned above can be neglected by properly designing the multiplexer. The effect of the capacitive coupling through the parasitic capacitance of the transistor can have a real impact on the multiplexer output [ 128 ] and have to be analyzed. Figures 4.3 (a) and (b) present a transistor as a switch and its simplified model, respectively. In this model, Rst represents the state-resistance of the switch ( Ron and Ro f f for the on-state and off-state, correspondingly) and CEQ the equivalent parasitic capacitance of the switch (mainly comprising its drain-to-source capacitor and its drain-to-bulk and source-to-bulk capacitors). The crosstalk scheme for a M -channel multiplexer based on this simplified model is illustrated in Figure 4.3 (c). This model is developed to study the impact of the M− 1 turned-off channels at the multiplexer output while a single channel is enabled. In Figure 4.3 (c), Rost represents the output impedance of the stage feeding the multiplexer. In the case of multiplexing at the electrode interface, Rost will mainly comprise the spreading resistance, Rs , and the electrode impedance, Ze(Figure 4.3 (d)). The crosstalk in the multiplexer is now defined as the effect of the M− 1 turned-off channels at the output of the multiplexer Vout . Assuming Ro f f >> CEQ and Ron <<CEQ, this crosstalk, CrMU X , is given by: CrMU X (dB)=20log10 µRL Rost +ZEQm +RL¶(4.1) with: 41 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS Vin Vout VDriver CL Vin Vout Rst CEQ Vin,1 Rost Roff CEQ Vin,2 Rost Roff CEQ Vin,M-1 Rost CEQ Roff Rost CEQ Ron Vout (a) (b) (c) Active channel (d) Rost Ze Rs Figure 4.3: (a) MOSFET device as a switch. (b) Simplified equivalent circuit model for MOSFET as a switch. (c) Equivalent circuit model for crosstalk analysis of a M - channels multiplexer. (d) Equivalent impedance model for multiplexing at the electrode interface. RL=ZEQm(Ron +Rost ) ZEQm +Ron +Rost (4.2) ZEQm =1 (M−1) jωCEQ (4.3) ω being the frequency of the input signal. Simulations were conducted to demonstrate the effectiveness of the model and the impact of the crosstalk at the output of the multiplexer (Figure 4.4). Figures 4.4 (a) (2-channel multiplexer) and (b) (64-channel multiplexer) illustrate crosstalk in AFEs with the multiplexer located at the electrode interface against the electrode impedance variations. On the other hand, Figures 4.5 (a) (2-channel multiplexer) and (b) (64-channel multiplexer) show the crosstalk in AFEs with the analog multiplexer before the PGA, against the IA’s output resistance variations. Firstly, it can be observed that the effect of both variations increases with the number of multiplexed channels. Secondly, as the electrode impedance is usually largerthan the output resistance of a conventional amplification stage, multiplexer crosstalk noise has major impact on topologies with multiplexing at the input of the AFE than in other multiplexed architectures. In the worst case, this crosstalk remains below -65 dB and can be further reduced by properly designing the multiplexer. The effect of multiplexer crosstalk is, therefore, lower than that of electrode crosstalk and 42 4.2. Taxonomy of Multi-channel Neural Recording Multiplexed Systems can be ignored as a source of noise in most analyses of multi-channel neural recording devices. 105106107 Electrode Impedance (Ohms) -140 -130 -120 -110 -100 Crosstalk (dB) 105106107 Electrode Impedance (Ohms) -110 -100 -90 -80 -70 -60 Crosstalk (dB) Theoretical Simulation (a) (b) Theoretical Simulation Figure 4.4: Multiplexer crosstalk for TDM at the electrode interface against electrode impedance for (a) a 2-channel multiplexer. (b) a 64-channel multiplexer. 4.2 Taxonomy of Multi-channel Neural Recording Multiplexed Systems The neural front-ends presented in Section 2.3 can be multiplexed to reduce the area per channel of the device. Thereby, multi-channel neural recording AFE topologies can be classified by the position of the multiplexer in the signal path and, consequently, by the number of multiplexed blocks (Figure 4.6). 4.2.1 Non-Multiplexed AFE topology In non-multiplexed AFE topology (see Figure 4.6 (a)), each channel is recorded by a low-rate low-power AFE. For M independent recording channels, M independent AFEs are required. Herein, all the front-ends presented in Section 2.3 are suitable for being implemented using this architecture. The area limitations in the electrode interface make the integration of these AFEs along with the electrodes unfeasible. Moving the recording front-end far from the electrodes relaxes their size and power limitations. This enhances the design flexibility and allows the inclusion of additional on-chip functionality, such as data processing [ 10 ]. However, employing a complete AFE per channel increases the mismatch errors in multi-channel topologies [86]. 43 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS 103104 Output resistance of previous stage (Ohms) -180 -170 -160 -150 Crosstalk (dB) 103104 Output resistance of previous stage (Ohms) -140 -135 -130 -125 -120 Crosstalk (dB) (a) (b) Theoretical Simulation Theoretical Simulation Figure 4.5: Multiplexer crosstalk for TDM before the PGA against the IA’s output resistance for (a) a 2-channel multiplexer. (b) a 64-channel multiplexer. In terms of the analog-to-digital conversion, despite using a low sampling frequency, the need for one ADC per channel requires a very careful design in order not to largely penalize the area and power consumption of the neural recording IC. Successive Approximation Register (SAR) ADCs have generally provided a suitable performance for this kind of topologies [ 41 , 48 , 34 , 10 ]. After conversion, the signal is multiplexed, typically by using data serializers [ 32 , 49 ]. In the digital domain, multiplexing is less prone to errors because the signal has higher noise margins and is more stable against crosstalk and other noise sources. 4.2.2 ADC Sharing & PGA Sharing AFE topologies One of the most popular approaches for multi-channel architectures is to use a single ADC shared by all channels (Figure 4.6 (b)). Theoretically, this reduces the form factor and the power consumption of the IC in comparison with nonmultiplexed AFEs. This topology is based on M parallel structures sharing a single ADC [67, 129, 130, 131, 78]. The electrical properties of the electrode-AFE interface for these architectures are the same as for non-multiplexed AFEs. In these topologies, the signal after amplification is directed towards the ADC by means of TDM. Increasing the sampling frequency increases the required power consumption of the ADC and its previous stage, even requiring driving buffers at the input of the converter [132]. Most ofthe topologies presentedin Sec. 2.3 are suitable forbeing multiplexed 44 4.2. Taxonomy of Multi-channel Neural Recording Multiplexed Systems ChM Ch2 Electrodes LNA PGA Ch1 M:1 MUX ADC Wireless Tx ChM Ch2 LNA PGA Ch1 M:1 MUX ADC Wireless Tx M:1 MUX Electrodes LNA HB PGA ADC Wireless Tx Electrodes M N:M SEL Electrodes N ChM Ch2 LNA PGA Ch1 M:1 MUX ADC Wireless Tx (a) (b) (c) (d) ChM Ch2 Electrodes LNA PGA Ch1 M:1 MUX ADC Wireless Tx (e) Figure 4.6: (a) Non-multiplexed AFE topology. (b) PGA sharing AFE topology. (c) ADC sharing AFE topology. (d) Switch array AFE topology. (e) Time-division-multiplexing AFE topology. at the ADC stage. However, while chopper-stabilized AFE topologies demand an additional stage to properly settle the ADC, digitally-assisted architectures involve a considerable rise of power consumption. This is due to the need for oversampled blocks in addition to memory blocks which store the information of each channel to properly performing the mixed-signal operation. A similar alternative to ADC sharing relies on sharing, not only the ADC but also the PGA for the M independent channels, as shown in Figure 4.6 (c)). In this topology, the input amplification stage can be integrated into the same 45 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS Freq Bw Folding Freq Amplitude Noise Signal Amplitude fbfb fc/2 Signal Freq Noise Charge Sampling Freq Folding Amplitude Amplitude fifbfb fc/2 Digital Processing Signal Signal Bw (a) (b) Figure 4.10: Noise folding problem in (a) VS-based multiplexing circuits. (b) CS-based multiplexing circuits on integrating the signal during a period Ti , with fi= 1/ Ti and fc<fi<fs , and then sampling the last value. The NEB for charge-sampling architectures is then given by [17]: NEBCS =f s 2=−M fc/2 (4.10) It is worth noting from 4.10 and 4.7, that the NEB is reduced by ln ( ² )/2. Figure 4.9 illustrates how the NEB for CS-based topologies is significantly lower than for VS-based architectures when the number of multiplexed channels is large. Thus, high-frequency noise components are filtered (Figure 4.10 (b)) according to a sync filter specification [ 145 ], reducing the noise folding effect. In terms of circuit implementation, this technique is performed by a transconductance Gm -cell driving a sample-and-hold capacitor, Cint . The DC gain of this architecture is given by: CSDC =GmTi Cint (4.11) However, this technique has some significant drawbacks: i) the pole of the sync filter and the DC gain of the architecture are very sensitive to clock jitter [ 145 ]; 2) process variations willhave a high impacton the system’s gain and time constant due to the employment of an open-loop structure; 3) low-frequency noise components are not reduced; 4) large CM signals could change the operating point of the Gmstage, which may lead to distortion or even saturation. 52 4.3. Review of Time-division-multiplexing AFEs 4.3.2 DC Offset from Electrodes in TDM AFEs DC offset from electrodes is a recurrent problem in DC-coupled AFEs [ 47 , 53 , 52 ]. In most of the architectures employing an IA per channel, DC offset can be rejected using large time constant high-pass filtering stages. However, these analog filters are not suitable in rapid multiplexing systems, since the filtering would increase crosstalk between channels and would not be fast enough to reject large DC offset variations between channels. One solution to this problem relies on limiting the gain of the AFE and increasing the resolution of the ADC. However, this extra resolution, together with the high sample rate required for multiplexing, would make the ADC unsuitable for low-power designs. High-pass filtering the signal through a mixed-signal loop has been adopted as an alternative approach to palliating this issue in DC-coupled topologies [ 25 , 97 ]. In this method, a Finite-Impulse-Response (FIR) or Infinite-Impulse- Response (IIR) filter is fed into the input of the AFE by a DAC. While the filter can be designed to not penalize the system’s power consumption and area occupation, the required DAC resolution has to be high enough not to increase the noise at the input of the AFE. The number of bits of the DAC will be then determined by the resolution of the ADC, the overall gain through the signal path, and the input-referred noise of the AFE. In most practical cases, a DAC of more than 16-bits is required, which strongly compromises the form-factor specification of the neural recording front-end. An adopted solution for implementing this high-resolution DAC is to employ a ∆Σ modulator [ 25 , 97 ]. However, this method is not feasible for TDM AFEs because the required oversampling frequency will be multiplied by M , and this will significantly impact the power consumption of the digital part of the IC. An alternative to a high-resolution DAC would be to use a binary search algorithm, as proposed in [ 18 ]. This algorithm initially computes the DC offset codes for each channel and retains the correction values until a threshold condition occurs. At that instant, the binary search recalculates the correction value for each channel. By applying this method, DC offset drifts are palliated without increasing the input-referred noise of the AFE. Nevertheless, although the system range is ensured, there will be a residual offset at the output of the AFE, which must be filtered in the digital domain. Another proposed solution is based on working with ∆ -signals (as illustrated in Figure 2.8 (c) and (d)). In this approach, the system tracks differences between successive samples, high-pass filtering the input signal. After conversion, the signal has to be reconstructed in the digitaldomain using an integrator/accumulator. This technique can be transferred to TDM AFE topologies by employing registers to store the previously sampled value of each channel. One example of a TDM AFE that exploits this technique is reported in [11, 12]. 53 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS 4.3.3 Comparison of TDM AFE Architectures Despite their promising results, to the best of the authors knowledge, TDM AFE topologies have not been researched in depth. In this subsection, two main reported TDM AFE architectures are detailed. Block diagrams of these neural front-ends are shown in Figure 4.11 and more detailed in Figure 4.12 and Figure 4.13. As illustrated in Figure 4.11, both structures are based on mixed-signal architectures for DC offset rejection. ADC M - MUX IA DAC1 Binary Search Electrodes DSL Off-chip DAC2 OTA ADC M - MUX DAC Calibration & Weigthed Sum DM artifact Template Electrodes Integrator Off-chip Δ- Encoding Autozero & CM Supression CS OTA WIS (a) (b) Figure 4.11: Block diagram of the reported TDM AFE topology in (a) [17, 18]. (b) [12]. The first architecture, reported in [ 17 ] and [ 18 ], is illustrated in Figure 4.11 (a) and detailed in Figure 4.12. In this proposed scheme, 20 channels are multiplexed. The IA comprises a capacitive feedback single-stage cascaded OTA whose gain is fixed by the ratio Cin / Cf b . This input stage is biased by a noisy bias network. Then, an open-loop OTA is employed as a Gm -cell along with the SAR ADC capacitors to implement the WIS filter and to further amplify the signal (Figure 4.12 (a)). This reduces the high-frequency noise components from the acquisition electronics and from the electrodes. The timing diagram of this operation is shown in Figure 4.12 (b). It can be seen that the integration period, Ti , lasts for most of the sampling period, Ts . After that, before the capacitors of the ADC are reset ( φr st ) and the input channel is changed, the conversion 54 4.3. Review of Time-division-multiplexing AFEs phase, Tconv , takes place for only 11 % of the sampling period. This short-time conversion is carried out by an asynchronous converter. To remove the DC offset, a binary search algorithm is implemented externally by a Python script. This algorithm recomputes the 9-bit code each second to palliate the input DC offset. This is fast enough to compensate DC drifts at the input. The code is divided into 4-bits for DAC 1 and 5-bits for DAC 2 and maximizes the useful dynamic range of the system while reducing the ADC requirements. These both used DACs are embedded in the amplifier’s structures. Frst Fi Fi Gm Frst Async ADC Cint Cint Ts Frst Fi 9-bit output Ti Tconv 5-bit DAC Binary Search OTA 4-bit DAC Cfb Cfb Cin Bias Cin Vref F1 FM F2 Vin,M Vin,2 Vin,1 FM F1 F2 (a) (b) Figure 4.12: (a) Scheme of the TDM AFE proposed in [ 17 , 18 ]. (b) Timing diagram of the presented scheme. A ∆ -Encoded TDM AFE was first presented in [ 11 ] and further developed in [ 12 ] (Figure 4.11 (b) and Figure 4.13). In this architecture, after the 64-channel input multiplexer, a switching scheme performs two main functions: i) autozeroing the inputs to reduce crosstalk between adjacent channels, and ii) largely suppressing the CM signals. This switching scheme (Figure 4.13 (a)) comprises the input capacitors, Cin , and the switches whose phases are φAZ1 , φAZ2 and φT IE . This switched architecture presents two operation modes. The first mode is intended for neural recording with the absence of large CM perturbations and its timing diagram is illustrated in Figure 4.13 (b). The second mode, triggered by the CM flag signal, largely suppresses the CM interferences. This mode was previously explained in Section 3.2 and its operation was simplified and shown in Figure (3.9 (b). It is worth pointing out that when the CM suppression is en- 55 4. TIME-DIVISION MULTIPLEXING IN NEURAL RECORDING FRONT-ENDS abled, the performance of the system specially in terms of bandwidth and IRN is penalized [ 12 ]. After the switching scheme, an 8-bit capacitive DAC connected to the input node of the OTA then carries out the ∆ -operation by subtracting the previous signal value to the current value, increasing the system’s dynamic range. Afterwards, the ∆ -signal is amplified by a charge-sampling amplifier consisting of an open-loop Gm -cell, capacitors CL and switches (Figure 4.13 (a)). Note that the value of CL is variable, mainly to set the gain of the charge-sampling topology and to palliate the φi clock variations. The timing diagram of this sampling operation is illustrated in Figure 4.13 (b). Once the signal is converted by an 8-bit SAR ADC, it can follow two paths: i) through the mixed-signal loop to perform the encoding technique; ii) to the sum and reconstruction block. In the mixed-signal path, the first stage is a user-programmable threshold block which determines the update quantity of the tracking signal to perform the ∆ encoding. The update values, which can be − 1, 0 or + 1, are added to the previous tracking values, which are stored in a 64x8-bit register. This unit holds the correction data for each input channel, and, together with the tracking update value, performs an integration loop. The output signal from this loop feeds the DAC and is also scaled and added to the ADC output in order to reconstruct the signal. The output code thereby increases its resolution from 8 to 16 bits. In both schemes, the input impedance is mainly defined by the input capacitors and the sampling frequency. Herein, these values along with the electrodeinterface have to be carefully selected to not significantly increase the attenuation at the input of the system. This could compromise the scalability of the system, and, therefore, its spatial resolution. This scalability could be also degraded by the fact that both circuits demand external circuitry to properly operate. In the case of [ 17 ], it requires a computer to perform the DC offset removal and, in the case of [ 12 ], a Field-Programmable Gate Array (FPGA) is employed to tolerate large input DM signals. 56 4.3. Review of Time-division-multiplexing AFEs Fi Gm SAR ADC 8-bit th+ th- WDAC(7) WDAC(6) WDAC(7) WDAC(0) WDAC(7) WDAC(6) WDAC(7) WDAC(0) CLFAZ Vmid FAZ Vlow Fi CLFAZ Vmid FAZ Vlow 8-bit Sum and Calibration 16-bit output Ts FAZ Fi Ti 64x8b Register FM F1 F2 FAZ2 Vmid FAZ2 Vmid Cin Cin Vmid Vmid FAZ1 FAZ1 FTIE F1 FM F2 Vin+,M Vin+,2 Vin+,1 F1 Vin-,1 F2 Vin-,2 FM Vin-,M CM Flag Stimulator Control FAZ1 (a) (b) Figure 4.13: (a) Scheme of the TDM AFE proposed in [ 11 , 12 ]. (b) Timing diagram of the presented scheme for no CM signals supression. Note that φAZ 2 and φT IE are not shown and open for the whole period. 57 CHAPTER 5 A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM I n the course of this work, the main considerations about designing multichannel neural recording systems have been addressed. As aforementioned, most of the design constraints of neural recording devices are related to power consumption, area occupation and noise. Some techniques and architectures have been presented to improve these system’s specifications. Here, TDM AFEs have demonstrated to be an auspicious alternative to conventional neural frontends, specially increasing the area efficiency per channel. Moreover, for closedloop systems in presence of large stimulation artifacts, the dynamic range and the maximum input tolerable signal have also emerged as key specifications in the design of these interfaces. This chapter addresses the above problems and presents a 32-channel lownoise, high dynamic-range recording front-end, fabricated in a 180 nm standard CMOS technology. Focus has been on the recording of LFPs or ECoG signals. This extends earlier contributions in [ 146 ] and [ 116 ] with new experimental verifications, including measurements in saline, and additional theoretical analysis with emphasis in bandwidth and noise issues. The new prototype herein presented integrates a modified version of the converter in [ 147 ] and a new dedicated digital signal processor along with some minor modifications and corrections not included in our previous prototype [ 146 ]. The design follows a TDM recording strategy and uses two digital-feedback loops which provide robustness against large interferences with little impact on power consumption, area occupation or noise behavior. One loop implements a voltage-triggered 59 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM auto-ranging algorithm which allows to extend the effective dynamic range of the AFE to 71dB + 26dB; the other is a DC servo loop for electrode offset cancelling which extends the AFE input range to 300 mVpp . Design considerations to not sacrifice other specifications such as crosstalk between channels, CMRR or input impedance are also presented. Furthermore, extended theoretical analyses have been carried out in order to describe the system’s performance in terms of bandwidth and noise. Compared to previous TDM front-end proposals withwhich this work presents similarities (only two to our best of knowledge, [ 17 , 11 , 12 , 148 ]), our circuit uses a closed-loop amplification and filtering approach instead of charge-sampling techniques, it offers the possibility of applying both bipolar or monopolar sensing at the input multiplexer and it can delta encode neural signals between channels [ 32 , 29 ] instead of tracking signal increments per channel. Additionally, our system offers two output modes (in one of them input signals are reconstructed including interferers, no matter their morphology or origin) and exploits the auto-ranging loop for handling differential-mode artifacts instead of adaptive filters [148]. 5.1 System Overview Figure 5.1 shows the block diagram of the proposed time-multiplexed neural recording system. The main core has been integrated in an Application Specific Integrated Circuit (ASIC) while some functions have been implemented in a micro-controller (µ-C, Rigado®BMD-350). ADC DAC MUX Auto-ranging SPI ASIC Control Unit SPI Clock Gen μ-Controller rst clk Artifact Attenuation Artifact Restoration BLE Control M Electrodes Bipolar / Monopolar Sensing IA1IA2 HPF Calibration DSL D Mode 2 Mode 1 LUT Test ADC Mode 1 Mode 2 Decimation Filtering z-1 M z-1 M Figure 5.1: Block diagram of the proposed neural recording system. After a switch matrix to multiplex M input neural signals, the ASIC comprises two cascaded fully-differential low-noise instrumentation amplifiers ( IA1 and IA2 ) to sample, filter and amplify the signals captured by the electrodes. The multiplexer can be configured in two sensing modes, monopolar or bipolar, depending on whether signals are referred to a common reference or voltage differences between nearby electrodes are measured. Following amplification, a rail-to-rail SAR is used for taking signals into digital-domain. In this work, input signals are oversampled by a Oversampling Ratio (OSR) to reduce the in-band AFE IRN. The bandwidth of interest has been limited to Bw≈ 200 Hz. 60 5.1. System Overview Accordingly, the AFE sampling rate has been set to fs= 2 MOSRBw to satisfy the Nyquist rate criterion. All the time references are extracted from a master clock with frequency, fm . For easy reference, Table 5.1 summarizes the main system frequencies and their notations. Table 5.1: Summary of Frequency Parameters Symbol Description Equivalent Value fmMaster clock frequency 2.5 MHz fsSampling frequency fm/13 =2·M·OSR ·Bw fbAmplifier Bandwidth >fs fcSampling frequency per channel fs/M fI A CDS Bandwidth fc≈fI A <fs/2 Two feedback loops from the ADC memory are combined in a digital adder to drive the input of the first instrumentation amplifier by means of two DACs, one per differential terminal of the AFE. One loop, denoted as Auto-Ranging Loop (ARL), is used for the compression of large interferers, such as differential artifacts. The other feedback mechanism is a DSL for input offset rejection [ 25 ]. This loop is preceded by a decimation stage to filter signals down to baseband. Similar to [ 148 ], the ASIC control unit can enable an off-line calibration process to obtain the ADC outputs for all possible DAC input codes. The ASIC features two output modes. In Mode-1, the decimated signal is transmitted through an SPI port. If monopolar sensing is enabled at the input multiplexer, the system gives the option to transmit increments between consecutive recordings. The purpose is to explore the possibility to losslessly reduce the word length of neuronal data, taking advantage of the large spatial correlation observed in LFP/ECoG signals captured from nearby electrodes. In bipolar sensing, decimated signals are inherently delta compressed and there is no need for further processing. For both sensing methods, output words are 14-b long. The second output mode, called Mode-2, is essentially used for verifying Mode-1 outcomes. In Mode-2, the output consists of two signals which are transferred through corresponding serial ports. One of the signals is the undecimated output of the SAR ADC (10-b) and the other is the sequence of the ARL codes (9-b). These codes are combined in the µ -C to losslessly reconstruct the input signal, including artifact, with 14-b resolution. An optional HPF has been also implemented in the µ -C for removing any residual DC component before data is transmitted through the Bluetooth Low-Energy (BLE) interface. For all the modes and rates, this HPF is a 6 th -order Butterworth IIR filters with cut-off frequency at 0.5Hz. 61 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM 10-3 10-2 10-1 f Ts -25 -20 -15 -10 -5 0 Norm. Transfer Function (dB) fIA GIA = 17.21 GIA = 19.67 GIA = 22.12 GIA = 24.58 GIA = 27.04 GIA = 29.50 GIA = 31.96 GIA = 34.42 Figure 5.8: Normalised transfer function of the CDS instrumentation amplifier for different gain settings. The IA1bandwidth is marked in red. 10-3 10-2 10-1 fTs 100 100 PSD (fV /Hz) 2 300 500 700 Simulation Theoretical fIA Figure 5.9: Output noise spectral density comparison between simulation results and the proposed model. experimental results show that more than 80% of noise comes from this stage), taking only into account the white noise contribution from the OTA (this represents more than 94% of the total noise generated by IA1 ), can be approximated as [153, 154]: SI A(ω)=4sinc2(ωTs/2) SCDS(ω) (5.7) where sinc ( x ) ≡sin ( x )/ x and SCDS ( ω ) is a spectral density factor which depends on this particular CDS topology (see Appendix A for calculation details). This expression takes into account the folded noise components inherent of CDS techniques. The noise folding factor Nf≈πfb / fs , where fb is the OTA band- 68 5.2. Analog Front-End width, is essentially defined by the requested settling accuracy and amounts about 7 for IA1 in this design. Figure 5.9 plots SI A ( ω ) for IA1 using both electrical simulations and equation (5.7). The discrepancy between the plots is lower than 2% in the range from 1 Hz to 4/ Ts , thus confirming the accuracy of the model. Note that the 4 sinc2 ( ωTs /2) factor in (5.7), which accounts for the hold operation of the amplifier, provides additional anti-aliasing filtering to the narrow-band amplifier. The side lobes of the noise spectral density are more than 2 orders of magnitude smaller than the spectral density in the passband. The noise equivalent bandwidth is approximately given by πfI A /2 (assuming a first-order roll-off model), and, hence, similar to the sampling frequency per channel. This allows attenuating the out-of-band noise folded components arising from time multiplexing as illustrated in Figures 5.3(c-d). Hence, the approach effectively reduces the integrated input-referred noise compared to the case in Figure 5.3(b), while power consumption, essentially determined by settling considerations, remains at approximately the same level [ 17 ]. Note also that, once in digital domain, the decimation and filtering stage reduces the quantization noise of the ADC and filter out the thermal noise beyond the bandwidth of interest. Hence, the in-band noise power is actually divided by the oversampling ratio, thus palliating the noise folding due to the CDS operation. Furthermore, assuming the same noise folding factor, the OTA bandwidth increases with the oversampling ratio, what decreases the OTA noise floor and, hence, the overall folded noise compared to a non-oversampled system. This is at the cost of additional power and area consumption; however these increments are averaged by the number of channels multiplexed, as will be shown in the next subsection. It is also worth remarking this combined strategy of narrow-band signal acquisition and oversampling not only holds for the OTA noise but also for the noise from the multiplexed electrodes. Using the microwire array model reported in [ 17 ], simulations from extracted layout were run to evaluate the noise contribution of the electrodes ( M= 32) and the in-band input-referred noise was lower than 3 µVrms in Mode-1, similar to the results presented in [ 17 ] with windowed integration sampling techniques. 5.2.3 Scalability Figures 5.10 and 5.11 illustrate the scalability of the proposed analog front-end, including the ADC, in terms of the number of multiplexed channels (from 16 to 128) and the sampling rate per channel (from 6- to 30kS/s), respectively. While the former analysis is performed in Mode-1, the latter considers Mode-2 operation. In both cases, changes in power and area consumption, as well as, in-band IRN, have been the metrics used for assessing scalability. In all the analysed configurations, the OTA structure of Figure 5.5, the capacitances in Figure 5.4, the oversampling ratio OSR , and the supply voltage have been preserved as in the current design; however, OTAs have been resized to guarantee operation in 69 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM weak inversion. 20 30 40 50 60 70 80 90 100 110 120 Number of channels 0.8 0.85 0.9 0.95 1 Power/channel (mW/ch) 20 30 40 50 60 70 80 90 100 110 120 Number of channels 1 1.2 1.4 1.6 1.8 2 In-Band IRN (mVrms) 20 30 40 50 60 70 80 90 100 110 120 Number of channels 0.005 0.01 0.015 0.02 Area/channel (mm2/ch) (a) (b) (c) Figure 5.10: System scalability in terms of the number of multiplexed channels: (a) Power consumption per channel; (b) in-band IRN; and (c) area per channel occupation (only analog circuitry). The OTA power consumption in IA1 and IA2 has to increase with the number of multiplexed channels to meet with bandwidth requirements. This is observed in Figure 5.10(a) where the power consumption per channel remains fairly constant with M . Deviations are due to the impact of OTA parasitics (in particular, the gate-to-drain capacitances Cm ) on the feedback factor, βq , of the OTAs – see Appendix A. Further, as the power consumption of the OTAs increases, the intrinsic in-band thermal noise floor of the IAs decreases, thus, partially compensating for the noise folding due to channel multiplexing, for the same settling accuracy. This is illustrated in Figure 5.10(b) where only a mild increase in IRN is observed with the number of multiplexed sites. Finally, it is observed that, although the OTA dimensions have to scale with their power consumption to keep input transistors in weak inversion, the total area occupation per channel of the analog circuitry (only 10% of the total active area) actually decreases, as shown in Figure 5.10(c). Similar arguments hold if the sampling rate per channel is increased for the recording of action potentials, typically at 30kS/s [ 10 ]. As shown in Figure 5.11(a) and (c), the power consumption and the area occupation per channel increase with the recording bandwidth. However, increasing the recording bandwidth can only be done by increasing OTA bandwidths which, in turn, decreases the noise thermal floor and, thereof, the r ms value of the aliased noise components due to multiplexing. Accordingly, the in-band IRN decreases with the recording bandwidth as illustrated in Figure 5.11(d). 70 5.3. Digital Processing Power/channel (mW/ch) In-Band IRN (mVrms) Area/channel (mm2/ch) (a) (b) (c) 1 2 3 4 2.5 3 3.5 4 4.5 5 8 10 12 14 16 18 20 22 24 26 28 30 0.01 0.0105 0.011 0.0115 0.012 8 10 12 14 16 18 20 22 24 26 28 30 8 10 12 14 16 18 20 22 24 26 28 30 Sampling rate (kS/s) Sampling rate (kS/s) Sampling rate (kS/s) Figure 5.11: System scalability in terms of bandwidth: (a) AFE power consumption per channel; (b) in-band IRN; and (c) area per channel occupation (only analog circuitry). 5.3 Digital Processing The samples converted by the SAR ADC are demultiplexed in digital domain by cyclically filling a 32-location memory block using a 5-b counter for address selection. This effectively decreases the sampling rate per channel to fc . As shown in Figure 5.1, the stored codes, VADC , are then serially transferred to either the auto-ranging block or the DC servo-loop, this latter via a decimation and filtering circuit which is implemented by a 2 nd -order Cascaded Integrator–Comb (CIC) filter (see Figure 5.12). Z Z Z Register x32 rst Z Z Z Register x32 rst 18b SE 10b VADC Z Z Z Register x32 rst 16 Z Z Z Register x32 rst 14b 10b VDEC VOUT Decimation Integrators Comb filters Figure 5.12: Block diagram of 2nd-Order CIC filter with decimation. 5.3.1 DC Servo Loop The purpose of the DSL is twofold: (i) to limit the offset at the input of the front-end IA and (ii) to place a high-pass pole in the AFE transfer function. The 71 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM proposed architecture is shown in Figure 5.13 and consists of two main elements; a digital integrator and a binary search algorithm block, both operating serially over the 32 multiplexed channels. The former has been preferred for filtering instead of high-order FIR/IIR structures as they require larger area occupation and may even lead to stability problems [ 155 ]. Similar to [ 17 ], a binary search block has been chosen for driving the DACs instead of Σ∆ modulators [ 25 , 97 ]. Because of the TDM operation, such modulators would require large oversampling frequencies and/or high-order topologies, which would demand large power consumption and area occupation. In the proposed approach, the DSL output code is only updated when necessary (for instance, if offset drifts are detected), avoiding the onset of potential oscillations at the AFE input. Z Z Z Register x32 rst GINT Binary Search Algorithm Z Z Z Register x32 rst VINT WDSL 2x8b 9b 21b SE 10b VDEC Fd Fd Figure 5.13: Block diagram of the Binary Search DC Servo Loop. The gain factor, GINT , of the integrator has been chosen as the largest integer power of 2 satisfying [155] fhp ≤Bw πln³1 1−RCGDC GI NT ´(5.8) where fhp is the intended frequency for the high pass pole of the AFE transfer function (in the proposed design fhp = 0 . 5Hz), GDC is the DC gain of the AFE feedforward path and RC is the ratio between the total DAC capacitance, i.e., Ctot =Cu (2 8− 1), and the input capacitor, Cin . In this design, GINT must be at least 1/6000 so it has been rounded off to 1/2 13 for easy implementation through bit shifting. The integrator accumulates the VDEC values (extended to 21-b to avoid overflows) provided by the decimation and filtering stage. Every Td= 2 9 / Bw period (aprox. 3 seconds long) at instances of pulses Φd , the output of the integrator, VINT , is transferred to the binary search blockand then it is initialized to 0 to start a new count. Either at start up or on-demand through a reset operation, the binary search block solves the binary words of the input DACs, WDSL , sequentially from Most Significant Bit (MSB) to Least Significant Bit (LSB), based on the VINT values provided by the integrator. As is conventional, every bit is decided at each iteration based on the sign of VINT . During the process, the auto-ranging block is disabled so it does not interfere in the binary search. Once the search is 72 5.3. Digital Processing Voltage -VDAC ¾ VDAC ½ VDAC ¼ VDAC 0 -¼ VDAC -½ VDAC -¾ VDAC VDAC Time VINT Td wp7 = 1 wn7 = 0 wp6 = 0 wn6 = 1 wp5 = 1 wn5 = 0 wp0 = 1 wn0 = 0 |VINT|<VBS wp7 = 1 wn7 = 0 wp = 0 wn = 0 ResetStabilization Binary Search Figure 5.14: Illustration of the different operation modes of the binary Search block. completed, the block assesses that the following VINT instances verify |VINT |< VBS , where VBS is a threshold value corresponding to the maximum tolerable offset at the AFE input. In this design, VBS =VLUT (2 10 ), i.e., the ADC code stored in the LUT after calibration corresponding to 2 DAC LSBs. If the condition is met, WDSL preserves its previous values, otherwise, it is incremented or decremented by 1 DAC LSB to compensate for potential DC drifts as large as 0.4mV/s (this is 25% larger than the drift rates experimentally measured in [ 18 ]). This mechanism provides dc baseline stabilization. 5.3.2 Auto-Ranging Loop The purpose of the ARL is to make the recording system tolerant to undesired high amplitude interferers or artifacts. More specifically, the feedback loop avoids the onset of saturation in the AFE main signal path whenever the input signal exhibitvariations below 40 V/s and, in case of fastertransitions, it provides mechanisms for quick recovery into non-saturated system operation. This is particularly relevant in monopolar sensing mode where signals are acquired with respect to a common reference and may exhibit larger voltage swings than in bipolar mode. The ARL operation is triggered when the input neural signal, contaminated by the interferer, exceeds threshold voltages, ±Vth , beyond the useful signal range. In this work, Vth amounts 2.5mV p ; much larger than the peak amplitude of LFP/ECoG signals which is typically below 1mV p [ 25 ]. If the input signal surpasses these limits, the ARL block generates voltage increments which are added or subtracted at the AFE input to take the signal back to the ±Vth range. Similar auto-ranging procedures were proposed in [ 55 , 9 ]. Along this operation, no attempt is made to distinguish between neural signals and interferers, as the ARL block does not rely on the use of complex filtering stages or template-based mechanisms for artifact detection and suppression [12]. 73 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM The block diagram of the ARL circuit is shown in Figure 5.15. First, a dead zone operator with bounds at ±Vth is applied in the incoming VADC signal to obtain VZ(l)=       VADC (l)−Vth ,VADC (l)>Vth 0 ,|VADC (l)|≤Vth VADC (l)+Vth ,VADC (l)<−Vth (5.9) where l is a time index at a clock rate fc . Any VZ ( l ) outside the dead zone is deemed to be affected by a high amplitude interferer. Then, the auto-ranging block generates the correction code WA(l)=(WA(l−1)−αVZ(l) ,VZ(l)6=0 WC(l−1) ,VZ(l)=0(5.10) which is fed back to the AFE input (Figure 5.1). Artifact Compression Algorithm Z Z Z Register x32 rst VADC 9b 10b WA WR VZ Vth -Vth Z Z Z Register x32 rst Figure 5.15: Block diagram of the auto-ranging circuit. If |VADC ( l ) | > Vth , the correction code WA ( l ) aims to take the next VD AC instance back, or at least closer, to the dead zone. No overflow is permitted, i.e., the magnitude of WA ( l ) is limited by an all-ones word. The scaling factor α is nominally given by the voltage gain from the DAC input to the ADC output as, α=VBG VDD 2 RCGDC (5.11) where the factor 2 accounts for the 1-b difference between the DAC and ADC resolutions. In practice, α has been rounded to the nearest power of 2 so scaling can be simply implemented through bit shifting. If |VADC ( l ) |≤Vth , two cases can be distinguished; either there is no artifactor an artifact is ongoing but VADC is comprised within the dead zone. Accordingly, variable WCin (5.10) is given by, WC(l)=(0 ,|WR(l)|≤WBS WA(l) ,|WR(l)|>WBS (5.12) 74 5.3. Digital Processing where WBS amounts 2 DAC LSBs and the control variable WR ( l ) to decide between both states is simply given by the WA increment, WR ( l ) =WA ( l ) −WA ( l− 1). From (5.12), if the accumulated value of WR ( l ) remains below a given tolerable offset deviation WBS , it means that the artifact has concluded and WC ( l ) = 0. Otherwise, WC ( l ) takes on the current correction code WA ( l ). This is done to avoid that a potentially large residual offset is held at the AFE input. In Figure 5.15, the control variable WR is serially calculated per channel by taking the difference between corresponding positions of two daisy-chain memories, one for WA(l) and the other for WA(l−1). The correction codes WA are transferred to the AFE DACs at a rate fs to voltage shift input samples and compress, within the dead zone limits, the highamplitude input signal formed by the superposition of the neural record and the interferer (no matter its morphology or origin). These auto-ranged input samples pass through the AFE direct signal path to obtain the system outputs. In mode-1 operation, the neural information in the band of interest can be recovered after decimation and filtering, although contaminated by the filtered residues of the interference and the ARL voltage compensation. These residues are due to the limited quantization of the DAC and, in sum, account for the finite attenuation of the artifact. Such attenuation depends on the amplitude and frequency content of the interference. In both cases, the larger the values, the higher the attenuation because the larger are the differences between the neural signal of interest and the artifact. This is illustrated in the 3D plot of Figure 5.16 which shows the achievable attenuation versus the frequency and amplitude of the interference when the system is configured in monopolar sensing mode with no delta encoding. In this plot, input signals are formed by the superposition of two tones: a 2m Vpp tone at 30Hz emulating useful neural signal and a variable tone, representing the artifact, with amplitude larger than 3m Vpp (for triggering the auto-ranging mechanism) and frequency lower than half the sampling rate per channel, fc . Note that the attenuation is smaller in the baseband and grows significantly for larger frequencies, particularly for high amplitude interferers. Larger attenuations could be accomplished by narrowing the dead zone, however, this is at the expense of increasing the activity of the auto-ranging loop and, therefore, its power consumption. Similarly, the attenuation could be improved for low frequency interferers by increasing the scaling factor α ; however, this increases the chance for saturation at higher frequencies. For all the artifact configurations in Figure 5.16, the tone at 30Hz is recovered with eventual artifact-induced perturbations which, in any case, do not take the output signal out of the threshold limits. This will be illustrated in Chapter 6. In Mode-2, input signals are fully reconstructed, including artifacts, by reverting in digital domain the correction codes WA previously injected at the AFE input. To this end, the VADC values corresponding to each possible WA code have to be determined, taking into account not only the DAC nonidealities (mainly due to capacitor mismtach) but also any deviation in the AFE signal 75 5. A 32-CH TIME-MULTIPLEXED ARTIFACT-AWARE NEURAL RECORDING SYSTEM Amplitude (dBV) Frequency (Hz) Attenuation (dB) -50 -40 100 -30 -20 -10 102 104 50 60 30 40 20 0 10 Figure 5.16: Attenuation of sinusoidal artifact versus tone frequency. path. This vector mapping is obtained through an off-line calibration process in which the DAC is externally driven by a ramp sequence sweeping all WA values. The process does not modify any circuit in the AFE nor use any extra technique; it just stores in a 9 × 10 Look-Up Table (LUT) the ADC-converted versions of the referred deviations. Based on these values, the losslessly restoration of the input voltage at instant l , VR ( l ), including uncompressed artifacts, can straightforwardly be obtained as, VR(l)=VADC (l)+VLUT [WA(l−1)] (5.13) where the last term represents the voltage stored in the LUT for the correction code WA. 76 CHAPTER 6 EXPERIMENTAL RESULTS AND DISCUSSION F igure. 6.1(a) shows a die photograph of the ASIC, fabricated in a standard 180nm CMOS process. Its total active area is 0.70mm 2 . Figure 6.1(b) shows both sides of the test PCB. The ASIC, together with the µ -C and the electrode connector, is placed at the top (picture on th left), while a battery is located at the bottom (picture on the right). The power supply of the ASIC, provided by a voltage regulator connected to the battery, is 1.2 V. 6.1 Electrical Characterization and System Validation Powered by the battery, in Mode-1, the ASIC consumes 48 µ W so the power consumption per channel is 1.5 µ W/ch. The power budget, dominated by the first IA, is illustrated in the pie chart of Figure 6.2. In Mode-2 for artifact restoration, the power consumption raises to 82 µ W due to the increased data transfer rate to the µ-C. Figures 6.3-6.6 show measurements for single input channel characterization. Unless otherwise stated, the ASIC was configured in Mode-1, using monopolar sensing mode without delta encoding and the output was taken directly from the decimation stage with no extra processing. Channel #1 was indistinctly taken for analysis – no meaningful differences were observed for the other channels. In all cases, the reference was connected to ground. Figure 6.3(a) shows the transfer function of the AFE, obtained by applying input tones of1 m Vpp amplitude at different frequencies (soliddots in the figure). 77 6. EXPERIMENTAL RESULTS AND DISCUSSION -0.2 -0.1 0 0.1 -0.2 -0.1 0 0.1 1.8 1.85 1.9 Time (s) -0.5 0 0.5 Amp. (V) -0.5 0 0.5 Amp. (V) -0.2 0 0.2 Amp. (V) 1.8 1.85 1.9 Time (s) Ch. 1 Ch. 2 Ch. 3 Ch. 1 - Ch. 2 Ch. 2 - Ch. 3 (a) (b) Amp. (V)Amp. (V) Figure 6.8: ADC output w/out (a) and with (b) bipolar sensing. # of Samples Code Range -1000 -500 0 500 1000 0 5 10 15 (b) 5 # of Samples Code Range -1000 -500 0 500 1000 0 5 10 15 (a) 5 Figure 6.9: Output code range histograms for signals from Figure 6.8 w/out (a) and with (b) bipolar sensing. It is worth observing from Figure 6.7(e) that decoding errors in bipolar sensing mode increase with the channel order. This is due to the cumulative nature of (5.5). In fact, it can be shown that the output-referred noise power, v2 no,k , of the k-th reconstructed signal can be approximated as, v2 no,k≈i OSR hh2 12 +G2 AFE ·v2 n,∆i(6.1) where i is given by (5.2), h represents the ADC resolution after decimation and filtering and v2 n,∆ is the in-band input-referred noise variance of the ∆k increments in (5.4) before conversion. Hence, the output rms noise increases with the square-root of index i . This problem observed with bipolar sensing is not present in delta-encoded monopolar signals because both coding and decoding are implemented in digital domain [see (5.3) and (5.5)] and errors cancel out 84 6.2. In-vitro Measurements along signal decoding. This is illustrated in Figure 6.10 which compares the experimental output signals generated by the encoded monopolar and bipolar techniques after decoding. In both cases, the reconstructed signals are compared to the input signals and the mean absolute value deviations are quantified in effective LSBs. Measurements have been taken over the 32 available channels. Clearly, with monopolar signals, coding errors remain independent of the channel order. This suggests that bipolar recordings can relax specifications on AFE dynamic range, DC offset rejection or CMRR but they should be periodically refreshed to avoid that decoding errors increase indefinitely. 5 10 15 20 25 30 Channel 2 4 6 8 10 12 14 16 Mean Decoding Error (LSBs) Monopolar Recording Bipolar Recording Figure 6.10: Average decoding output error obtained by the monopolar and bipolar spatial delta-encoding in terms of the channel index i. The main objective in this design was the recording of LFP/ECoG signals; however, it is not completely true that spikes cannot be recorded. Certainly, it is not possible in Mode-1, but APs can be acquired in Mode-2 at a sampling rate of 6kS/s. This can be appreciated in Figure 6.11 using a pre-recorded in vivo signal (similar to that used in Figure 6.7). Figure 6.11, (a) shows the original signal sampled at 30kS/s and (b) shows the signal captured by our circuit in Mode-2. As can be observed, spikes can be identified although with lower number of samples compared to the input signal as well as some increase in the noise floor because the signal is not decimated and filtered. However, it is hardly feasible to identify the putative single-units responsible for the spikes with such a low number of samples. 6.2 In-vitro Measurements The following experiments were made with recording electrodes immersed in a Phosphate Buffered Saline (PBS) solution. Electrical signals, either in current or voltage form, were applied to the solution through a platinum electrode and recordings were captured in monopolar, non-coded configuration. Figure 6.12 shows the experimental setup. The crosstalk between channels was evaluated in saline by applying a set of 5m Vpp tones to channel #1 (aggresor) and measuring the impact on the 85 6. EXPERIMENTAL RESULTS AND DISCUSSION 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Time (s) -4 -2 0 2 4 Amplitude (mV) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Time (s) -4 -2 0 2 4 Amplitude (mV) (a) (b) Figure 6.11: (a) Pre-recorded in vivo signals containing APs captured at 30kS/s. (b) Signal captured by the proposed circuit in Mode-2 at 6kS/s. Computer with BLE Receiver Arbitrary Function Generator 1 Arbitrary Function Generator 2 Oscilloscope Spectrum Analyzer Test PCB Flexible Electrode Array + PBS Figure 6.12: Experimental setup for in-vitro measurements. other channel (victims) which were referenced to ground. These measurements showed that interferences remain below − 62dB for all channels across the signal band. However, this result cannot be attributed to the ASIC because same results were measured from the unmounted PCB alone. The capacitive couplings between the long interconnection lines running in parallelon the PCB are likely the cause of the observed crosstalk (similar to illustrated in Chapter 2). Hence, it can be estimated that the crosstalk induced by the ASIC is lower than the referred value (−85dB according to simulations). Figure 6.13 shows the results obtained when the solution was voltage driven by a long pre-recorded motion artifact superposed on a 1.5mV pp , 78Hz tone as signal of interest. A polymide-based sub-dural microelectrode array with 32 nanoporous gold electrodes separated by 300 µ m (diameter 30 µ m) was used for signal recording. The input waveform is shown in Figure 6.13(a), while Figures 6.13(b-e) show the outputs obtained from channel #1 along three different 86 6.2. In-vitro Measurements experiments with the same signal. Figure 6.13(b) shows the output when the ARL is disabled, resulting in the saturation of the AFE main signal path and, therefore, the lost of the signal of interest. In another experiment, Figure 6.13(c) shows the system output in Mode-1 with ARL enabled. Note that the signal of interest can be recovered although perturbed by the imperfect cancellation of the artifact, which is attenuated by 22dB (in agreement with Figure 5.16). In any case, the output safely remains within the linear range of the AFE. Finally, Figures 6.13(d) and (e) show, respectively, the compression code from the ARL loop and the reconstructed input signal in Mode-2. In this case, the combined waveform can be recovered with 99% correlation accuracy with respect to the original signal. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -20 0 20 Magnitude (mV) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 Time (s) -20 0 20 Magnitude (mV) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -20 0 20 Magnitude (bits) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 Time (s) -20 0 20 Magnitude (mV) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 Time (s) -20 0 20 Magnitude (mV) (a) (b) (c) (d) (e) Time (s) Time (s) Figure 6.13: (a) Pre-recorded motion artifact plus in-band 1.5mV pp tone applied to the saline solution, (b) output with ARL disabled, (c) Mode-1 output signal, (d) artifact compression code and (e) reconstructed signal in Mode-2. Using the same setup as in Figure 6.13, a symmetric biphasic stimulation current pulse was applied to the PBS solution through a voltage-controlled Howland current pump circuit. The duration of the cathodic/anodic phases is 2ms, with an interphase delay of 400 µ s, and a peak current amplitude of 100 µ A. Figure 6.14(a) shows the voltage recorded at the electrode interface with a commercial acquisition system (USB-ME32-FAI, Multi Channel Systems 87 6. EXPERIMENTAL RESULTS AND DISCUSSION MCS, GmbH). The other plots in Figure 6.14 were obtained with the proposed neuralrecording system along three different experiments with the same current stimulation. As in the previous example, Figure 6.13(b) shows the output with no auto-ranging, resulting in saturation; Figure 6.13(c) shows the system output in Mode-1 with ARL enabled and Figures 6.14(d) and (e) were obtained in Mode-2, representing the correction code and the reconstructed output, respectively. In this case, the reconstructed signal, including the artifact, is also almost identical to the signal recorded with the commercial equipment (97% correlation) and the attenuation of the artifact in Mode-1 amounts 25dB. (c) Time (ms) Magnitude (mV) 5 10 15 20 25 30 (b) Magnitude (mV) Time (ms) 5 10 15 20 25 30 (a) (e) Magnitude (mV) Magnitude (mV) Time (ms) Time (ms) 5 10 15 20 25 30 5 10 15 20 25 30 (d) Time (ms) Magnitude (bits) 5 10 15 20 25 30 Figure 6.14: (a) Voltage in the saline solution after applying a biphasic stimulation current pulse, (b) output with ARL disabled, (c) Mode-1 output signal, (d) artifact compression code and (e) reconstructed signal in Mode-2. Table 6.1 compares the presented proposal to other state-of-the-art high dynamic range neural recording systems. Although operation in Mode-2 is conceived as an auxiliary testing facility, it has also been included in the table for completeness. The table includes other artifact-aware [ 58 , 9 , 55 , 41 ] and TDM [ 17 , 12 ] proposals reported in the literature. As can be seen, this work performs comparably to other proposals along all metrics with noticeable improvements on input range, CMRR, linearity and dynamic range. Furthermore, all the functionalities discussed in this work have been implemented on-chip 88 6.2. In-vitro Measurements with the exception of the large interference reconstruction operation in Mode-2, which is done in the µ-C. 89 6. EXPERIMENTAL RESULTS AND DISCUSSION Table 6.1: Comparison with State of the Art [9] [41] [17] [55] [58] [12] This work Mode-1 Mode-2 Year 2014 2017 2018 2018 2019 2020 2020 Technology (nm) 180 180 HV 180 65 130 65 180 Supply voltage (V) 1 1 1 0.8 1.2 2.5 1.2 Power per channel (µW) 4.53 8 7 0.8 0.99 2.98 1.5 2.5 Area per channel (mm2) 0.129 - 0.0039 0.024 0.011 0.0023 ‡0.022 Artifact insentive DM DM - DM CM/DM CM/DM ‡CM/DM # multiplexed channels 1 1 20 1 1 64 32 Input differential range (Vpp) 8 100 17 †260 10 110 300 IRN per channel (µVr ms) 3.83 1,6 5.6 1 2.6 1.66 ?1.4 4.8 Signal bandwidth 5.7kHz - 15kHz 500Hz 1-500Hz 1-1000Hz ?0.5-200 Hz 0.5-3000 Hz NEF/PEF per channel 3.09/9.72 7.8/60.8 4.7/22.4 1.8/2.6 3.5/15.2 2.21/12.2 ?4.5/24 5/20 Crosstalk (dB) - - - - - -92 -85 CMRR (dB) - - 50 81 (0-60Hz) 78 76 87 THD <1%@3mVpp 0.7%@100mVpp 2%@17mVpp †71 (SFDR) 70.1 (SFDR) <1%@5mVpp 0.1%@5mVpp <1%@80mVpp Dynamic Range (dB) 66 90 66-68 †92 60 †91 71+26 (w/ARL) 83 Channel FoM (pJ/c-step) a0.139 0.309 0.401 0.025 0.052 0.013 ?0.065 0.036 † Estimated value not explicitly mentioned in the reference. ?For nominal recording operation, w/out CM artifact suppression. ‡ Off-chip DM artifact suppression. 4ADC not included. a. Channel-FoM(DR)=Pch/(2BW ·2ENOB(DR)), where ENOB(DR)=(DR(dB)- 1.76)/6.02. 90 6.3. Discussion 6.3 Discussion Time-division multiplexing AFEs have been exploredas a new promising paradigm for the design of multi-channel neural sensing devices because of their benefits regarding area and power consumption. Nevertheless, their inherent noise folding components significantly compromises the scalability of these systems. Techniques and architectures to overcome this issue have been explored. Charge-sampling [ 126 , 11 ] and windowed integration sampling [ 17 ] have been proposed to reduce this negative effect. The basic structure in both techniques consists in a Gm -cell driving a sample-and-hold capacitor. The hold operation attenuates high frequency noise components and effectively reduces the noise equivalent bandwidth to NEB =fs /2. Whilst simple, this circuit is not without drawbacks: the DC-gain and time constant of the AFE suffers from deviations due to process variations which may demand for some tuning mechanism; flicker noise, falling in the LFP/ECoG frequency band, and dc offsets are not reduced; large common-mode signals can drastically change the operation point of the Gm -cell, giving rise to distortion or even saturation; and the common-mode rejection ratio can be significantly lower than in closed-loop architectures. The two latter points can be solved by means of a passive SC arrangement before the charge-sampling stage [ 11 , 148 ], but this is at the expense of increasing the noise floor of the AFE. Table 6.2: Time-multiplexed Amplification-Filtering Stages Comparison CDS CS / WIS Architecture Closed-loop Open-loop Noise filtering SCDS ·sync2sync2 Noise folding Yes No Flicker reduction Yes No CM tolerance High Low Clock/Process variations Robust Weak Power Medium/High Low In this work, a different approach based on narrow-band Correlated Double Sampling instrumentation amplifiers is proposed. The DC gain of the structure is well-defined by ratioed capacitances and it inherently exhibits low-pass filtering characteristics which effectively reduces the bandwidth of the AFE transfer function. Additionally, the technique offers high linearity, large common-mode range and is tolerant against process variation. It also attenuates DC offsets and flicker noise [ 149 ] with no need for an additional dummy channel [ 148 ] which either reduces the equivalent sampling frequency per channel or demands for larger master clock frequencies. The cut-off frequency of the amplifier, fI A , can be made much lower than the sampling frequency, fs , so that folded noise 91 6. EXPERIMENTAL RESULTS AND DISCUSSION components falling in the bandwidth of interest are attenuated [ 149 , 150 ]. To lower the folded noise even further and, hence, reduce the input-referred noise of the structure, techniques such as oversampling are needed at the expense of larger power consumption compared to the charge sampling approach. Other techniques, a priori more suitable for reducing noise folding, such as chopping modulation [ 47 , 159 , 127 ], are difficult to implement in rapid time-multiplexing systems due to the need to remove up-modulated noise and offset components per channel with large time-constant low-pass filters [ 17 , 126 ]. Table 6.2 summarizes the main differences between the presented WIS and CS techniques and the employed narrow-band CDS architecture. 92 CHAPTER 7 CONCLUSIONS T his thesis was divided into two main parts. The first set of chapters (from Chapters 2 to 4) presented a review of multi-channel neural recording systems. In the second part, based on this study, this thesis proposed a prototype for implantable multi-channel neural recording applications (Chapters 5 and 6). The main contributions of this work are detailed below: • To offer a complete review of recording techniques and architectures for high-channel-count, densely-spaced microelectrode arrays. This provides high-performance strategies to optimize the area occupation and the power consumption of the silicon-based conditioning circuitry without penalizing other conventional neural sensing microsystems considerations. • To propose a novel study of the electrode-AFE interface where the pros and cons of embedding the input amplifiers adjacent to the electrodes are disclosed. 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Denker and et al., “LFP beta amplitude is linked to mesoscopic spatiotemporal phase patterns,” Scientific Reports, vol. 8, p. 5200, Mar. 2018. [159] F. Butti, M. Piotto, and P. Bruschi, “A chopper instrumentation amplifier with input resistance boosting by means of synchronous dynamic element matching,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 753–764, 2017. 117 Norberto Pérez Prieto Plaza de las Cortes 26 CP: 41500 Alcalá de Guadaira - Seville - Spain T+34 601 094 782 Bnorb[email protected] Education 2017–Present PhD in Physical Sciences and Technologies: Micro-Nano Electronics: Devices, Circuits, Systems and Applications ,Institute of Microelectronics of Seville (IMSE) - University of Seville (US), Seville, Spain. 2016–2017 Master in Microelectronics: Design and applications of micro/nanometer systems,IMSE-US, Seville, Spain. 2012–2016 Degree in Electronics, Robotics and Mechatronics,US, Seville, Spain. Theses PhD’s Thesis Title Low-Power Artifact-Aware Implantable Neural Recording Microsystems for Brain-Machine Interfaces. Advisor Dr. Manuel Delgado Resituto. Advisor Dr. Ángel Rodríguez Vázquez. Master’s Thesis Title Design of a Chopper-Stabilized amplifer for neural recording applications. Advisor Dr. Manuel Delgado Resituto. Advisor Dr. Ángel Rodríguez Vázquez. Bachelor’s Thesis Title About the application of Chopper technique in order to reduce flicker noise in neural recording amplifiers. Advisor Dr. Ángel Rodríguez Vázquez Professional Experience 2019 Internship ,Back telemetry circuit design for next generation of retinal implants, Second Sight Medical Products Inc, California, US. 2018–2021 Undergraduate Student Research ,Doctoral scholarship of the Spanish Ministry of Economy and Enterprise (MINECO), Integrated Pattern-Adaptive optical NEurostimulator with Multi-site recording Array (IPANEMA), IMSE-CNM. Seville, Spain 2016–2018 Predoctoral Researcher ,Scholarship in the University of Seville Researcher Foundation (FIUS), Study of recording and conditioning analog and mixed-signal interfaces for neural signals recording, IMSE-CNM. Seville, Spain Publications 2019 A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression ,Norberto Pérez-Prieto, Rafaella Fiorelli, José Luis Valtierra, Pablo Pérez-García, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez, Biomedical Circuit and Systems Conference (BioCAS), Nara, Japan. 2019 A High TCMRR, Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation ,José Luis Valtierra, Rafaella Fiorelli, Norberto Pérez-Prieto, Manuel Delgado-Restituto, Ángel Rodríguez- Vázquez, Biomedical Circuit and Systems Conference (BioCAS), Nara, Japan. 2019 A subµVrms Chopper Front-End for ECoG Recording ,Norberto Pérez Prieto, José Luis Valtierra, Manuel Delgado Restituo, Ángel Rodríguez Vázquez, IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan. 2019 Artifact-Aware Analogue Mixed-Signal Front-Ends for Neural Recording Applications ,Norberto Pérez Prieto, Manuel Delgado Restituo, Ángel Rodríguez Vázquez, ISCAS, Sapporo, Japan. 2017 A subµVrms Chopper-Stabilized Local Field Potential Amplifier ,Norberto Pérez Prieto, José Luis Valtierra, Manuel Delgado Restituo, Ángel Rodríguez Vázquez, XXXII Conference on Design of Circuits and Integrated Systems, Barcelona, Spain. 2017 A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation ,Norberto Pérez Prieto, Manuel Delgado Restituo, Ángel Rodríguez Vázquez, XXIII European Conference On Circuit Theory and Design (ECCTD), Catania, Italy. Courses and Programs 2020 Artificial Vision with MATLAB,MATLAB, IMSE-US, Seville, Spain. 2020 Automated Driving with MATLAB,MATLAB, IMSE-US, Seville, Spain. 2018 Innovus implementation system: blocks,Cadence, Online. 2018 IMFAHE mentor program,University of Seville - Harvard University. 2017 Labview Core I,IMSE-US, Seville,Spain. 2016 Machine Learning Course ,University of Stanford, imparted by Coursera, Online. Languages Spanish Mother tongue English Reading Fluent Cambridge First Certificate Exam (B2) (2016). Writing Fluent Oral Fluent French Reading Basic High School lessons (2006-2012). Writing Basic Oral Basic Other Skills Microcontroller Programming Intermediate nRF, TI... Android Programming Basic Android Studio. Driving Licence B References available upon request.