Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design

Reliable Analysis of Settling Errors in SC Integrators − Application to High-Speed Low-Power Σ∆ Modulators Design R. del Río, F. Medeiro, J. M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla − CNM-CSIC Edificio CICA-CNM, C/Tarfia s/n, 41012- Sevilla, SPAIN Phone: +34 95 4239923, Fax: +34 95 4231832, E-mail: [email protected] Abstract This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration and sampling phases. Results are applied to the design of high-speed low-power Σ∆ modulators and simplified equations are obtained for manual-estimation of the settling error power. 1. Introduction As sampling frequency in Σ∆Modulators (Σ∆Ms) increases in order to cope with XDSL specifications − demanding high-resolution high-speed low-power operation −integrator defective settling becomes one of the most limiting factors in present SC designs. In this scenario, knowing and quantifying the main mechanisms degrading the settling of SC integrators is therefore mandatory. Although most SC integrator models [1]-[5] take into account the amplifier finite gain-bandwidth product (GB) and slew-rate (SR), they do so only for the integration phase, while errors derived from the sampling dynamic are omitted, leading to an under-esti- mation of defective settling specially important in high-speed applications. The SC integrator model considered in [6] includes all former errors, but the developed study is centered on filter design and cannot be easily extended to the case of Σ∆Ms. This paper focuses on the analysis of the transient response of a general SC integrator model during both the integration and sampling phases, giving also compact expressions for a precise estimation of settling errors limiting the performance of high-speed Σ∆Ms. 2. Transient Response of SC Integrators 2.1. SC Integrator Model In order to make a reliable analysis of the transient response of SC integrators, the generic scheme considered, illustrated in Fig.1, includes: •iinput branches connected to switching input voltage levels, and , • the parasitic capacitor associated to the summation node, • the capacitive load associated to the amplifier output node and to the bottom plate of the integration capacitor , as well as, •jbranches of an assumed integrator connected to its output during the sampling phase, which has switched to input levels during the previous integration phase. On the other hand, the amplifier, depicted in Fig.2, is considered to have: Vi1Vi2 Cp Cl Co Vnj2 - + C o φ 1d φ 2 φ 2d C 1 V 11 V 12 φ 1 C p C l φ 1d φ 2 φ 2d C 2 V 21 V 22 φ 1 φ 1d φ 2 φ 2d C i V i1 V i2 φ 1 - + φ 1d φ 2 φ 2d C n1 V n12 φ 1 φ 1d φ 2 φ 2d C n2 V n22 φ 1 φ 1d φ 2 φ 2d C nj V nj2 φ 1 Fig. 1: SC integrator model. . . .. . . . . . vo va (*) This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580. • a non-linear static characteristic, providing a maximum output current , and • a single-pole dynamic. With this model for the SC integrator, the amplifier GB and SR limitations are taken into account, as well as parasitic capacitors associated to its input and output nodes. Moreover, capacitive load at the integrator output is considered to change from the integration to the sampling phase, what reflects the actual situation in most SC sections. 2.2. Integration Phase Considering respectively and as the amplifier input and output voltages at the end of the preceding sampling phase, at the beginning of the integration phase, , charge-conservation imposes a jump on these voltages to values (1) with and referring to the equivalent capacitive load at the amplifier output during the integration phase, given by (2) Note from eq.(1) that and jump at the beginning of this phase in the opposite direction to their final values (see Fig.3). It must be also remarked that, unlike previous models [1]-[5], we have considered , which reflects the possibility of having this node incompletely discharged by the end of the preceding sampling phase. Depending on the value of the initial amplifier input voltage two possibilities can be distinguished: (a) , where Iostands for the amplifier maximum output current and for its transconductance. The amplifier will then operate linearly and its input node discharges exponentially following (3) where has been supposed. (b) , so that the amplifier slews and its input node will then evolve linearly following: (4) The slewing will go on until , when the condition for the amplifier to start operating linearly, , fulfills. From this condition we get (5) and from then on will relax exponentially: (6) During the integration phase is given by (7) where stands for eq.(3), (6) or (4) depending, respectively, on the amplifier linear operation, partial- or complete-slewing in this phase. Attheendoftheintegrationphase, , and will be given by eq.(8). 2.3. Sampling Phase Taking and , respectively, as the amplifier input and output voltages at the end of the preceding integration phase, at charge-conservation imposes†a new jump on these voltages to (9) Io Vout V+ V- Io -Iogm(V+-V-)gout Fig. 2: Amplifier model. Cout van 1–,von 1–, t0= vai i, 1Cl Co ------+   Ceq i, --------------------- V12 V11 –()C1…+[= voi i,von 1–, Co CoCl + ------------------ vai i,van 1–, –()+= …Vi2Vi1 –()Ci]+C′ Ceq i, -------------van 1–, + C′CpCl1Cp Co -------+   += Ceq i, Ceq i,CpC1…Ci ++++= Cl +1 CpC1…Ci +++ Co --------------------------------------------+   vavo van 1–,0≠ vai i, Io gm ------ ≤ gm †. Forsimplicitypurposes,nextintegratorinputnodehasbeensupposed totally relaxed by the end of the preceding integration phase. vat() vai i, gm Ceq i, -------------t–   exp= gmgout » vai i, Io gm ------ > vat() vai i, Io Ceq i, -------------vai i, ()tsgn–= tt oi, = vatoi, ()Iogm ⁄= toi, Ceq i, Io -------------vai i, Ceq i, gm -------------–= vat() vat() Io gm ------ vai i, () gm Ceq i, -------------tt oi, –()–expsgn= vot() C1 Co ------ V12 V11 –()–…Ci Co ------–Vi2Vi1 –()+– 1CpC1…Ci +++ Co --------------------------------------------+   vat()+ vot() von 1–,1Cp Co -------+   van 1–, ––= vat() tT s2⁄=va vo vaTs2⁄()voTs2⁄() tT s2⁄= vai s,va Ts 2 -----  Cn1 Ceq s, -------------–vo Ts 2 -----  Vn12 –…–= voi s,vo Ts 2 -----   1Cp Co -------+   vai s,va Ts 2 -----   –+= …Cnj Ceq s, -------------–vo Ts 2 -----  Vnj2 – where refers to the equivalent capacitive output load during the sampling phase, given by (10) Note from eq.(9) that and again jump in the opposite direction to their final values (see Fig.3). Depending on the initial amplifier input voltage, two more possibilities can be distinguished: (a) , and the amplifier operates linearly: (11) (b) , so that the amplifier slews and its input node will then evolve linearly following: (12) The slewing will go on until , when fulfills and the amplifier starts operating linearly. From this condition we get (13) and from then on will relax exponentially: (14) During the sampling phase is given by (15) where stands for eq.(11), (14) or (12) depending, respectively, on the amplifier linear operation, partial- or complete-slewing during this phase. At the end of the sampling phase, , and will be given by eq.(16). 2.4. Overall Integration-Sampling Process The former study on the SC integrator dynamics in the integration and the sampling phases can be easily concatenated, so that the transient evolution of the integrator output voltage is accurately described for the overall integration-sampling process. Nine different evolutions can be obtained for the complete process, which are summarized in Table 1. The actual response the SC integrator follows, out of the nine possible‡, will mainly depend on the input signals level as well as on the amplifier static characteristics. Ideally, at the end of the process would be, (17) while the actual can be obtained for each possible evolution by the linking of its equations during the sampling phase to those of the preceding integration Ceq s, Ceq s,CpClCn1…Cnj +++()1Cp Co -------+   += vavo vai s, Io gm ------ ≤ vat() vai s, gm Ceq s, ------------- tTs 2 -----–   –exp= vai i, Io gm ------ > vat() vai s, Io Ceq s, ------------- vai s, ()tTs 2 -----–   sgn–= tt os, = vatos, ()Iogm ⁄= tos, Ts 2 ----- Ceq s, Io ------------- vai s, Ceq s, gm -------------–+= vat() vat() Io gm ------ vai s, () gm Ceq s, ------------- tt os, –()–expsgn= ‡. Although possible, evolutions 3 and 7 are unlikely to occur in practice, since they imply a huge change on the values of capacitors in the connected SC sections. vot() vot() vo Ts 2 -----   1Cp Co -------+   vat()va Ts 2 -----   –+= vat() tT s =va vo vo von,von 1–, C1 Co ------ V12 V11 –()…–Ci Co ------ Vi2Vi1 –()––= von, va Ts 2 -----   vai i, gm Ceq i, -------------Ts 2 ----- –   exp vai i, Io Ceq i, -------------vai i, () Ts 2 ----- sgn– Io gm ------ vai i, () gm Ceq i, -------------Ts 2 ----- toi, –   –expsgn            = Ts 2 ----- toi, >, Ts 2 ----- toi, ≤, vai i, Io gm ------ ≤, vai i, Io gm ------ >, vo Ts 2 -----   von 1–,1Cp Co -------+   van 1–, –C1 Co ------ V12 V11 –()–…Ci Co ------ Vi2Vi1 –()–1 CpC1…Ci +++ Co --------------------------------------------+   va Ts 2 -----   +–= (8) vaTs () vai s, gm Ceq s, ------------- Ts 2 ----- –   exp vai s, Io Ceq s, ------------- vai s, () Ts 2 ----- sgn– Io gm ------ vai s, () gm Ceq s, ------------- Tstos, –()–expsgn            = Tstos, >, Tstos, ≤, vai s, Io gm ------ ≤, vai s, Io gm ------ >, voTs () vo Ts 2 -----   1Cp Co -------+   vaTs ()va Ts 2 -----   –+= (16) phase (see Table 1). Every term obtained for the actual , different from those in eq.(17), derives from an incomplete settling, due to the amplifier finite GB and SR. Fig.3 shows an evolution with a partial-slewing during both clock-phases and illustrates the influence of the sampling dynamics. Considering only the integration phase would lead in this case to an under-estimation of the defective settling error, since the deviation of the settled voltage is higher at the end of the sampling phase than it was at the end of the integration phase. Equations for all nine cases match with HSPICE results with less than 1% error. 3. Application to Σ∆Ms Design 3.1. Comparison with Previous Models through Behavioral Simulations As the conversion rate increases to cope with specifications demanding high-resolution and high-speed operation, defective settling errors due to amplifiers finite GB and SR become one of the most limiting factors in present Σ∆Ms designs. Moreover, these must be achieved with a reduced power consumption, so that the amplifier dynamic features should be kept as less demanding as possible with no degradation on the modulator performance. This has been traditionally accomplished allowing a certain slewing on the amplifier [2][4], what relaxes the amplifier characteristics and does not imply a severe loss of dynamic range in the Σ∆M. Although amplifiers finite GB and SR are taken intoaccount in most SCintegratormodels [1]-[5], this only applies for the integration phase, omitting errors due to the sampling dynamic that become important as the operating frequencies increase. The new model for the SC integrator and the equations describing its transient response, developed in Section 2, have been introduced in ASIDES [4], a behavioral simulation tool for SC Σ∆Ms. Simulations have been carried out on a 12bit@4MSamples/s 2-13mb cascade Σ∆M [7], operating with sampling frequency fs= 32MHz, oversampling ratio M=8, last-stage quantizer resolution B= 4 and reference levels . Fig.4 shows a comparison of the in-band error power due to defective settling, , for both traditional and new models as a function of the amplifier transconductance. Note that not considering errors induced during the sampling phase gives too optimistic results, leading in this case to an under-estimation on of around 12dB. 3.2. Manual Estimations of Settling Error Power Integrators defective settling has generally been modeled in Σ∆Ms as an error source at the integrator input, so that only the first integrator in the modulator is considered in an approximated analysis. This can be done since the contribution of the rest of integrators to the in-band error power is attenuated by increasing powers of the oversampling ratio [4]. Fig.5 shows the deviation of the settled output voltage at the first integrator in the 2-13mb Σ∆M from its ideal value, eq.(17). This deviation approximates to a gaussian distribution when the input signal amplitude A approaches the reference voltage . Taking into account this and the equations formerly developed for the transient response of SC integrators, we will try to translate them into compact expressions for the settling error power in SC Σ∆Ms. von, TABLE 1: Possible evolutions during the integration-sampling process INTEGRATION SAMPLING 1 Linear eq.(3) Linear eq.(11) 2 Partial-slew eq.(6) Linear eq.(11) 3 Slew eq.(4) Linear eq.(11) 4 Linear eq.(3) Partial-slew eq.(14) 5 Partial-slew eq.(6) Partial-slew eq.(14) 6 Slew eq.(4) Partial-slew eq.(14) 7 Linear eq.(3) Slew eq.(12) 8 Partial-slew eq.(6) Slew eq.(12) 9 Slew eq.(4) Slew eq.(12) to,s 0102030 -0.2 0.0 0.2 0.3 -0.1 0.1 0.5 15 255 t(ns) vo(V) INTEGRATION SAMPLING to,i 0.4 Fig. 3: Transient evolution of integrator output voltage. Vr ±1V±= New model Traditional model 1.0 1.25 1.5 1.75 2.0 gm (mA/V) -120 -110 -100 -90 -80 -70 Pst (dB) Fig. 4: Comparison of models applied to a 2-13mb Σ∆M. (Vin = 0.5V, Io = 0.5mA, C1 = Cp = 0.5pF, Co = 2pF, Cl = 1pF, Cntot = 1.5pF) Pst Pst Vr The voltage that the integrator output settles to has been re-written in the following way, (18) mapping deviations into: • a hold-error on the initial output voltage, , • a gain-error, , and • an offset-error, , with . Although the obtaining of compact expressions has been done for all nine possible evolutions in the integration-sampling process, we will only consider the first case as an illustrative example. If the amplifier operates linearly during both clock-phases (case 1 in Table 1), the value of the former errors turns out to be, (19) where , , , and terms in and in have been neglected. The actual implementation of the first two integratorsin the 2-13mb Σ∆Mis shown inFig.6. When compared to the SC integrator model considered in Fig.1, we get that , and . In this situation, worst case will then occur for when ††,so that (20) • On the one hand, and can be considered as error sources that add to the modulator input signal and, therefore, are not attenuated in the baseband. Considering, as in [5], that these errors correspond to three times their standard deviation in a gaussian distribution, and that they are uniform in the range (-fs/2, fs/2), we get: (21) Integrating in the baseband, we get their contributions to the defective settling error power, -20 -10 0 10 20 0 100 200 300 400 500 600 Number of events (mV) von actual ,von ideal , – Fig. 5: Histogram of the error in settled voltage. (A = 0.75V, Vr = 1V) von,von 1–,1εo +() Citot Co ----------- vin 1εg +()ε off ++= εo εgεoff Citot Co -----------vin C1 Co ------–V12 V11 –()…–Ci Co ------–Vi2Vi1 –()= εg Citot Ceq i, -------------1Cl Co ------+  Ts 2τi -------–   –exp–= εo1Cp Co -------+   Cntot Ceq s, ------------- Ts 2τs --------–   exp–= 1Cp Co -------+   Cntot Ceq s, ------------- Ts 2τs --------–   exp– ††. Results will be analogous if V12 = Vn22 = Vr for vin < 0. εoff 1Cp Co -------+   Cn1Vn12 …C+n2jVnj2 + Ceq s, ----------------------------------------------------------------Ts 2τs --------–   exp= τiCeq i,gm ⁄=τsCeq s,gm ⁄= Citot C1…C+i += Cntot Cn1…C+nj += Ts 2τi -------–   exp Ts 2τs --------–   exp⋅ van 1–, V11 vin =V12 V=n22 Vr ±= Vn12 0= vin 0>V12 V=n22 Vr –= εg C1 Ceq i, -------------1Cl Co ------+  Ts 2τi -------–   –exp–= εoff 1Cp Co -------+   –Cn2 Ceq s, ------------- Vr Ts 2τs --------–   exp= εo1Cp Co -------+   Cntot Ceq s, ------------- Ts 2τs --------–   exp–= 1Cp Co -------+   Cntot Ceq s, ------------- Ts 2τs --------–   exp– εgεoff σg εg 3 -----vin =⇒Sgf() σg 2 fs ------εg 2 9fs -------- vin 2 == σoff εoff 3 ---------= ⇒Soff f() σoff 2 fs ----------εoff 2 9fs ---------== Fig. 6: Implementation of first and second integrators in the 2-13mb Σ∆M. - + Co φ1dφ2 φ2d C1 vin φ1CpCl- + φ1dφ2 φ2d Cn1 φ1 φ1dφ2 φ2d Cn2 φ1 gm, Io Vr ± Vr ± (22) where A is the input signal amplitude. • On the other hand, error translates into a memory error that will basically affect the noise transfer function of the modulator. Considering only this error term, the integrator output at the end of the integration-sampling process will be, (23) where . The integrator transfer function will then be, (24) so that the following expression, valid for cascade Σ∆Ms [4], can be derived for its contribution to , (25) where is the quantization step of the comparator inthe first-stage of the cascadeand L1is the first-stage order. For the 2-13mb Σ∆M, this leads to: (26) The total in-band error power due to defective settling will then finally be given by: (27) A comparison between simplified equations and results obtained by behavioral simulation in ASIDES is carried out in Fig.7 for a wide range of variation on the amplifier transconductance and its input parasitic. Note the high agreement of the obtained . Moreover, simplified equations present the additional advantage of being a bit conservative when compared to more accurate behavioral simulation results, what may be very practical for a hand-made estimation of the required integrator dynamics. References [1] W. M. C. Sansen, H. Qiuting and K. A. I. Halonen: “Transient Analysis of Charge Transfer in SC Filters - Gain Error and Distortion”. IEEE Journal of Solid-State Circuits, vol. 22, n. 2, pp. 268-276, April 1987. [2] L. A. Williams and B. A. Wooley: “A Third-Order Sigma-Delta Modulator with Extended Dynamic Range”. IEEE Journal of Solid-State Circuits, vol. 29, n. 3, pp. 193-202, March 1994. [3] F. Wang and R. Harjani: “Nonlinear Settling Behavior in Oversampled Converters”. Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 23.6.1-4, May 1997. [4] F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez: “Top-Down Design of High-Performance Sigma-Delta Modulators”. Kluwer Academic Publishers, Boston, November 1998. [5] V. F. Dias, G. Palmisano, P. O’Leary and F. Maloberti: “Fundamental Limitations of Switched-Capacitor Sigma-Delta Modulators”. IEE Proceedings-G, vol. 139, pp. 27-32, February 1992. [6] A. Robertini: “Linear and Nonlinear Distortion in SC Circuits Due to Nonideal Amplifiers and Switches”. Hartung-Gorre Verlag, Konstanz, 1991. [7] R. del Río, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez: “High-Order Cascade Multi-bit Σ∆ Modulators for High-Speed A/D Conversion”. Proc. Design of Circuits and Integrated Systems Conf. (DCIS), pp. 76-81, Madrid, November 1998. 1Cp Co -------+   +Cntot Ceq s, ------------- Ts 2τs --------–   exp 2 Poff Vr 2 9M -------- 1Cp Co -------+   2Cn2 Ceq s, -------------   2Ts τs -----–   exp= PgA2 9M -------- C1 Ceq i, -------------1Cl Co ------+  Ts 2τi -------–   +exp= ε o von,von 1–,1εo +()g1vin n,1– += g1C1Co ⁄= voz() vin z() -------------- g1z1– 1z1– 1εo +()– ------------------------------------= Pst Po ∆1 2 12 ------π2L12– L1 2L11–()M2L11– ------------------------------------------- εo 3 -----   2 ⋅= ∆1 Po 2Vr 2 27 ----------= π2 3M3 -----------1Cp Co -------+   2Cntot Ceq s, -------------   2Ts τs -----–   exp⋅⋅ Pst PoP+gPoff += Pst Fig. 7: Comparison of simplified equations and behavioral simulation results for the 2-13mb Σ∆M: (a) Variation of gm(Vin = 0.5V, Io= 0.75mA, C1= 0.5pF, Co= 2pF, Cl= 1pF, Cp= 1.5pF, Cntot = 2pF) (b) Variation of C p (Vin = 0.6V, gm= 2mA/V, Io= 0.25mA, C1= 0.5pF, Co= 2pF, Cl= 1pF, Cntot = 1pF) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Cp (pF) -120 -110 -100 -90 -80 -70 -60 -50 Pst (dB) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 gm (mA/V) -110 -100 -90 -80 -70 -60 -50 -40 -30 Pst (dB) ASIDES Simplified eqs (b)(a) ASIDES Simplified eqs