A Low-Voltage Floating-Gate MOS Biquad

VLSI DESIGN 2001, Vol. 12, No. 3, pp. 407-414 Reprints available directly from the publisher Photocopying permitted by license only (C) 2001 OPA (Overseas Publishers Association) N.V. Published by license under the Gordon and Breach Science Publishers imprint, member of the Taylor & Francis Group. A Low-Voltage Floating-Gate MOS Biquad ESTHER O. RODRGUEZ-VILLEGAS*, ALBERTO YIIFERA and ADORACION RUEDA Instituto de Microelectrbnica de Sevilla (IMSE), Centro Nacional de Microelectrbnica (CNM), Edificio CICA, 4vda. Reina Mercedes s/n, 41012-Sevilla, Spain (Received 20 June 2000; In final form 3 August 2000) A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage supply with a full differential input linear range and a THD below 1%. Programming and tuning are performed by means of a single voltage signal. The transconductor incorporates a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS transistors. Keywords: Analog low-voltage low-power filters; FGMOS circuits I. INTRODUCTION Low Power (LP) and Low Voltage (LV) circuits are nowadays extensively demanded by the market of portable applications (computers, phones, biomedical implants) [1]. This is leading the circuit design philosophy to environments where the scaling down of the power supply is continuously decreasing, but where the circuit performance must be also retained. Filters are building blocks appearing on demanded LP/LV products. Continuous Time Filters (CTF) could be a good choice versus the sampled-data filters alternatives, because they avoid the pre and post-aliasing filters. Also, they reduce the components spread (capacitors, current gains, etc.) if large time constants, as in audio-frequency applications are required. One of the main drawbacks of CTF is that tuning processes are necessary due to technological process variations, but on the contrary clock-noise is absent. Continuous Time Filters performance is directly related to the continuous time integrator quality measured in terms of power consumption, linearity, noise, phase response and tunability as main parameters. In the context of L V/LP circuits, some contributions have been reported. Looking at the technology capabilities, a first approximation could classify them in bipolar, BiCMOS or CMOS designs. Totally bipolar realizations can work at * e-mail: [email protected] Corresponding author. Tel.: + 34-955056666, Fax: + 34-955056692, e-mail: [email protected] e-mail: [email protected] 407 408 E. O. RODRGUEZ-VILLEGAS et al. L V [2, 3], until V of supply voltage [3]. The best performance in terms of power efficiency and dynamic range for LP/LV CTFs has been proved for these technological realizations in [4, 5]. This optimal performance is obtained with a non-linear integration method preserving linear input-output relationship (companding technique [6]). They seem to be a good candidate for low-voltage high-frequency operation [7], although good results have been also obtained in the audio frequency range [8]. CMOS realizations are based on biasing transistors at strong inversion, on saturation [9-11] or linear [12, 13] region, and also in weak inversion mode [14-16]. Companding realizations can be found in CMOS technologies, being possible to be ruled either by squared-root [11] or by logarithmic [15, 16] laws, unlike bipolar designs. This fact makes possible to distinguish between so called log-filters and x/- filters. The BiCMOS technologies make compatible the reduced voltage swing for bipolar transistors with MOST working at linear region. In Refs. [17, 18] circuit techniques are used to limit the drain-to-source voltage on MOST. In this paper, a biquad based on a new transconductor realization is presented. The circuit is based on the FGMOS transistor principle [19- 20]. The use of this technique makes easy the voltage-down process without degrading the circuit performance parameters. The specifications are focused on the audio frequency range. Large time-constants for low frequencies (some tens of Hz) need low gm/C ratios, which forces to low transconductance values and large integrating capacitors as well as high output resistance. The transconductor has good programming and tuning characteristics. Fully balanced input-output operation has been used in order to reduce distortion, so the proposed transconductor includes a new common-mode feedback circuit (CMFB). The common-mode feedback circuit presented also exploits the processing capabilities of the FGMOS technique. The simulation results obtained are compared to other audio-frequency filter realizations. II. FGMOS BASIC PRINCIPLE In the FGMOS technique exposed in [19], the drain-to-source current characteristic of a MOS transistor is externally modified by adding a set of capacitors connected to the gate terminal as shown in Figure l(a). Here, the FGMOS transistor has Vi (i= 1,2,...,n) input voltages. Ci are the input capacitors, Cox the floating-gate oxide capacitance, and CFD, CFS and CFS the overlap capacitances between the floating-gate to the drain, source and bulk respectively. The equivalent circuit and schematic are shown in Figures l(b) and (c), respectively. The drain-to-source current in saturation if CF9, CFS <<Cr is given by, Io n wiVi + wnVn wsVs wrVth (1) i=1 where fin is the transconductance parameter, Vth is the nominal transistor threshold voltage, Vs and Vs the body and source voltages respectively. The weights in Eq. (1) are defined as: wi=Ci/Cr, WB-- CFB/CT, WS= [1 --(CFB/CT)-- 2/3(Cox/Cr)], WT=[1--2/3(Co/CT)], being CT the total capacitance seen from the floating gate. Let us consider the three-input FGMOS case, where V1 is the input signal (V i,,- V), and V and V3 are bias voltages (V bE V2 and Vb3 V3). For Vs Vs- 0, the following expression results from Eq. (1), ID --/n(Wl Vl -[" w2V2 + w3V3 Vth) 2 (2) in which, the drain-current is given as a quadratic dependence of input voltages’ weighted sum. s cc... Cn o I "q T T6W F-" v. h o J v,4 (a) () FIGURE Floating-Gate MOS (FGMOS) transistor: (a) Capacitors model. (b) Equivalent circuit. (c) Schematic. FGMOS CIRCUITS 409 When C1 Cox, Eq. (2) can be rewritten as, C (gin- Vtth 2 ,o (3) where, C2 C3. (Vth Vb3) (4) Vth Vth "-[--11" (Vth Vb2)-’[--11 This expression enables the reduction of the threshold voltage seen from the input terminal (V1). In order to obtain this, it must be fulfilled that Vb2 > Vth and/or Vb3 > Vth. The magnitude of the reduction is controlled by the input capacitor ratios Ci/C1 (i 2, 3). As consequence, the requirements for voltage-down are less restrictive. If C1 C2-- C3 and Vz V3 1.5 Vth, a V;h 0 is obtained. Equation (2) can be also interpreted as follows: the FGMOS transistor has two inputs, Vin+ V1 and Vgn-= V2, and a bias signal, Vb3 V3. The inputs are symmetrical with respect to the common mode level (Vcm Via and its weights are equals, C1 C2. The result for this selection is, C1 Io fln c--y Vcm V’th (5) where the a threshold voltage, C3. (Vth Vb3) (6) V;h V,h + smaller than Vth can be obtained if Vb3 > Vth. The operation expressed in (5) represents the calculus of the mean value of the two input signals through the gate-to-source voltage of a MOST. This gate- to-source voltage is equal to the voltage commonmode value, with a threshold voltage controlled by Vb3. This sensing method for the Vcm voltage can be used for common-mode correction via feedback or feedforward circuits. In the following section, these two basics interpretations of the floating-gate MOS transistor operation are applied to build the transconductor used in the biquad filter we propose to show the feasibility of FGMOS-based implementations. llI. FILTER IMPLEMENTATION The proposed gm-C integrator is shown in Figure 2 [21]. The transconductor is a pseudo-differential pair composed of M1-M4, with M9-M10 as active load and a CMFB circuit which will be described later on. The M1-M4 three-input FGMOS transistors work as a two cross-coupled pair, giving a current defined by (Is-I2) or (Ii-Is), being I1+I2=2Is, and Is the bias current. The aspect ratios and input capacitors for these transistors are the same, being different the bias voltages, Vbl and Vb2. When transistors are in saturation region, the output current is calculated as, IL 2flnCinCc(Vb2 Vbl C2 T Vin Vin2 (7) where fin is the transconductor parameter #nCoxW/L, Cin is the input capacitance connected to Vnl,2, and Cc the control capacitor connected to Vbl and Vb2 respectively. Cr is the total capacitance seen from a floating gate. The large signal transconductance, Gm 2flnCinCc(gb2 Vbl (8) can be easily tuned through the (Vb2-- Vbl) factor. Values of negative resistances can be also obtained VDD M9 MlO Voutl MI casn FIGURE 2 Fully-differential FGMOS integrator. 410 E. O. RODRiGUEZ-VILLEGAS et al. if necessary. Capacitor and voltage biasing value are selected in agreement with Eq. (4) in order to reduce the input voltage levels and maintaining MOST on saturation and strong inversion. The schematic of the CMFB circuit used is represented in Figure 3. It is composed of a differential pair (M12, M13) with diode-connected transistors as loads (M14,M15). The FGMOS pair has the same total input capacitance (CT, lZ=CT,13), and all the capacitors have the same value. The constant reference voltage (Vzz/ 2) is obtained from the mean value of Voz and ground. According with Eq. (5), the current through M13 is, ( )2 Vdd 1013 n --- Vh (9) where the new threshold voltage, for equal input capacitors at Vzz and gnd inputs is, Vth Vth + Vs (10) which is compared with the equivalent gate voltage at M12. The V is the common source voltage of the differential pair. The drain current in this case is, ID12 tn(Vcm V’tth) 2 (11) where the new threshold voltage is the same as M13 given in Eq. (10). The differential pair will be unbalanced when the common-mode level is not zero (for symmetrical power supplies), sensing the Vcm, Olt common-mode voltage level. The output of this circuit is connected to the transconductor bias current and a capacitor input of the cross-coupled input pair to obtain a negative feedback. The common-mode voltage level can be easily defined by the capacitor ratios at the CMFB circuit. The transconductor has been used as basic block for a second order Tow-Thomas filter. The schematic of this block is shown in Figure 4. The equations describing filter operation are: VBp(S) S" (gml/C1) Vin(S) S 2 t_ S" (gm2/C1) -- (gm3gm4/CIC2) (12) VLp(S) (gmlgm3)/(C1C2) Vin(S) s 2 -a ts" (gm2/C1) q- (gm3gm4/C1C2) (13) where the typical filter parameters of a second order section are, ,/gm3gm4 o V 122 (14/ Q V/gm3gm4 C1/C2 gin2 (15) being o and Q the cut-off frequency and the quality factor, respectively. Using Eqs. (14)- (15), the Wo and Q tuning can be performed through control voltages Vbl and Vb2 as shows Eq. (8). C1 FIGURE 3 Common-mode feedback circuit. FIGURE 4 Tow-Thomas biquad. FGMOS CIRCUITS 411 IV. RESULTS The design of a filter illustrating the circuits described before has been focused for low-voltage audio applications. The time constant required are in the range of [10ms, 25 ts] for frequencies between 100 Hz to 40 KHz respectively. These time constants can be implemented by choosing the adequate transconductance to capacitance ratio (gm/2rCi-1, 2) in Eqs. (12)-(13). The lowest time constant imposes large capacitor values, so a trade-off between capacitor area and Gm value is necessary. For Ci= 5 pF and a frequency range between 100 Hz and 10 KHz gm is located between 0.31S and 3nS. Cascode transistor structures were used at the outputs to increase the output resistance. The M1 M4 transistors are W/L=2.5tm/lOtm, with capacitance values of 150 fF, 250 fF and 600 fF for the inputs. The M12 and M13 aspect ratio is 2.5 tm/17 lxm, with input capacitances of 133 fF, and the total capacitance is 0.533 fF. Electrical simulations have been performed in a 0.8 lxm CMOS technology, with nominal threshold voltages of Vtn=0.85V and Vtp=-O.75V. BSIM3v2 models have been used for MOST. Figure 5 shows simulation results for the output current (IL) versus the differential input voltage for several values of the control voltage (Vb2-- Vbl). In both, the high linearity of the transconductor and 200m V/div }’" :: :::::::::::: ::::::::::::::::::::::::: 200m V/div FIGURE 5 Gm-tuning: (a) for (Vb2-- Vbl 0.2, 0.3 and 0.4V and (b) for (Vb2-- Vbl 4, 14 and 24mY. 0.8 Gml =3nS 12.6 0.5 1.0 1.5 2.0 Vd [W (a) 1.0 0.8 0.6 0.4 0.2 Gm2=3OOnS 0.5 1.0 1.5 2.0 Vd IV] (b) FIGURE 6 THD versus peak-to-peak input range: (a) for Gm= 3 nS and (b) for Gm-" 300 nS. 412 E. O. RODRGUEZ-VILLEGAS et al. the extremely wide input voltage range can be observed. The results obtained with this graphic agree with Eq. (8). The low distortion has been confirmed by transient analysis. The THD obtained for gml 3 nS and gm2--300nS are shown in Figures 6(a) and (b) respectively. Both have been calculated at the edges of the input Common- Mode Range (Vcm, min 0 V, Vcm, max 0.8 V ). The total THD is always below 1%. Finally, in Figure 7, the bandpass and lowpass filter transfer function have been obtained for two values of the cut-off frequency and the quality (a) 0dB OdB 1KHz 1KHz 10KHz 100KHz (b) Frequency FIGURE 7 (a) Q-tuning and (b) Wo-tuning for both band-pass and low-pass filter transfer-functions. FGMOS CIRCUITS 413 TABLE Summary of transconductor HSPICE simulations gml 3 nS gin2 300 nS Vsupply v(v) CMR THD@2 V Power 2V 1.6 2V 2V 0.8 V 0.8 V <1% lOtW factor. Table I summarize the performance of the transconductor for the maximum and the minimum transconductance values. V. CONCLUSIONS A L V/LP filter implementation based on a new FGMOS transconductor has been presented. The transconductor uses FGMOS to decrease the supply requirements as well as to tune the filter cut-off frequency, obtaining a full range differential input voltage and two decades for frequency tuning. Harmonic distortion is always below one per cent for all input values. The voltage common-mode correction is performed also by calculating its possible swing by means an FGMOS differential pair. The feasibility of the block has been illustrated with a second order Tow-Thomas biquad. The obtained results agree with expectations, and propose a close solution for low voltage, low frequency applications with the FGMOS technique. Acknowledgment This work is supported in part by the CICYT Spanish project No.:TIC-97-0648. References [1] Plassche, R. V., Sansen, W. and Huijsing, J. H. (Eds.), "Analog Circuit Design: Low-power Low-voltage, Integrated filters and smart power", Kluwer Academic Publ., 1995. [2] Koyama, M., Ara, T., Tanimoto, H. and Yoshida, Y., "A 2.5 V Active Low-Pass Filter Using all n-p-n Gilbert Cells with a 1-Vpp linear Input Range", IEEE Journal of Solid- State Circuits, 28, 1246-1252, Dec., 1993. [3] Tanimoto, H., Koyama, M. and Yoshida, Y., "Realization of a V Active Filter Using Linearization Technique Employing Plurality of Emiter-Couple Pairs", IEEE Journal of Solid-State Circuits, 26, 937-945, Jul., 1991. [4] Punzenberger, M. and Enz, C., "A 1.2V Low-Power BiCMOS Class AB Log-Domain Filter", IEEE Journal of Solid-State Circuits, 32, 1968-1978, Dec., 1997. [5] Punzenberger, M. and Enz, C., "A Compact Low-Power BiCMOS Log-Domain Filter", IEEE Journal of Solid- State Circuits, 33(7), 1123-1129, Jul., 1998. [6] Frey, D. R., "Log-domain filtering: an approach to current-mode filtering", Proceedings lEE, 140, Pt. G, No. 6, 406-416, Dec., 1993. [7] Frey, D. R., "Log Domain Filtering for RF Applications", IEEE Journal of Solid-State Circuits, SC-31(10), 1468 1475, Oct., 1996. [8] Serdijn, W. A., Broest, M., Mulder, J., van der Woerd, A. C. and van Roermund, A. H. M., "A Low-Voltage Ultra Low-Power Translinear Integrator for Audio Applications", IEEE Journal of Solid-State Circuits, 32, 577-581, Apr., 1997. [9] Zele, R. H. and Allstot, D. J., "Low-Power Continuous- Time Filter", 1EEE Journal of Solid-State Circuits, 31, 157-168, Feb., 1996. [10] Kaiser, A., "A Micropower CMOS Continuous-Time Low-Pass Filter", IEEE Journal of Solid-State Circuits, 24(3), 736-743, Jun., 1989. [11] Mulder, J., van der Woerd, A. C., Serdijn, W. A. and van Roermund, A. H. M., "Current mode companding x/Y- domain integrator", Electronics letters, 32(3), 198-199, Feb., 1996. [12] Wang, Y., Uehara, G. T. and Ren, M. (1998). "A 3 V High-Bandwidth Integrator for Magnetic Disk Read Channel Continuous-Time Filtering Applications", IEEE Custom Integrated Circuits Conference, pp. 427-430. [13] Yoo, C., Lee, S. and Kim, W., "A 4- 1.5V, 4-MHz CMOS Continuous-Time Filter with a Single-Integrator Based Tuning", IEEE Journal of Solid-State Circuits, 33(1), 18-27, Jan., 1998. [14] Yfifera, A. and Rueda, A., "Programmable Low-Voltage Continuous-Time Filter for Audio Applications", IEEE International Symposium on Circuits and Systems, Orlando (USA), pp. 200-203, May, 1999. [15] Toumazou, C., Ngarmnil, J. and Lande, T. S., "Micropower log-domain filter for electronic cochlea", Electronics letters, 30(22), 1839-1841, Oct., 1994. [16] Python, D., Puzenberger, M. and Enz, C., "A 1-V CMOS Log-Domain Integrator", IEEE ISCAS’99, II, 685-688. [17] Rezzi, F., Baschirotto, A. and Castello, R. (1995). "A 3 V 12- 55 MHz BiCMOS Continuous-Time Filter with Pseudo-Differential Structure", ESSCIRC, pp. 74-77. [18] Yang, F. and Enz, C. C., "A Low-Distortion BiCMOS 7th-order Bessel Filter operating at 2.5 V Supply", IEEE Journal of Solid-State Circuits, 31, 321-330, Mar., 1996. [19] Shibata, T. and Ohmi, T., "A Functional MOS Transistor Featuring Gate Level Weighted Sum and Threshold Operations", IEEE Trans. on Electronics Devices, 39(6), 1444-1455, Jun., 1992. [20] Rodriguez, E. O., Quintana, J. M., Avedillo, M. J. and Rueda, A., "Sorting Networks Implemented as VMOS Circuits", Electronics letters, 34(23), 2237-2238, Nov., 1998. [21] Rodrlguez, E. O., Ytlfera, A. and Rueda, A., "A gm-C Floating-Gate MOS Integrator", IEEE International Symposium on Circuits and Systems, IV, 153-156, June, 2000. 414 E. O. RODRGUEZ-VILLEGAS et al. Authors’ Biographies Esther Rodriguez-Villegas received the B.S. degree in Electronics from the University of Sevilla, Spain in 1996. Since 1997 she is in the Institute of Microelectronics at Seville (IMSE) where is currently working toward the Ph.D. degree. Her main research interests are the design of Floating-Gate circuits for both digital and analog applications. Alberto Ydfera joined the Department of Electronics and Electromagnetism at the University of Seville in 1988 as Assistant Professor, and obtained the Ph.D. degree in 1994. Since 1991 he is Associate Professor in the Department of Electronic Technology at the University of Seville. In 1989 he became researcher at the Department of Analog Design of the National Microelectronics Center (CNM), now Institute of Microelectronics at Seville (IMSE). He has participated in several research projects financed by the Spanish CICYT and in ESPRIT Projects. He has published several technical papers in main international journals and conferences. His current research interests include analysis and design of analog integrated circuits and systems for signal processing, and development CAD tools for analog circuits. Adoraci6n Rueda joined the Department of Electronics and Electromagnetism at the University of Seville in 1976 as Assistant Professor, and obtained the Ph.D. degree in 1982. From 1984 to 1996 she was Associate Professor in that Department, where now holds the position of Professor in Electronics. In 1989 she became researcher at the Department of Analog Design of the National Microelectronics Center (CNM), now Institute of Microelectronics at Seville (IMSE). She has participated in several research projects financed by the Spanish CICYT or by the European Community. She has also published several technical papers in main international journals and conferences, and she won the Best Paper Award of the 10th IEEE VLSI Test Symposium in 1992. Her current research interests are design and test of analog and mixed analog/digital circuits, and development of CAD tools. She is member of the Institute of Electrical and Electronic Engineers. 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