Error control in simplification before generation algorithms for symbolic analysis of large analogue circuits

Error control in simplification before generation algorithms for symbolic analysis of large analogue circuits J.D. Rodriguez-Garcia, 0. Guerra, E. Roca, F.V. Fernandez and A. Rodriguez-Vazquez Circuit reduction is a fundamental first step in addressing the symbolic analysis of large analogue circuits. A new algorithm for simplification before generation is presented which is very efficient in terms of speed and the amount of circuit reduction, and solves the accuracy problems of previously reported approaches. Introduction: One of the main drawbacks to symbolic analysers concerns the exponential increase in expression complexity with circuit size. On the one hand, this makes the symbolic results very difficult to use. On the other hand, it imposes a drastic limitation on the maximum size of circuit that can be analysed. In recent years, this drawback has been partially overcome through the use of techniques for simplification before (SBG) and during (SDG) generation [ 1, 21. SBG techniques simplify the system of equations (either in matrix or graph form) before solving it [3 - 51. Although the reported SBG approaches exhibit significant differences, they share the feature that the error induced by the elimination of an entry in a matrix, or by the removal of a branch or the contraction of a node in a graph, is evaluated at either one single frequency or a finite number of frequencies. Therefore, accuracy is not guaranteed at frequencies other than the sampling frequencies, as Fig. 1 illustrates. This Figure displays the magnitude and phase errors induced by the application of SBG to the integrator of Fig. 2a. The magnitude and phase error specifications were Alq 5 +5dB and A$H 5 k5O in the frequency range 1Hz 5 f 5 100MHz. As Fig. 1 shows, the error specifications are met at the sampling frequencies, but exceeded at intermediate frequencies. The methodology in this Letter solves this problem by introducing error evaluation mechanisms which guarantee the required accuracy at any frequency within a given range. 6, _________---- -4 -6 7 10 10 10 frequency,Hz 1621111 Fig. 1 Magnitude and phase errors of Fig. 2a at I MHz If I lOOMHz due to application of SBG algorithm A sampling frequencies New SBG methodology: Our approach involves replacing those elements whose contribution to the network function is small by either an open circuit (device removal) or a short circuit (node contraction). The objective is to find the sequence of node contractions and device removals yielding the simplest circuit in which errors are kept below some threshold. In our methodology, node contractions are given priority over device removals as the computational complexity of the posterior (SDG-based) solution algorithms increases much more quickly with the number of circuit nodes than with the number of devices. First of all, the algorithm calculates the contribution to the transfer function of the contraction of the terminal nodes of each individual device. The least significant contraction is chosen and the induced magnitude and phase errors are evaluated. If the allowed error is not exceeded, node contraction is carried out and all devices connected in parallel are removed. The contraction process continues iteratively with the next least-significant one while the accumulated magnitude and phase error does not exceed the specified maximum error. When the contraction process is finished a similar operation for device removal is perfornied. As explained above, both the node contraction and device removal processes start with an evaluation of the contribution of each possible contraction or removal. This means that the maximum difference in magnitude and phase between the original circuit and a modified circuit in which a pair of nodes have been contracted or a device has been removed must be evaluated. Also, after each node contraction is performed, a check must be made to determine if the maximum difference in magnitude and phase between the original circuit and the reduced circuit, in which the contraction at hand, together with all previously accepted contractions, has been performed, exceeds the error specifications. A similar test must be performed when each device removal is attempted. HJs) denotes the network function of the complete circuit with only the complex frequency s as symbolic parameter, and Hap($ the corresponding network function of a simplified circuit in which the appropriate node contraction(s) and/or device removal(s) have been performed. The magnitude and phase errors are given by Therefore, evaluation of the maximum magnitude and phase errors requires the calculation of: (a) the network functions H,(s) and H&) of (usually large) analogue circuits; and (b) the maxima of eqn. 1 when o varies within a given interval. The frst problem can be solved by means of numerical interpolation techniques. An efficient interpolation technique able to handle large analogue circuits can be found in [6]. Our solution for the second problem is based on the use of interval analysis techniques [7]. AlH and A&, in eqn. 1 are functions in o, which can take any value within the frequency interval [oL, mu]. The problem is solved if accurate estimates of the interval bounds of AI4 and AQH, when o E [o,, o,] can be calculated. This computation, commonly known as the interval extension of Alff and A$H, can make use of interval arithmetic operators. Substitution of the real variable o in eqn. 1 and real operators (addition, product, quotient, etc.) by the corresponding interval variables and operators yields the so-called natural interval extension [I. Unfortunately, this computation usually overestimates maximum errors [8]. a' 'b Fig. 2 Integrator, transistor model and CMOS opamp a Integrator b Transistor model c CMOS opamp To solve this problem, the natural interval extension is applied to the derivatives of eqn. 1. Although the interval widths of the derivatives are also overestimated, the zero inclusion in the resulting interval extension is sufficient for delimiting the frequency subranges in which the maximum magnitude and phase errors occur. 260 ELECTRONICS LETTERS 18th February 1999 Vol. 35 No. 4 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 26,2020 at 16:03:57 UTC from IEEE Xplore. Restrictions apply. Then, the exact frequency points for which the maximum magnitude or phase errors occur in those frequency subranges are easily calculated using the Newton-Raphson method. 0 2 4 6 10 10 10 10 frequency,Hz frequency,Hz Fig. 3 Magnitude and phase diagrams of Fig. 2c before and after application of SBG algorithm Experimental results: The accuracy and complexity reduction capabilities of the proposed methodology are illustrated through the circuit of Fig. 2c with the transistor model of Fig. 2b. By applying our SBG technique, the number of nodes in the smallsignal model was reduced from 26 to 8 and the number of devices from 253 to 26 in only 11s of CPU time. Magnitude and phase deviations were also kept within the prescribed margjns: Alff < k3dB and A$,, 5 ?So, as Fig. 3 shows. Because of the significant complexity reduction achieved, the circuit was manageable using our SDG algorithm, which provided the following approximated expressions for the transfer function: VOUT A, = - U- = [ - Gm14GmgGm13(Gm6 + GmlZ)(GmAl + GmAZ) - G~I~G~~G~GG~A~G~II] / [Gds12Gds14Gm8(Gm5 + Gmll)(GdsAl + GdsA2) + Gm14Gds~Gds~(Gm5 + Gmll )GdsA2 + Gml4Gm~Gds8Gdsl4Gds~2 +s(C,~+C,Z)G,~~G,S(G,~+G~~~)(G~A~ +G~Az)] Conclusions: In this Letter we have has demonstrated the possibility of generating very compact, interpretable expressions for the main behaviour characteristics of even large building blocks, while maintaining accuracy. Acknowledgments: This work was supported by the EEC ESPRIT Project #21812 (AMADEUS) and the Spanish C.I.C.Y.T. under contract TIC97-0580. 0 IEE 1999 Electronics Letters Online No: 19990235 DOI: IO. IO49/el:I 9990235 J.D. Rodriguez-Garcia, 0. Guerra, E. Roca, F.V. Fernandez and A. Rodriguez-Vazquez (Instituto de Microelectrdnica de Sevilla, Centro Nacional de Microelectrdnica. Avda. Reina Mercedes s/n. E-41012 Sevilla, Spain) 4 November 1998 References 1 FERNANDEZ E.V., RODRiGUEZ-VAZQUEZ A., HUERTAS J.L., and GIELEN G.: ‘Symbolic analysis techniques. Applications to analog design automation’ (IEEE Press, Piscataway, NJ, 1998) 2 WAMBACQ, P., FERNANDEZ, F.v., GIELEN, G., SANSEN, w., and RODRIGUEZ-VAZQUEZ, A.: ‘Algorithm for efficient symbolic analysis of large analogue circuits’, Electron. Lett., 1994, 30, (14), pp. 1108- 1109 HSU, J.-J., and SECHEN, c.: ‘Fully symbolic analysis of large analog integrated circuits’. IEEE Custom Int. Circuits Conf. Proc., San Diego, CA, 1994, pp. 21.4.1-21.4.4 3 4 SOMMER, R., HENNIG, E., DROGE, G., and HORNEBER, E.H.: ‘Equationbased symbolic approximation by matrix reduction with quantitative error prediction’, Alta Frequenza, 1993, 5, (6), pp. 3 17-325 5 YU, Q., and SECHEN, c.: ‘A unified approach to the approximate symbolic analysis of large analog integrated circuits’, IEEE Trans., 1996, CASI-43, (8), pp. 656669 RODR~GUEZ-VAZQUEZ, A.: ‘Symbolic analysis of large analog integrated circuits: the numerical reference generation problem’, to be published in IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., 1998, 45, (lo), pp. 1351-1361 7 MOORE, R.E.: ‘Methods and applications of interval analysis’. SIAM, Philadelphia, 1979 HUERTAS, J.L.: ‘Formula approximation for flat and hierarchical symbolic analysis’, Analog Integrated Circuits Signal Proc., 1993, 3, pp. 43-58 6 FERNANDEZ, F.V., GUERRA, O., RODRIGUEZ-GARCiA, J.D., and 8 FERNANDEZ, F.V., RODRIGUEZ-VAZQUEZ, A., MARTIN, J.D., and Improvements in hierarchical symbolic tolerance and sensitivity analysis F. Eberhardt, W. Tenten and P.R. Shepherd Sensitivity and tolerance analyses are important for circuit optimisation, but unfortunately very time consuming. In recent years new hierarchical symbolic methods have been developed for large linear circuits. These approaches make symbolic techniques a worthwhile altemative to classical numerical methods. Using the hierarchical symbolic approach, a new strategy is introduced which si&icantly reduces the computational expense of sensitivity and tolerance analyses compared to previous procedures. Introduction; Let H(s, 3 denote the transfer function of the circuit where s is the Laplace variable and X is the set of circuit parameters. The tolerances of H caused by variations of the parameters can be measured by determining the small change sensitivity (gradient) and large change sensitivity (step changes). Classical numerical methods for determining the sensitivities [l, 21 are only valid for small change sensitivity and require a complete new solution of the system matrix at each frequency point. Symbolic analysis provides a good altemative for tolerance investigations, especially when the number of fiequency points is large [3]. In recent years hierarchical symbolic analysis methods [4, 51 have been developed. The benefit of the hierarchical approach is that the computational expense has a linear up to quadratic dependence on the circuit complexity as opposed to the exponential nature of classical symbolic analysis. Consequently, much larger circuits can be described. The purpose of this Letter is to introduce a hierarchical symbolic sensitivity analysis method which significantly minimises the computation time compared to previous procedures, especially when the influence of many or all parameters is investigated. , a b 774 Fig. 1 Hierarchical network partitioning and binary partition tree a Hierarchical network partitioning b Binary partition tree Hierarchical symbolic analysis: The symbolic analysis in [SI is based on a hierarchical partitioning of the circuit. This partitioning process is modelled by a binary partition tree (Fig. 1). The system matrices of the circuit blocks are calculated starting with the leaves of the tree and proceeding from the bottom up. The result is a sequence of expressions (SOE) for the network function H: H1 = f(s,X), H2 = f(s,X,H1),..., H = Hk = f(s,X, Hi, ..., Hk-1) (1) ELECTRONICS LETTERS 18th February 1999 Vol. 35 No. 4 261 Authorized licensed use limited to: Universidad de Sevilla. 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