Neuro-fuzzy chip to handle complex tasks with analog performance

0 Neuro-Fuzzy Chip to Handle Complex Tasks with Analog Performance Fernando Vidal-Verdú Dto.Electrónica-Universidad de Málaga Complejo Tecnológico, Campus Teatinos 29071 Málaga, SPAIN email: [email protected] Rafael Navas-González Dto.Electrónica-Universidad de Málaga Complejo Tecnológico, Campus Teatinos 29071 Málaga, SPAIN email: [email protected]ma.es Angel Rodríguez-Vázquez Dept.of Analog and Mixed-Signal Circuit Design C N M - Universidad de Sevilla Edificio CICA, C/Tarfia s/n, 41012-Sevilla, SPAIN [email protected]s.es Keywords: Fuzzy-Control, Fuzzy-Hardware, Mixed-Signal. Paper No. SP018 Corresponding Author: Dr. Fernando Vidal-Verdú Dto.Electrónica-Universidad de Málaga Complejo Tecnológico, Campus Teatinos 29071 Málaga, SPAIN phone: +34 952 13 33 25 fax: +34 952 13 3324 email:[email protected] 1 Neuro-Fuzzy Chip to Handle Complex Tasks with Analog Performance Abstract This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7µm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided. I. INTRODUCTION Associative Memory Networks, as the CMAC network, the B-spline Network, Radial Basis Function Network or Fuzzy Systems [2] perform a partition of the input space and generate the output from data related to small areas around the input vector. This fact provides network transparency and allows the introduction of structured knowledge, as in the Fuzzy Systems, which has become a major advantage to design control systems quickly. On the other hand, the number of basis functions (rules in a fuzzy system) grows exponentially with the input space dimension in Associative Memory Networks, which is their main disadvantage. Implementations of large control algorithms with many variables are usually carried out by software in powerful computers [3][4]. This works for systems where just mechanical or thermal processes are involved, with time constants above one second, thus the input-output delay of the control action is not very demanding. However, if faster processes are going to be faced, as those in motion control and power systems, special purpose hardware could be necessary or perform better than the previous approach. To cope with complex control tasks in the range of milliseconds, general purpose microprocessors or DSPs, or those with a special set of instructions are the best 2 choice [5][6]. However, to manage delays of few milliseconds and down to the microsecond and even nanosecond range, special purpose ASICs are required [7][8][9]. Digital ASICS [10][11] are robust because they work with digital signals, thus they can handle more complex tasks. On the other hand, they need the outer shell of analog circuitry to build the interface with sensors and actuators. Analog circuits [12][13][14][15][16] are considered good candidates to implement neural networks, despite their sensitivity to errors and noise, because the precision requirements are supposed low. However, the latter is not as true in ANN as in other networks with a high redundancy as the multilayer perceptrons, due to the fact that just a few nodes and parameters determine the output, thus errors in these nodes modify the output and are not compensated or corrected by other nodes. Thus, if the input dimension grows and hence the system complexity, errors are difficult to keep bounded. The most complex pure monolithic analog fuzzy controllers implement around 15 rules (basis functions) [13][14]. Nevertheless, since analog circuits provide the best efficiency in terms of area and power/speed ratio, it would be desirable to be able to increase their complexity to manage problems as motor control, where complexities above 25 rules are common [5]. Their straight interface to the plant and faster operation allow them to get better results in terms of less overshoot, smaller settling time, oscillations or ripple voltages or currents [7][9]. In order to build larger analog circuits with bounded errors, we could exploit the inherent tuning capabilities learning procedures have. However, this is only useful if the learning algorithm is implemented on-chip or with the chip-in-a-loop [17]. The first approach increases the requirements on hardware, because we need precise circuits for the learning part as well as fine tunable nodes in the remaining architecture [18]. The second approach still needs tunable nodes but takes advantage of an external computer to perform precise computations. The main drawback here is that the resulting controller is more expensive because of the need of tuning. It is also less 3 flexible, the process to get the controller becomes longer and begins to loss its main appeal. In addition, the resulting controller is less autonomous to be used in embedded applications. Thus, learning algorithms are many times used to get the programming parameters in a conventional computer, then the result is put on silicon without further tuning [9]. Under such conditions, how could we increase the complexity of the networks while processing in analog mode to keep a small delay, power consumption and area?. This paper shows and implementation of the strategy in Fig.1 that exploits the local feature of ANNs to preserve the advantages of analog implementations [1]. Since ANNs provide the output from just a few set of nodes, we implement these nodes in an analog core and make it dynamically programmable to compute the output for any input vector. The basis function identifier performs the input space partition with a set of A/D converters. Note that these converters do not convert the input for further computing, but just perform a coarse clustering to get the set of basis functions that determine the output. This means we usually need only simple, as low as 3bits A/D converters for every input dimension. The output of the converters is used to address a data base which stores the programming data for the analog core. Once the programming data are in the programming bus, the controller is able to provide the output because the core processes the input with analog circuits. Since the input to output signal path is entirely analog, the analog performance is preserved as long as the programming time is just a fraction of the analog core delay. In addition, small analog cores BASIS FUNCTIONS DATA BASE MULTIPLEXING BLOCK ANALOG CORE: SIMPLEST SYSTEM IDENTIFIER Selecting bus Programming bus Inputs Outputs Fig. 1. Strategy to increase the complexity 4 can be carefully designed to bound the error at output and be multiplexed dynamically to implement a large number of rules. This solves the problem of facing complex tasks while preserves a small input-output delay time, and even good performance in terms of area and power consumption. Section II briefly describes this strategy and the resulting mixed-signal highcomplexity fuzzy architecture; Sections III and IV describe the implementation of the high level building blocks in this architecture; and Section V provides experimental results of the MFCON prototype based on the previous approach that has been implemented in standard technology as well as results from a control application example. Finally, conclusions are collected in Section VI. II. MIXED-SIGNAL HIGH-COMPLEXITY FUZZY CONTROLLER ARCHITECTURE The proposed controller is based on a zero-order Takagi-Sugeno fuzzy system whose rules, have singletons in the consequents. The surface response is interpolated from the singletons as (1) where the multi-dimensional basis functions are evaluated by extracting the minimum from the values of the one-dimensional membership functions associated to the k-th rule, and are chosen to generate a lattice partition of the input space [19] [20] − see Fig.2(a) for illustration of lattice partitions. This type of inference with lattice partitions has been employed in different implementations. Its advantages are simplicity, generality and ease of programmability [21] [22]. As a counterpart, the number of rules needed to perform a good approximation becomes prohibitively large as the number of inputs increases [20]. Since in fully-analog implementations the errors and parasitic IF x1 is A1k () AND x2 is A2k () AND…xM is AMk () THEN yy k * = 1kN≤≤() yfx() yk *wkx() wkx() k1N,= ∑ ------------------------------ k1N,= ∑yk *wk *x() k1N,= ∑ == = wkx() sik xi () wkx() min s1kx1 ()s2kx2 ()... sMk xM (),,,{}= sik xi () 5 capacitances at the global computation nodes grow with the number of rules, these errors become very large, thus degrading the global accuracy and input-output delay. The architecture used herein overcomes this problem by using the decomposition property presented in [23] [24]. The input space is split into subspaces defined by the lattice partition; see Fig.2(a) for illustration. Within each subspace the corresponding piece of the surface response − see drawing at the right in Fig.2(a) − is captured by the simplest fuzzy system within this subspace, a system of just two rules per input [23] [24]. Interestingly, the structure of this simplest fuzzy system remains the same for all subspaces; only some parameters must be tuned in order to fit the Fig. 2. General Multiplexed Architecture Fuzzy Controller with Analog Core E1EM Ep (RELATED TO RULE CONSEQUENT) RULE ANTECEDENT) ANALOG CORE RULE ANTECEDENT Size: LMxS bits x1 y w(A) SS S 2M is (log2 (L-1)) is (log2 (L-1)) is (log2 (L-1)) INPUT BLOCKS ( RELATED TO RULE BLOCKS xi xM y1*yl*y*2M PROGRAMMER INTERVAL SELECTOR RULE CONSEQUENT PROGRAMMER AD1 ADi ADM MULTIPLEXING BLOCKS SET X11 X1m+1X1L X1m X21 X2L x2 x1 Cmn E1m E2n ε1mε1m+1 ε2n ε2n+1 X2n+1 X2n Rmn xi sik (a) (b) 6 surface response within each subspace. Thus, the strategy adopted here consists of: a) implementing a programmable analog fuzzy core for the simplest fuzzy system; b) locating the subspace corresponding to the applied inputs; c) mapping the actual subspace location onto a set of corresponding programming signals for the analog fuzzy core. Outputs are then computed by the analog core driven by the inputs and the subspace programming signals. Since errors and inputoutput delay are basically determined by the simple analog core, they can be kept bounded even in very complex controllers. From now on, the generic subspace, labelled Cmn in Fig.2(a), will be called interpolation interval. Fig.2(b) shows the proposed fuzzy controller architecture for a case with inputs, labels per input − thus rules −, and where digital words of -bits per singleton are used to represent the singleton values. Two parts are clearly identified. The Analog Core at the top implements the simplest fuzzy system. The Multiplexing Blocks Set delivers the programming signals corresponding to the interpolation interval to which the actual inputs belong. In the Multiplexing Blocks Set, a battery of simple and fast AD converters − just three bits if seven labels per input are considered − is used to codify the interpolation intervals. The digital word of 1 bits provided by these converters drives the Rule Antecedent Programmer, which provides a set of analog programming values, , (2) and the Rule Consequent Programmer, which provides a set of digital programming values, . (3) These are used to program the antecedent and the consequent blocks of the Analog Core, respectively. 1. means the next superior integer of . ML LMS AD1…ADMMislog2L1–()[]× isx() x PACk1…kME1…Ep…EM ,,,,{}= PCCk1…kM y1 *… yl *… y2M * ,,,,    = 7 This system operates in asynchronous and continuous-time mode, so that its input/output delay is bounded only by the intrinsic circuit response time. In order to preserve the analog performance, the multiplexing blocks must be designed to minimize their effects on global parameters, such as the input/output delay, errors, etc. In the following, we will describe the implementation of the blocks in Fig.2(b). This description includes considerations pertaining to a general case and details pertaining to the bidimensional case implemented at the MFCON controller prototype. III. ANALOG CORE The analog core of Fig.2(b) implements the Takagi-Sugeno algorithm in (1) in a controller with two inputs, therefore four rules, which has a generic interpolation interval as the input space − see Fig.3(a). The circuitry is based on that previously reported by the authors in [14], although some important modifications have been made to incorporate programmability, as well as to save area and power. ε1mε1m+1 ε2n ε2n+1 Fig. 3. (a) Interpolation interval and related parameters, (b) analog core architecture, (c) input block, (d) rule block X1m+1=X1b X1m=X1a Cmn x2 x1 X2n+1=X2b X2n=X2a Rmn= R1Rm+1n= R2 Rm+1n+1= R4 Rmn+1= R3x1 x2 E1 E2 ,()y1∗ ( y2∗ y3∗ y4∗ ,, ), Rule Block Rule Block Rule Block Rule Block Input Block Input Block yNA Programming Interface min output norm weighting wlwl* RULE BLOCK Common Node Glyl∗ Xib sia min inp min inp INPUT BLOCK Xia xiMFC sib Ep E1 E2 R1 R2 R3 R4 X1a X2b X2b X1b X1a X1b X2a X2a (a) (b) (c) (d) min inp 2M-1 min inp min inp min inp 2M-1 8 The core is composed of instances of two main building blocks, namely the Input Block − see Fig.3(c) − and the Rule Block − see Fig.3(d). There is one Input Block per input, hence two in total; and one Rule Block per rule of the simplest fuzzy system, hence four in total. These six blocks are wired as depicted in Fig.3(b) to form the core. Programming of the input blocks is made through voltages that locate the center of the interpolation interval − see Fig.3(a). On the other hand, programming of the rule blocks is realized through digital signals which codify the singleton values. Note that rules R1 and R3 in Fig.3(a) are rules R2 and R4, respectively, in the interval located at left of that depicted in the figure. This means that a rearrangement of the rules is required when there is a change of the interpolation interval and the core is programmed. This rearrangement is realized by analog multiplexors in other programmable architectures [13][25]; here, however, the core architecture is fixed, and the rearrangement is realized by digital multiplexors in the programming interface − details are found in Section IV.E. On the one hand, this strategy is much more robust; on the other, it yields a significant reduction of errors, delays and interferences. A. Input Block Circuitry As Fig.3(c) shows, the input block accepts two types of inputs, the set of controller inputs and the set of programming signals ; and delivers two sets of outputs. Fig.4(b) shows the schematics of the input block. The front-end differential amplifier is employed to obtain the membership functions associated to labels and (see Fig.3(a)). Hence, programmability of the central point location is readily implemented by driving the differential pair with the voltage . Also, since these membership functions are complementary, a simple differential pair suffices to provide both, as Fig.4(a) illustrates. This is exploited to simplify the implementation of the minimum operator by using De Morgan’s Law, i.e. with complement plus maximum circuits. Note in Fig.4(b) that the differential pair outputs are replicated by current mirrors and then used xi Ep2M1– Xia Xib Ep 15 CMOS logic gates of minimum size. On the other hand, Fig.9(a) shows the simple three-stage comparator with hysteresis that has been implemented in MFCON, whose schematic is depicted in Fig.9(c). The input stage is a CMOS differential amplifier which provides high impedance inputs. The hysteresis stage, comprises a simple CMOS inverter comparator, and two complementary PMOS and NMOS current switches controlled by the inverter output vAO, which implements the positive feedback to get hysteresis. Finally the output stage, is another simple CMOS inverter. + − + − Eref vin vout Eref vout vA Mp Mn IP H IPH (b) (a) vAO Fig. 9. Comparator with hysteresis: (a) Symbol and ideal transference curve, (b) Multi-stage comparator with hysteresis used in MFCON, (c) Input stage, hysteresis and output stages schematic Input stage Hysteresis stage Output stage vinvin+ vA Mn1Mn2 Mp3 Mp4 Mp6 Mn7 Mn8 Mp9 Mn10 Mn11 IQ VQij Mn1 =Mn2 Mp3 =Mp4 Mp6 =Mp9 Mn7 =Mn10 Mn8 =Mn11 VQ2 VQ1 IQVQij MnQ 20 MnQ 10 MnQ 2ij MnQ 1ij IPH IPH vAMp Mn Mp1Mp2 Mn1Mn2 a ij bij (c) vAO vin vout VREF ETH + ETH - VSH VSL VOL VOH IPOLH aij bij Mnij Mn00 Mn ph Mpij Mp00 Mn1 =Mn2 (W/L)Mp3 =Mp4 (W/L)Mp6 =Mp9 (W/L)Mn7 =Mn10 (W/L)Mn8 =Mn11 (W/L)MnQ 20 (W/L)MnQ 10 (W/L) 150µm/2µm30µm/2µm60µm/2µm20µm/2µm20µm/2µm10µm/2µm20µm/5µm MnQ 2ij (W/L)MnQ 1ij (W/L)Mn (W/L)Mp (W/L)Mn1 (W/L)Mp1 (W/L)Mn2(W/L) 10µm/2µm20µm/5µm4µm/6µm4µm/2µm2µm/2.4µm3µm/0.8µm2µm/0.8µm Mp2 (W/L)Mnph (W/L)Mp00 (W/L)Mn00 (W/L)Mpij (W/L)Mnij (W/L) 4µm/0.8µm15µm/3µm60µm/3µm15µm/3µm60µm/3µm15µm/3µm vout vin 16 The switches in the second stage allow us to either connect or disconnect the current sources IPH to the input inverter node vA; this either adds or substracts current at this node, thereby forcing the reference voltage of the comparator to be either or , respectively (see Fig.9(b). First-order calculations obtains, ,(4) where gm is the small-signal transconductance of the differential stage; and , if and , where are the output resistances of the circuitry which implements the current sources IPH − see right part of Fig.9(c), and are the ON resistances of the NMOS and PMOS switches, respectively. The expression above shows that the hysteresis can be controlled by the current source IPH, which is derived from an external bias current IPOLH. The Table in Fig.9 shows the sizes of the transistors in Fig.9(c) as used in MFCON. They have been designed to cope with the requirements of gain, common mode range, power consumption and errors, from the simulations and analytical expressions reported in [27]. D. Rule Antecedent Programmer The main requirements for this block are high-speed operation, as well as design simplicity, reliability and compactness. Because every element in must be selected from the whole set of programming values in Fig.8(b), this block comprises a battery of digitally controlled analog multiplexor cells, as Fig.10(a) shows. Fig.10(b) shows the internal structure of an analog multiplexor cell, which is composed of analog switches (CMOS transmission gates), and a Gray decoder which provides the digital control signals for the switches. Both elements are wellknown CMOS building blocks and their design will not be explained here. The estimated input- ETH+ETH – ETH+ IPHn gm ----------- =ETH – IPHp gm ----------- –= IPHn IPHp IPH ≈≈ ronPH rDSnON »ropPH rDSpON »ronPH and ropPH rDSnONand rDSpON EpPACk1…kM Eij M 17 output delay for this block, obtained from simulations, is negligible in comparison with the Interval Selector input-output delay. E. Rule Consequents Programmer Every element in is an S-bit digital value, which must be selected from the whole set of singleton values , for , hence this block must store and address efficiently up to data bits in a digital memory. Besides, it must implement two ways to address these data, one for writing or reading data for external programming (i.e. to program the controller with the proper rule set), and another one for internal accesses, to get the set from the address provided by the Interval Selector. This internal read interface must be asynchronous and fast enough to cope with the speed and continuous time requirements of the controller. It must also provide the whole set ( ) in one step and in the proper order. Because of the input space lattice partition, every generic fuzzy rule belongs to different adjacent interpolation intervals, thus the corresponding singleton value can belong to different programming sets − see example in Fig.11(a). Besides, this shared rule is in different positions depending on the interval it contributes, hence the corresponding singleton value Analog AD1[0 : p] ADM[0 : p] ADi[0 : p] Cell i Cell M E1 Ei EM E11 E1jE1L-1 EM1EMj EML-1 Ei1Eij EiL-1 Cell 1 Multiplexor Analog Multiplexor Analog Multiplexor Fig. 10. Rule Antecedent Programmer: (a) Arrangement of Analog Multiplexor Cells, (b) Cell internal structure (a) (b) Ep SEL-1 SE1 SEk GRAYDECOD. Ei1Eij EiL-1 ADi0 ADi p yl *PCCk1…kM yk *1kL M ≤≤ LMS× PCCk1…kM PCCk1…kM Rmn 2M ymn * ymn * 18 must appear in different locations in the programming bus − see Fig.11(b), because this bus is fixed in the Analog Core side as discussed in Section III. The design of this block is based on the generic conceptual architecture for internal accesses depicted in Fig.12(a). The figure shows how the data are distributed into different blocks of Memory Cells, which contain subsets of singleton values which will never be addressed simultaneously. For a given address, the Row Selector selects one row per Memory Cell block simultaneously, thus all needed singleton values are ready to be accessed. At the same time, the Cmn C(m-1)(n-1)Cm(n-1) C(m-1)n Rmn ε1mε1m+1 ε1m-1 ε2n ε2n+1 ε2n-1 (a) (b) Fig. 11. (a) Rmn is active rule in four adjacent intervals: , (b) Rule order and programming bus example for two adjacent intervals Cmn Cmn 1–() Cm1–()nCm1–()n1–() ,,,() y*mn y*(m+1)n y*m(n+1) y*(m+1)(n+1) y*(m-1)n y*(m-1)(n+1) C(m-1)n Cmn C(m-1)n 12 34 Cmn 12 34 y*mn y*(m+1)ny*m(n+1) y*(m+1)(n+1) y*(m-1)n y*mn y*(m-1)(n+1) y*m(n+1) PCCmn ={ PCC(m-1)n={ } } R(m-1)n Rmn Rm(n+1) R(m+1)(n+1) R(m-1)(n+1) Rmn Rm(n+1) R(m+1)n 1234 Fig. 12. (a) Rule Consequents Programmer conceptual internal architecture, (b) Internal accesses interface timin g 2M -1 LM 2M -1 x S bits Memory Cells Column Selector Row Selector M x is (log2 (L-1)) LM -1 2M -1 2M -1 LM -1 2M -1 LxSLx S 2M xS MUX (2M -1 x L) x 1 2MxS bits (M-1) + is (log2 (L-1)) block LM 2M -1 x S bits Memory Cells block (M-1) x is (log2 (L-1)) tdad twa ADR DAT ADRa ADRb ADRc ADRd DATa DATb DATc DATd (a) (b) ADR DAT 19 Column Selector controls the multiplexor to locate properly every singleton value in the programming bus. Fig.12(b) illustrates the timing of these accesses. Fig.13 illustrates the organization and interfaces of the building blocks in the CMOS implementation of the Rule Consequent Programmer in MFCON based on Fig.12(a). These blocks are Memory Cells, Row Selector, Column Selector for Internal Accesses and Column Selector for External Accesses. The basic building block of the Memory Cell blocks in MFCON is shown in Fig.14(a). It comprises four one-bit memory basic cells, associated to two different Memory Cell Blocks in Fig.12(a). Specifically, row n in Fig.14(a) comprises one-bit basic memory cells (m,n) and (m+1,n), which belong to the Memory Cell Block 2, while row n+1 comprises the cells (m,n+1) Memory Cell blocks Basic Building Block Row Selector Basic Select. MUX 8 X1 MUX 16 X1 MUX 16 X1 MUX 16 X1 MUX 16 X1 Exter. Rd. Dat. Exter. Wr. Dat. Intr.Rd.Dat1 Intr.Rd.Dat.2. Column Selector Column Selector Internal Addressing Accesses External Addressing Accesses Data Interface for external accesses Data Interface for internal accesses Wiring For External Accesses For Internal Accesses Fig. 13. Organization of the different building blocks used in the CMOS implementation of the Rule Consequent Programmer in MFCON. Intr.Rd.Dat3 Intr.Rd.Dat.4. Control Control 20 and (m+1,n+1) which belong to the Memory Cell Block 1. For internal read accesses, switches sm and sm+1 are open, thus memory cells (m,n) and (m+1,n) are in different column lines in the Memory Cell Block 2, while (m,n+1) and (m+1,n+1) are in different column lines in the Memory Cell Block 1. Therefore, the four stored bits can be read simultaneously if both row lines are selected for internal accesses. However, for external accesses, switches sm and sm+1 are closed, so memory cells (m,n) and (m+1,n) belong to the same column line, as well as (m,n+1) and (m+1,n+1). Thus, the whole block is configured to be accessed as a two-row, two-column conventional memory block, and the memory is a conventional RAM for external accesses. Fig.14(b) shows the elements in one column of the basic building block in Fig.14(a). The one-bit basic memory cell used in MFCON (enclosed in dash square in Fig.14(b)), is a single-ended bitline static CMOS cell [28], which is common in register files and multiport memories. Because of the flexibility in changing its configuration, and its robustness [29], this cell results very suitable for the reconfiguration requirements of this application. Fig.14(b) also shows the switches for reconfiguration and the latches for regenerating the logic levels. The transistor sizes in the memory (m,n) (m+1,n) (m,n+1) (m+1,n+1) Wr.Dat. Col.mWR.Dat. Col.m+1 RD.Dat. Col.mRD.Dat. Col. m+1 smsm+1 WR.Sel. Row n WR.Sel. Row n+1 RD.Sel. Row n RD.Sel. Row n+1 RD.Dat.Col.m Cell Block 2 RD.Dat.Col.m+1 Cell Block 2 RD.Dat.Col.m Cell Block 1 RD.Dat.Col.m+1 Cell Block 1 Data Interface for external accesses Data Interface for internal accesses Row Selection Interface Sel_RWRn Sel_RRDn Ext. N1 N2 INV1 INV2 INV3 Sel_RWRn+1 Sel_RRDn+1 WR.Dat. RD.Ext.Dat. N1 N2 INV1 INV2 INV3 INV4 INV5 INV6 INV7 INV6 INV7 sm swcSel_CWRn Col m RD.Dat.Col.m CellBlock2 RD.Dat.Col.m CellBlock1 Ext.sw1m sw2m (m,n) (m,n+1) Fig. 14. (a) Memory Cell basic building block, (b) Detail of the elements of one column: Basic Memory Cell (enclosed in dashed square), reconfiguration switches and column sensed latches (a) (b) 21 cell have been determined from the design recommendations in [28]. The Row Selector activates the proper row selection lines after decoding the access type (read/ write) and origin (internal/external) and the corresponding subset of address lines − see Fig.13. For external accesses the block works as a conventional binary decoder, while for internal accesses it works as a Gray decoder which activates simultaneously several row selection lines per access, one per Memory Cell block considered. Fig.15(a) illustrates the conceptual architecture and interfaces, while Fig.15(b) illustrates the basic building block of the Row Selector as implemented in MFCON. Because internal accesses are always for reading, the Column Selector for Internal Accesses comprises a battery of properly sized multiplexors with shared control lines, as Fig.15(c) illustrates, where the conceptual architecture and interfaces of this block in MFCON are shown. Because column data lines are properly wired to the multiplexor inputs, the control block can be Dec Bin 3:8 0 1 2 3 4 5 6 7 D2 D1 D0 Ena Sel_FWR1 Sel_FRD1 Sel_FWR2 Sel_FRD2 Sel_FWR3 Sel_FRD3 Sel_FWR4 Sel_FRD4 Sel_FWR5 Sel_FRD5 Sel_FWR6 Sel_FRD6 Sel_FWR7 Sel_FRD7 Sel_FWR8 Sel_FRD8 Sele_F1 Sele_F2 Sele_F3 Sele_F5 Sele_F5 Sele_F6 Sele_F7 Sele_F8 Dec Gray 0 1 2 3 4 5 6 7 D2 D1 D0 Ena Seli_F1 Seli_F2 Seli_F3 Seli_F5 Seli_F5 Seli_F6 Seli_F7 Seli_F8 MUX_SEL WR_RD Ext External Address Internal Address AExt[2:0] AInt[2:0] 3 2 Row Selector Basic Building Cell AD Bits Ext. AD Bitsr Int. ExtExt WR_RD WR_RD Sel_FWRi Sel_FRDi ExtExt WR_RD WR_RD Ext Ext WR_RD WR_RD Sel_FWRi Sel_FRDi AD Bit Ext. AD Bit Int. Col.1 Col.2 Col.3 Col.4 Col.5 Col.6 Col.7 Col.8 Col.9 Col.10 Col.11 Col.12 Col.13 Col.14 Col.15 Col.16 4 y*mn MUX1 16x1 4 y*m+1n+1 MUX4 16x1 4 y*mn+1 MUX3 16x1 4 y*m+1n MUX2 16x1 4444 C CC C WIRING Memory Cell blocks Interface Analog Core Interface 4 C Column Selection Control 3 3 ADm ADn Memory Cell blocks interface Interval Selector Interface Fig. 15. (a) Row Selector conceptual architecture, and (b) Basic building block, (c) Column Selector for Internal Accesses conceptual architecture (a) (b) (c) 22 very simple. The Column Selector for External Accesses comprises a control block and a multiplexor per output line − see Fig.13. The control block contains a decoder which activates the proper column selection lines by decoding a subset of the corresponding address lines for write accesses. On the other hand, the multiplexors are controlled by the same subset of address lines to provide the data in read accesses. V. STATIC AND DYNAMIC PERFORMANCES OF MFCON The MFCON controller prototype has been integrated in a single-poly, double-metal CMOS 0.7µm technology offered in EUROPRACTICE. The chip was simulated with HSPICE and designed with Design Frame Work II. It implements the architecture of Fig.2 with two inputs ( ), eight labels per input ( ), and four bits per singleton ( ). Fig.16(a) shows a microphotograph of the chip, and Fig.16(b) shows the floorplan of the chip with the blocks and their sizes. Conservative layout strategies have been adopted; particularly, the analog circuitry has been placed far away from the digital one, with large isolation guard rings in between 1. Also, in order to further reduce interferences between these parts, separate pins and lines have been employed for the analog supply, the digital supply, and the ground [30]. 1. The area occupation of this chips, around 5mm2, is much larger than needed. Since 5mm2 is the minimum area for MPW projects, largely conservative layout floorplanning strategies have been adopted regarding the separation of analog and digital parts. M2= L8= S4= Fig. 16. (a) Microphotography and (b) Floor plan of the chip PADS area MEMORY A/D_C W_SEL ANALOG CORE VO 0.84 mm2 0.30 mm20.27 mm2 0.02 Rings Guard mm2 (a) (b) 23 Fig.17(a) shows the chip pin-out, while Fig.17(b) shows the digital and analog interfaces with the pins grouped in buses. On the one hand, the digital interface corresponds to a typical asynchronous peripheral for microcontroller-based systems, with an input address bus (A{0:5}), a bidirectional data bus (D{0:3}) and a control bus (COM, W-R). On the other hand, the analog interface is composed of the controller input and output signals, and a few off-chip bias signals to simplify testing of the prototype. These signals should be generated on-chip in a marketable final version. The fuzzy controller inputs are and , which are driven by voltage mode signals in the range from 2.0V to 4.8 V. The primary fuzzy controller output is − a current signal in the range from 0µA to 150µA. A voltage output is also provided at . This voltage is obtained by applying a replica of to an on-chip polysilicon resistor. Every singleton value is a four-bit digital word which encodes sixteen uniformly distributed analog values in the output current range. Fig.18 and Fig.19 show some experimental results obtained from the test environment. Fig.18(a) depicts a section of a measured DC control surface, and Fig.18(b) shows the transient response to a step input. The former illustrates the response (bottom) to a ramp in one input (top) while the other input remains constant, in a kind of mexican hat surface. The latter corresponds to Fig. 17. Fuzzy controller chip: (a) pin-out; (b) interfaces A(0:5) D(0:3)COM,W-R IPs,VREF Digital Analog FUZZY CHIP CONTROLLER ADDRESSDATA CONTROL OUTPUTSINPUTSBIAS Interface Interface x1x2 ,zIzV , 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28A1 A0 GNDG VREF IPH VDDA X1 X2 IPN IPG IPV GNDA ZV ZIGNDG A5 A4 A3 GNDD D3 D2 COM D1 D0 VDDD W_R A2 (a) (b) x1x2 zI zV zIymn * 24 a falling edge in one input which forces the output to change from its maximum to its minimum value, as well as to jump to a different interpolation interval, which means a dynamic programming of the analog core. The measured delay time is around 500ns. Since the oscilloscope is not able to sense currents, previous measurements are voltages in the output . With regard to Fig.19(b) and Fig.19(d), they are built with data obtained from a data acquisition board, where the current output x1 (V) zV (V) time x1 (V)zV (V) time x2 =3.2 V x2 =3.2 V Fig. 18. Measured results: (a) DC nonlinear control surface section, (b) transient falling edge step response. (a) (b) (a) (b) Fig. 19. Control surface measured results: (a) programming rule matrix I, (b) nonlinear control surface I, (c) programing rule matrix II and (d) nonlinear control surface II (c) (d) 2.0V 4.8V 2.0 V 4.8 V x1 (V) x2 (V) ZI (A) 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 0 15 0 0 0 15 15 15 X11 X18 X21 X28 x2 x1 Rule Matrix 4.4 V 2.0 V 2.0 V 4.4 V x1 (V) x2 (V) ZI (A) 0 0 10 10 0 10 10 0 10 10 0 0 10 0 0 10 0 0 10 10 0 10 10 0 10 10 0 0 10 0 0 10 5 5 14 14 5 14 14 5 14 14 5 5 14 5 5 14 5 5 14 14 5 14 14 5 14 14 5 5 14 5 5 14 X11 X18 X21 X28 x2 x1 Rule Matrix zV