Open loop sigma-delta modulators for digital-to-analog converters with high speed improving using time interleaving

Depósito de Investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published by Elsevier in AEU - International Journal of Electronics and Communications, Vol. 125 on October 2020, available at: https://doi.org/10.1016/j.aeue.2020.153394 © 2020 Elsevier. En idUS Licencia Creative Commons CC BY-NC-ND Open Loop Sigma-Delta Modulators for Digital-to-Analog converters with high speed improving using Time Interleaving F. Colodro, J.M. Martinez-Heredia, J.L. Mora, and A. Torralba Dr. Francisco Colodro, e-mail: [email protected] Dr. Juana María Martinez-Heredia, e-mail: [email protected] Dr. José Luis Mora, e-mail: [email protected] Dr. Jaime Ramírez-Angulo Dr. Antonio Torralba, e-mail: [email protected] Corresponding author: Francisco Colodro All of them are with the Electronic Engineering Department, ETS de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092, Sevilla, SPAIN Open Loop Sigma-Delta Modulators for Digital-to-Analog converters with high speed improving using Time Interleaving Abstract: Sigma-delta (SD) modulator based DACs are simple circuits with low accuracy requirements in their analog components. However, their signal bandwidth is limited by speed constrains. In this respect, Time-Interleaving (TI) allows the designer to trade-off between complexity and speed by replacing the original architecture by N parallel paths clocked at a frequency N times smaller. Unfortunately, this is only possible for small values of N because the resulting TI architecture has long combinatorial paths. These paths reduce the maximum clock rate. In closed-loop SD architectures these paths cannot be broken by the insertion of registers, because an increase of the loop delay compromises the stability of the modulator. This paper proposes a TI decomposition in open-loop SD modulators, which allows the insertion of as many registers as desired to shorten the critical combinatorial path. Consequently, the clock frequency (and, hence, the performances) can be increased at its maximum. The proposed method is illustrated with a second-order modulator, which has been synthesized in an FPGA (Spartan-6 xc6slx75t). Post-route static timing analysis and simulations show a considerable increase of performances. In authors´ knowledge, it is the first time that TI is applied in open-loop SD modulators, resulting in very speed DACs. Index Terms: Digital-analog conversion, Sigma-delta modulation, Time-Interleaving 1. Introduction Sigma-Delta modulators (SDMs) receive increasing more attention in the implementation of modern communication standards, both in the design of transmitters and receivers. Wideband software defined transmitters require the digital-to-analogue converter (DAC) to be rated at a very high frequency [1]-[5]. As long as a SDM based DAC is used, speed constraints of the technology impose limitations. If moderate oversampling ratio (OSR) values were chosen, moderate dynamic range (DR) values would be achieved; on the other hand, if a high OSR were used, the signal bandwidth would be low [6]. In this regard, Time-Interleaving (TI) has been used to relieve speed constraints by trading off complexity and speed [7]-[11]. The TI modulator can be derived from the classical one by replicating a basic modulator in N parallel paths clocked at the rate fs, such that the effective sampling rate is N f s . As consequence, the effective OSR is N times greater than that of the classical modulator. Due to current scale of integration, the higher complexity introduced by a TI realization does not represent a problem in terms of cost, power consumption and area. But the crossed paths that appear in the TI realization increase the delay of the critical path (CP), which is the path with the maximum delay that goes from the output of one register to the input of the succeeding one through combinatorial logic. The longer the CP, the lower the maximum operating frequency f s . This discussion can be illustrated for the case of a second-order modulator. The two-channel ( N =2) TI version can be directly derived using the block-filtering approach, resulting in the architecture shown in Fig. 1 [7]. The input x(n) is a sequence rated at 2 fs. This input is split into two sequences by means of the down-sampling block. The resulting signals x0(n)=x(2n) and x1(n)=x(2n+1) are processed by the two-path loop filter, resulting from the block-filtering approach, clocked at half the input signal rate, fs. Blocks named Q correspond to two equal quantizers, which have the same bit number as the quantizer of the equivalent second-order SDM clocked at rate 2 fs. Finally, the output y(n) is generated from y0(n) and y1(n) by time-multiplexing using the up-sampling block. The CP is shown with dashed lines. Even with a highly efficient implementation [5,11], the TI modulator does not outperform the classical one for values of N greater than 4 [5]. The CP could be broken by inserting registers (unit delays) along the path. But this solution increases the total delay of the path and, as long as the CP is part of the feedback path, it compromises the stability of the modulator. To overcome the frequency limitation that introduces the presence of long combinational paths in TI SDMs, this paper proposes the use of TI in open loop (OL) SDMs. Fig. 1 TI implementation of a 2nd order SDM. The dashed line traces the critical path 2. The open-loop SD modulator An OL representation of a SDM was first proposed in [12] for the sole purpose of mathematical analysis, as this representation is unfeasible, from the implementation point of view. OL structures have been proposed for implementation of both digital [13-14] and analogue [15-17] SDMs. The first OL architectures were built using integrators and differentiators, resulting in NTFs with all their zeros placed at DC. The equivalence between these OL and the classical closed-loop SDMs has been shown by means of simulations [14] or analytical procedures [18]. Other NTFs, which can achieve larger SNDR, have been designed with their zeros distributed along the signal band [16-17]. As there is no feedback in the OL architecture, the resulting TI architecture has not a feedback path. Therefore, the length of its combinatorial paths may be reduced by insertion of unit delays x 0 − − z -1 1−z -1 1 1−z -1 Q Q z -1 + 1 1−z -1 + z -1 − − + 1 1−z -1 + + + x(n) 2 2 z -1 x 1 2 y(n) 2 y 1 y 0 z -1 ( z −1) without stability concerns, and with the only consequence of a greater latency. A unit delays can be implemented by means of a flip-flop register clocked at the rate f s . As an example, the 2nd-order OL SDM is shown in Fig. 2 where Q is a digital quantizer and r ( n ) is the quantization noise when Q is replaced by its linear additive-noise model [6]. The signal path of the input, x ( n ), is through two integrators and two differentiators. So, the signal transfer function (STF) is in fact a double delay. Beside the quantization noise goes only through the two differentiators. In consequence, the STF and the noise-transfer function (NTF) are given by 𝑆𝑇𝐹(𝑧)=𝑧 𝑁𝑇𝐹(𝑧)=(1−𝑧) (1) a second-order noise shaping is achieved and the output can be expressed as Y ( z ) = STF ( z ) X ( z ) + NTF ( z ) R( z ). Let us assume that the signal ranges between − R /2 and + R /2. In that case each integrator and differentiator is implemented using R modular arithmetic; that is, when the expected output, u , is greater than + R /2, the actual value is wrapped downward to u − R ; and when u is lower than − R /2, the actual value is wrapping upward to u + R . Thus, if the number of bits of the quantizer (Q in Fig. 2) is B , the OL architecture will be equivalent to the conventional SDM, as long as the maximum value of | x ( n )| is smaller than X P,MAX [16], 𝑋, =𝑅(12 −2 2 ) (2) where L is the order of the SDM. Fig. 2 2nd-order OL SD modulator z-1 1−z-1 Q z-1 1−z-1 1−z-1 1−z-1 x(n) y(n) r(n) For the sake of simplicity, let us assume L =2 and R =2 (which corresponds to a signal swing of [−1,+1]). The larger the bit number of the modulator quantizer, the greater the complexity of the front-end DAC (which is the DAC placed just after the SDM; note that it has a low number of bits due to the B -bit digital quantizer Q, and is clocked at the frequency N f s ). So, a good tradeoff between dynamic range (DR) and complexity of the front-end DAC is achieved with B =3 or 4. From (2), when B is equal to 1 or 2, the maximum input amplitude takes the value −1 or 0, respectively; therefore, the OL SDM is unfeasible to be implemented. On the other side, when B takes a large value, the complexity of the front-end DAC will also be large1. It is a common practice in the design of SDMs that the maximum resolution of DACs does not exceed 5 or 6 bits [6]. In the case that B =3, X P,MAX is 0.5 (−6 dB); then the DR is approximately one bit smaller than that of the corresponding closed-loop version of the modulator. This DR loss could be reduced to −2.5 dB for B =4. As it will be shown below, this loss will be recovered by an increase of the effective OSR. 3. Proposed TI SD modulator This section presents the procedure to convert the original OL modulator to its corresponding TI version. Once again, for the sake of simplicity, a second-order open-loop SD modulator will illustrate this procedure for the case N =2, although this same procedure could be applied to higher order modulators with any value of N . The block-filtering approach is applied to the integrative and derivative sections of Fig. 2 [7]. The resulting architecture is shown in Fig. 3 (see appendix A). The polyphase decompositions [19] of the input and output signals are given by 1 Later it will be seen that the number of bits of the front-end DAC is B 𝑥(𝑛)=𝑥(2𝑛) 𝑥(𝑛)=𝑥(2𝑛+1) 𝑦(𝑛)=𝑦(2𝑛) 𝑦(𝑛)=𝑦(2𝑛+1) (3) I ( z ) and D ( z ) are the filter banks obtained from the polyphase decomposition of the double integrative and derivative sections of Fig. 2, respectively: 𝐼(𝑧)= ()()󰇡1+𝑧 2 2𝑧 1+𝑧󰇢 𝐷(𝑧)=󰇡1+𝑧 −2 −2𝑧 1+𝑧󰇢 (4) Taking into account (Fig. 3) that 𝑝(𝑛)=𝑞(𝑛)and 𝑝(𝑛)=𝑞(𝑛−1) (5) the resulting TI OL SDM is shown in Fig. 4. Let’s note that the architectures in Fig.2 - Fig.4 are equivalent [7,19] and consequently Y ( z ) = STF ( z ) X ( z ) + NTF ( z ) R ( z ), where the STF and the NTF are, once again, given by (1). Fig. 3 Architecture that results of an independent application of the blocking filtering approach to the integrative and derivative sections of the modulator in Fig. 2 The CP of the resulting TI OL SD modulator is represented in Fig. 4 with a dashed arrow line. In the CP, the signal flows through 4 adders and 1 quantizer, adding a total delay of five functional blocks. Note that, as a first advantage of the TI OL SDM over its corresponding closed-loop version, its CP is shorter. In fact, the CP of the closed-loop modulator not only is through one branch crossing (just like the TI OL SDM), but it continues through the feedback path. As a consequence, the CP in Fig. 1 has a total delay of eleven functional blocks. Let t d be the total delay of the CP in Fig. 4. In a first approximation, the frequency f s of the modulator clock has to verify: 𝑓<  (6) 2 x(n) y(n) 2 2 2 Q Q z -1 x 0 x 1 y 1 y 0 z -1 2 2 q 0 q 1 z -1 2 2 z -1 p 0 p 1 I(z) D(z) + where t CO and t SU are the clock-to-output delay and the setup time of the flip-flop registers placed at the input and output of the CP, respectively. As a second advantage of the TI OL SDM, its critical path can be broken into small pieces by the insertion of one or more unit delays, since the insertion of a delay in the signal path of an OL architecture does not degrades performances or compromises its stability. For instance, a unit delay can be inserted in each point where the dotted vertical lines and the signal paths intersect in Fig. 4. The resulting architecture is shown in Fig. 5. The only difference between both architectures is that x ( n ) and r(n) arrive at the output with an additional delay of five and two units of the slow clock f s , respectively. Then, both outputs in Fig. 5, y 0( n ) and y 1( n ), are multiplexed at the high rate 2 f s , and Y ( z ) = z −10 STF ( z ) X ( z ) + z −4 NTF ( z ) R ( z ), where the STF and the NTF are, once again, given by (1). Due to these delays the output in Fig. 2 or Fig. 3 is not exactly the same as in Fig. 5. But, as the power of the signal and noise components at the output does not change2, neither does the SNR. Simulation results in the following sections confirm this last assessment. Fig. 4 Proposed 2nd-order TI OL SD modulator derived from Fig. 3 (multiplexers and demultiplexers are not shown) 2 The power only depends on the shape of the transfer functions which does not change with the delays. That is, if z =exp(j π f / f s ) at the rate of (2 f s ), then | z −m F ( z )|2=| F ( z )|2 z -1 x 0 (n) z -1 1−z -1 1 1−z -1 x 1 (n) y 1 (n) y 0 (n) z -1 1−z -1 1 1−z -1 z -1 + +Q +Q z -1 + z -1 + + + − − z -1 + z -1 2 2 z -1 2 2 The PSD for an input amplitude of, approximately, −6 dBfs (255≈2 M /4 in two’s complement) is depicted in Fig. 12. The SQNR obtained by VHDL simulation is 60.72 dB. In this simulation the clock rate was f s =400 MHz and the quantization noise power was calculated from 0 to 16 MHz (an effective OSR of 16). Unlike Fig. 8, the PSD in Fig. 12 is limited at the low frequencies by the 10-bit quantization noise background of the input signal. Fig. 12 Power spectral density of the TI OL SD modulator output y(n) for an input amplitude of −6 dB. The vertical dashed line marks the signal bandwidth. The clock rate is normalized at fs =1 Hz. Simulation obtained in VHDL (M=10, B=3, and SQNR=60.72 dB) 5.3 Performances improvement by increasing the clock rate In order to estimate the maximum achievable clock rate f s of the TI architectures, Post- Place&Route simulations in the time domain have been run using the same design platform. Maximum achievable clock rates were 101.6, 161.9, and 456.4 MHz for the TI closed-loop (Fig. 1), the TI OL SDM (Fig. 4) and the TI OL SDM with a shortened CP (Fig. 5), respectively. Since the DR in a second-order SDM improves 15 dB every time that the sampling frequency is doubled [6], the TI OL SDM and the TI OL SDM with a shortened CP outperform the closedloop modulator in 4.13 dB and 26.62 dB respectively (that is, in 10.3 dB and 32.62 dB, minus the 6 dB due to the falling off of the maximum input amplitude fall in OL architectures, respectively). PSD (dB) 6 Conclusions In this paper the proposed TI OL SD modulator has been shown to have the potential to increase the clock frequency f s to a value only limited by the time delay of the slowest combinatorial block (adder or quantizer). Since the combinatorial paths cannot be broken by inserting unit registers in the TI implementation of a closed-loop modulator, the clocking frequency f s is limited by the time delay of the CP, which can be very long due to the presence of feedback and crossed paths. This paper shows that the digital part of the proposed TI OL SDM can be clocked up to frequencies 4.5 times greater than the closed-loop TI modulator for the case of a second-order modulator with two parallel branches ( N =2). In this way, the proposed modulator achieves an increase of 26.6 dB in the DR (4.4 effective bits) with respect to the conventional closed-loop one. Because the crossed paths have a large combinatorial delay for N >2, even a larger improvement in the DR is expected. Furthermore, the digital circuitry could be clocked at a higher frequency if the delay of every functional unit block (adder, subtractor,…) were reduced by inserting internal unit delays (for instance, by inserting a unit delay between each two adjacent full adders that compose a M -bit ripple-carry binary adder). Hence, in the implementation of a TI OL SDM based DAC, the maximum clocking frequency is ultimately limited by the front-end DAC. In the authors´ knowledge no other such a high speed implementation of a TI SDM has been ever reported. A. Appendix: derivation of Fig. 3 A discrete-time filter H ( z ) can be implemented at a rate N times lower by means of the block-filtering approach [7,19]. The resulting architecture is built of N parallel paths interconnected each other. The connection can be represented by the filter bank B ( z ), 𝐵(𝑧)=⎣ ⎢ ⎢ ⎢ ⎡ 𝑃(𝑧) 𝑃(𝑧) 𝑃(𝑧) … 𝑃(𝑧) 𝑧𝑃(𝑧) 𝑃(𝑧) 𝑃(𝑧) … 𝑃(𝑧) 𝑧𝑃(𝑧) ⋮ 𝑧𝑃(𝑧) 𝑧𝑃(𝑧) ⋮ 𝑧𝑃(𝑧) 𝑃(𝑧) ⋮ 𝑧𝑃(𝑧) … ⋱ …𝑃(𝑧) ⋮ 𝑃(𝑧) ⎦ ⎥ ⎥ ⎥ ⎤ (A.1) where P i ( z ) is the i -th component that results from the polyphase decomposition of H ( z ) 𝐻(𝑧)=∑𝑧𝑃(𝑧)   (A.2) Fig. A1 illustrates the case N =2. Fig. A1 Block-filtering approach The derivative section in Fig. 2 is a finite impulse response (FIR) filter and the polyphase decomposition is straightforward: (1−𝑧)=1−2𝑧+𝑧 =𝑃 (𝑧)+𝑧𝑃(𝑧) where P 0( z )=1+ z −1 and P 1( z )=−2. The bank filter D ( z ) given in (4) can now be obtained by replacing these functions in (A.1) for the case N =2. Taking into consideration that (1−𝑧)=(1−𝑧)(1+𝑧), the bank filter of the integrative section can be obtained as follows 󰇧𝑧 1−𝑧󰇨=𝑧󰇧1+𝑧 1−𝑧󰇨= 𝑧(1+𝑧) (1−𝑧)+ 𝑧 2𝑧 (1−𝑧)=𝑃 (𝑧)+𝑧𝑃(𝑧) The components are now given by 𝑃(𝑧)= ()(1+𝑧) y 𝑃(𝑧)=2  (). From these equations and (A.1) is straightforward to obtain the filter bank I ( z ) given in (4). 2 x(n) y(n) 2 22 z -1 x 0 x 1 y 1 y 0 z -1 B(z) H(z) x(n) y(n) a) b) References [1] Li H, Breyne L, Kerrebrouck J.V, Verplaetse, Wu C.Y, Demeester P, Torfs G. A 21- GS/s single-bit second-order delta-sigma modulator for FPGAs. IEEE Trans. Circuits Systems 2019; vol. 66, no 3, pp. 482–486. https://doi.org/10.1109/TCSII.2018.2855962 [2] Bhide A, Alvandpour. An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS. IEEE J. Solid-State Circuits 2015; vol. 50, no. 10, pp. 2306-2318. https://doi.org/10.1109/JSSC.2015.2460375 [3] Tanio M, Hori S, Tawa N, Kunihiro K. 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IEEE Trans. on CAS-I, 2009; vol. 56, Iss. 10, pp. 2159–2172. https://doi.org/10.1109/TCSI.2009.2015211 [17] Wulff C. Efficient ADCs for nano-scale CMOS Technology. Doctoral Thesis, 2008. Norwegian University of Science and Technology [18] Lipshitz S. P, Vanderkooy J, Bodmann B. G. Sigma–delta modulators without feedback around the quantizer?. Proc. 123rd Conv. Audio Eng. Soc., 2007, vol. 7201, pp. 1–15 [19] Vaidyanathan P.P. Multirate systems and filter banks. Prentice Hall, 1993 Francisco Colodro received his Telecommunications Engineering degree from the University of Vigo, Spain, in 1992, and his Ph.D. degree from the University of Seville (US), Spain, in 1997. He is currently a Senior Lecturer in the Department of Electronic Engineering, US. His research interests include analog-to-digital and digital-to-analog conversion, sigma–delta modulators, and microelectronic circuits and systems with application to control, aeronautics and communications. Juana M. Martinez-Heredia received her Telecommunications Engineering and Ph.D. degrees from the University of Seville (US), Spain, in 1999 and 2006, respectively. Since 1999, she has been with the Department of Electronic Engineering, US, where she is an Associate Professor. Her research interests include low-voltage low-power analog circuit design, analog and mixed-signal design, and design of circuits for aircrafts and UAVs José Luis Mora-Jiménez received his M.S. and Ph.D. degrees in Industrial Engineering from the US, Spain, in 1992 and 2001, respectively. He is currently an Associate Professor in the Department of Electronic Engineering, US. His current research areas are digital design, modeling and control of power converters, multilevel converters, and sensor-less motor drives. Antonio Torralba (M’89-SM’02) has a Ph.D. in Electrical Engineering from the University of Sevilla (1985). He joined the Electronic Engineering Department of this University in 1983, being full Professor in 1996. He has published more than 90 papers in Journals and Transactions. His research interest is in analog and mixed design.