An Op-Amp Approach for Bandpass VGAs With Constant Bandwidth

1549-7747 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2808236, IEEE Transactions on Circuits and Systems II: Express Briefs  Abstract—Two approaches to implement variable gain amplifiers based on Miller op-amps are discussed. One has true constant bandwidth while the other has essentially reduced bandwidth variations with varying gain. Servo-loops and AC coupling techniques with quasi floating gate transistors are used to provide a bandpass response with very low cutoff frequency in the range of Hz. In practice, one of the schemes is shown to have bandwidth variations close to a factor two while the second one has true constant bandwidth over the gain tuning range. Experimental results of test chip prototypes in 180 nm CMOS technology verify the theoretical claims. Index Terms—Constant bandwidth, VGA, Servo-loop, AC coupled amplifiers, QFG transistors. I. INTRODUCTION EVERAL approaches to implement Variable Gain Amplifiers (VGAs) with constant bandwidth based on Current Conveyors (CC) [1]-[2], Current Feedback (Transresistance) Amplifiers (CFA) [3]-[5], OTAs with tunable transconductance gain and constant load [6] and Cherry-Hooper amplifiers (OTA op-amp combination) [7]-[9], have been reported. In all cases, constant bandwidth is achieved by adjusting the gain G with resistor R1 as depicted in Figs. 1a-c. For high gains, resistor R1 is required to have small values relative to R2. In the case of CC and CFA this requires very low impedance at input terminal X (RX << R1 << R2), which is difficult to achieve at high frequencies. In Cherry-Hooper amplifiers, the OTA has typically a transconductance gain Gm=1/R1 related to a resistor R1 which is also required to have a small value. In both cases (very low RX, and high Gm) increased power dissipation is required. Amplifiers based on conventional op-amps in inverting and non-inverting configurations have a bandwidth BW=GB/(1+R2/R1)=βGB which decreases with the gain (Fig. 1(d)), where β is the feedback factor given by β=1/(1+R2/R1) and GB is gain bandwidth product given by GB=gmDP/Cc in Miller (two-stage) op-amps and by GB=gmDP/CL in one stage op-amps (OTAs). Further, gmDP is the transconductance gain of the transistors in the differential input stage, CL is the load capacitance and Cc is the compensation capacitance in Miller op-amps (typically a value Cc=CL is selected to achieve unity gain stability). A technique to achieve constant bandwidth has been proposed by scaling gmDP with the gain [10]. This requires digitally programmable arrays of transistors and current sources for the input differential pair and it is limited to relatively narrow gain tuning ranges. S. Pourashraf and J. Ramirez-Angulo are with the VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, 88003, USA (e-mail: [email protected]; and [email protected]). A. J. Lopez-Martin and J. M. Algueta-Miguel are with the Institute of Smart Cities, Public University of Navarra, E-31006 Pamplona, Spain (e-mail: [email protected]; and [email protected]). (a) (b) (c) (d) Fig. 1. (a) Current Conveyor amplifier CCA, (b) Current Feedback Amplifier CFA, (c) Cherry-Hooper amplifier, and (d) Conventional inverting amplifier. (a) (b) (c) (d) Fig. 2. Bandpass VGA implementations: (a) Servo-loop. (b) AC coupled. (c) Fully differential (FD) two-stage Miller op-amp used in VGAs. (d) Common mode feedback network. In this paper, two simple approaches for the implementation of bandpass VGAs based on two-stage Miller op-amps (Fig. 2) are compared. They both have low cutoff frequencies in the range of Hz. One of them is shown to have greatly reduced BW variations with respect to the Conventional Approach while the other has true constant bandwidth with varying gain. Bandpass R. Carvajal is with the Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, E-41092, Spain (e-mail: [email protected]). Shirin Pourashraf, Member, IEEE, Jaime Ramirez-Angulo, Fellow, IEEE, Antonio J. Lopez-Martin, Ramon González-Carvajal, Senior Member, IEEE, and Jose Maria Algueta-Miguel, Member, IEEE. An Op-amp Approach for Bandpass VGAs with Constant Bandwidth S 1549-7747 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2808236, IEEE Transactions on Circuits and Systems II: Express Briefs response is achieved using the two methods described in Sections I-A and I-B, respectively. A. Servo-loop (shown in red in Fig. 2a) This method uses an integrator in a negative feedback loop to achieve attenuation in the low frequency band. The op-amp has an additional differential pair (differential difference amplifier (DDA)) to inject the feedback signal from an integrator with unity gain frequency ωo=1/(RLargeCINT). In this case, the open loop response of the op-amp can be approximated by a bandpass response with two real poles AOL(s)=AOLDC[s/(s+ωL)][1/(s+ωH)] (see Fig. 3a). Further, AOLDC is the op-amps DC open loop gain, ωL=ωoAOLDC and ωH=GB/AOLDC. Note that AOL(s) neglects the op-amp high frequency pole ωpH, the finite attenuation at DC, where AOL(0)=1/AOL-INT, and a very low frequency zero ωZ=ωo/AOL-INT caused by the finite DC open loop gain of the integrator AOL-INT. Notice that the unity gain frequency ωo of the integrator becomes the unity gain frequency of the bandpass amplifier in the low frequency band. Straightforward analysis assuming ωH>>ωL and βAOLDC>>1 shows that the closed loop response G(s) given by G(s)=AOL(s)/[1+βAOL(s)] can be approximated by a bandpass response G(s)=G[s/(s+ωL’)][1/(s+ωH’)] with real poles ωL’, ωH’. Further, G=-R2/R1 is the mid-band gain and the relation ωLωH=ωL’ωH’=ωoGB applies. In the Conventional Approach the switches shown in blue and controlled by bi low are not included. In this approach, the high -3 dB frequency is given by ωH’=βGB while the low -3 dB frequency is given by ωL’=ωo/β=ωo(1+|G|). B. AC Coupled Amplifier (see Fig. 2b) In this method an AC coupled amplifier is used, and ωH’ is also given by ωH’=βGB while ωL’ is constant and given by ωL’=1/(RLargeC) (see Fig. 3b) i.e. [11]. The remainder of this paper is organized as follows. In Section II, two approaches for constant bandwidth are discussed. Simulation and experimental results of two test chip prototypes are presented in Section III. Conclusions are drawn in Section IV. (a) (b) Fig. 3. Frequency response in open and closed loop (shown in black and blue, respectively): (a) Servo-loop. (b) AC coupled. II. APPROACHES A. Approach I In this approach, the compensation capacitor has a value Cceff that is dependent on G. It is scaled down with the gain G=-R2/R1 according to Cceff=Cc/|G| which leads to ωH’=β[gmDP/Cceff]=β|G|[gmDP/Cc]. In turn ωH’ can be expressed as ωH’=(GB|G|)/(1+|G|) and has a moderate gain dependent variation. For gain values |G|>>1, ωH’ remains approximately constant with a value ωH’≈GB; whereas, for |G|=1 it attains the minimum value ωHMIN’=GB/2. Fig. 4 shows a very simple implementation of a digitally scaling approach for Cc applied to an inverting amplifier with digitally programmable gain |G|=(20b0+···+2N-1bN-1) (see Fig. 2a and 2b without switches shown in blue and controlled by bi low). The gain programmable compensation capacitor is simply implemented as the series combination of binarily weighted capacitors (see Fig. 4), therefore Cceff=Cc/(20b0+···+2N-1bN-1)=Cc/|G| as required. The concept of scaling down Cc with the gain to maintain constant GB has been addressed in [12]-[13] using active methods based on Miller multiplication that adapt the compensation capacitance to the gain. They were applied in [13] to a buffered single stage OTA using an additional high bandwidth VGA as Miller multiplier. Remarks: 1. The total capacitance required to implement the digitally programmable capacitor array is Ctot≈2Cc, this is twice the capacitance Cc required in the conventional amplifier. 2. Bottom and top plate capacitances and MOS parasitic capacitances (especially CgdOUT of the output transistor), as well as switch on resistances, lead to larger than expected variations in ωH’. In practice, the effective compensation capacitance can be approximated by Cceff=(Cc/|G|)+CgdOUT+kCpar (k is a coefficient that depends on gain |G|) and high -3dB frequency by ωH’=[gmDP/(Cc+|G|(CgdOUT+kCpar)][|G|/(1+|G|)]. For gains |G|>>1, ωH’ can be approximated as ωH’=[gmDP/(Cc+|G|(CgdOUT+kCpar))]. This shows that ωH’ decreases with gain; in order to reduce this effect, values of Cc >> (|GMAX|CgdOUT) should be used. 3. This approach can also be used in single stage op-amps (OTAs) by using a buffer at the output of the OTA i.e. [14]-[15]. In this case, higher bandwidths could be achieved since GBMAX is limited by high frequency internal poles. 4. The switch on resistances can lead to changes in the phase margin and op-amps unity gain frequency. Fig. 4. Implementation of digitally programmable Cc in Approach I. 1549-7747 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2808236, IEEE Transactions on Circuits and Systems II: Express Briefs 5. In both the Conventional Approach and Approach I, the low -3 dB frequency ωL’ does not remain constant when a Servo-loop is used to achieve bandpass response. Instead, it increases with |G| according to ωL’=ωo (1+|G|). Implementation of CINT as a digitally programmable array of binarily weighted capacitors in parallel with value CINTeff=CINT|G| would lead to a constant ωL’, however it is not efficient in terms of area, since requires a large total capacitance GMAXCINT. B. Approach II In this approach (Fig. 2 including the switches shown in blue and controlled by bi low), the capacitance Cc (and therefore GB) is constant. True constant bandwidth and phase margin is achieved by connecting the active input terminals that determine G (with bi high) to the input signal source Vin, while connecting the remaining passive input terminals to ground (this approach includes the switches shown in blue and controlled by with bi low in Fig. 2a and 2b). This leads to a constant feedback factor β=1/(1+|GMAX|) and as a consequence, to a constant value ωH’=βGB=GB/(1+|GMAX|)=gm/[(1+|GMAX|)Cc]. The phase margin also remains constant since the unity gain frequency of the loop gain (ωuLG=ωH’) does not change with |G|, which is, in turn, set by the active input terminals connected to Vin. Remarks: 1. Implementation of bandpass VGAs can be done according to the two schemes shown in Fig. 2 including the switches shown in blue and controlled by bi low. In both, ωL’ is constant. For the amplifier with Servo-loop ωL’=ωo/β=ωo(1+|GMAX|) and for the AC coupled amplifier ωL’=1/(RLargeC). 2. Conventional VGAs have the lowest phase margin for |G|=1. For stability it is typically required that ωpH>2GB in order to achieve a phase margin greater than 60o (ωpH is the high frequency pole of the op-amp open loop response). The unity gain frequency of the loop gain ωuLG decreases with G according to ωuLG=ωH’=GB/(1+|G|). This causes the phase margin to increase with |G|. In Approach II, the unity gain frequency of the loop gain is constant and given by ωuLG=ωH’=GB/(1+|GMAX|). The stability condition requires 2GB/(1+|GMAX|)<ωpH instead of 2GB<ωpH. This can be satisfied even with values ωpH<GB, since ωuLG=GB/(1+|GMAX|) is constant and has the lowest possible value (Fig. 5). Given that ωuLG and ωpH are constant, the phase margin does not change with gain. Fig. 5. Frequency response in open and closed loop Approach II. 3. Selecting Cc=CL is a common choice to achieve unity gain stability in conventional VGAs based on Miller op-amps. Approach II allows the designer to select a smaller value Cc=CL/(1+|GMAX|) to achieve stable behaviour for all gains. For [CL/(1+|GMAX|)]<CgdOUT, no compensation capacitance is required. This leads to the maximum possible bandwidth. The BW factor can be programmed digitally using an array of digitally programmable capacitors. In practice, the minimum value for Cc is determined by noise considerations. 4. The rms input noise in this Approach is constant and proportional to 1/[(1+|GMAX|)Cc]1/2. It is lower by the factor·[(1+|G|)/(1+|GMAX|)]1/2 than the Conventional Approach and by factor [(1+|G|)/(|G|(1+|GMAX|))]1/2 than Approach I. As indicated above, if required, noise can be reduced by increasing Cc; however, there is a bandwidth penalty for higher Cc. If Cc is increased and the bandwidth needs to be maintained then gmDP needs to be increased by the same factor as Cc, which also has impact on power dissipation. III. SIMULATION AND EXPERIMENTAL RESULTS A. Simulation Results In order to compare the Conventional Approach and Approach I (Fig. 2a without switches in blue) to Approach II (Fig. 2a including switches in blue) discussed above, fully differential bandpass VGAs using Miller op-amps with servo-loops were simulated in 180 nm CMOS technology. Transistor sizes (in µm) were (W/L)N=20/0.5, (W/L)P=120/0.5, and switches (W/L)SW=1/0.22. Capacitors and resistors with values CINT=5 pF, CCM=1 pF, Cc=15 pF, CL=22 pF, Rc=1 kΩ, RCM=100 kΩ, and R=100 kΩ were used. The amplifier was designed with six-bit programmable gain N=6 [GMIN=1 (0 dB) and GMAX=63 (36 dB)]. Dual supplies VDD=0.9 V, VSS=-0.9 V, and bias currents Ibias=25 µA were used. The op-amp had a DC open loop gain AOLDC=60 dB and GB=4.8 MHz. For the purpose of achieving a value fL’ in the Hz range, RLarge was implemented using minimum sized Quasi Floating Gate transistors (QFGs) [16] that have equivalent resistance values RLarge~50 GΩ. Figs. 6 and 7 show plots of fL’ and fH’ as a function of G, respectively. Fig. 6 shows the values of fL’ as a function of the gain |G| in the Conventional Approach and in Approach I (curves a, and b, respectively) and with Cc=15 pF and without Cc in Approach II (curves c and d, respectively). In the first two cases, as expected, fL’ increases with gain according to fL’=fo(1+|G|). Fig. 7 shows the values of fH’ as a function of G. In the Conventional Approach, as expected, fH’ decreases according to fH’=GB/(1+|G|) in the range from 77.7 kHz<fH’<3.44 MHz (note that for low |G| values the high frequency pole introduces an error in the value of fH’). In Approach I fH’ shows variations with increasing |G| in the range from 3.44 MHz to 5.1 MHz and then decreases monotonically to 2.61 MHz. The changes in fH’ are consistent with the values of fH’ calculated using the effective compensation capacitance Cceff with Cc=15 pF, 1<|G|<63 (0 dB<|G|<36 dB), and CgdOUT=0.3 pF. Approach II was simulated with and without Cc (curves c, and d, respectively, in Figs. 6 and 7). 1549-7747 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2808236, IEEE Transactions on Circuits and Systems II: Express Briefs Fig. 6. Low -3 dB frequency fL’ vs |G| in FD-VGAs: (a) Conventional Approach with Cc=15 pF. (b) Approach I with (Cc=15/|G|) pF. (c) Approach II with Cc=15 pF. (d) Approach II with no Cc. Fig. 7. High -3 dB frequency fH’ vs |G| in FD-VGAs: (a) Conventional Approach with Cc=15 pF. (b) Approach I with (Cc=15/|G|) pF. (c) Approach II with Cc=15 pF. (d) Approach II with no Cc. In the case where no Cc was used, the drain-gate capacitance of the output PMOS transistor CgdOUTP~0.3 pF acts as a compensation capacitor and the amplifier is stable for all gains; this is due to the small value β=1/(1+|GMAX|)=1/64 that causes the unity gain frequency of the loop gain to be constant and lower than the high frequency output pole of the op-amp given by fpH=gmoutP/(2πCL). In this case (with CL=22 pF), fpH’~7 MHz. The (constant) values for fH’ with and without compensation capacitance are 77.7 kHz and 4.2 MHz, respectively. It can be seen that Approach II, as expected, provides true constant values for fH’ and fL’ independent of G. The phase margin of the circuit of Approach II also remains constant (not plotted due to space constraints). It has a value of 92o with Cc and 53o without Cc. Another possible way to achieve higher bandwidth without removing/reducing Cc is to utilize power efficient gm boosting techniques. This also increases the open loop gain and consequently reduces the nonlinearity associated to the attenuation introduced by utilization of a constant minimum β factor in as seen in Approach II. B. Experimental Results Fig. 8a shows a test chip prototype including two servo-loop bandpass FD-VGAs (Fig. 2a without switches in blue and controlled by bi low). One with the Conventional Approach (fixed Cc) and the other using Approach I (digitally programmable Cc, Fig. 4). For tests, they had the same parameters (W/L, Cc, etc.) specified in the simulation section. Fig. 8b shows another test chip prototype with two single ended (SE) AC coupled VGAs (SE of Fig. 2b including switches in blue and controlled by bi low) and GMAX=15 (23.5 dB) fabricated to verify Approach II. One of the VGAs had Cc=7.5 pF and the other Cc=1 pF. In this case, transistor dimensions (in µm) were (W/L)N=5/0.7 and (W/L)P=25/0.7, and the feedback capacitor had a value C=1 pF. (a) (b) Fig. 8. Micrograph of fabricated test chips in 180 nm CMOS Technology including: (a) servo-loop bandpass FD-VGAs with Conventional Approach (Fig. 2a) and Approach I (Fig. 4). (b) two SE AC coupled VGAs using Approach II (SE of Fig. 2b), one with Cc=7.5 pF and another with Cc=1 pF. Fig. 9. Experimental and simulated fL’ vs |G| in FD-VGAs using servo-loop: (a) Conventional Approach with Cc=15 pF. (b) Approach I with (Cc=15/|G|) pF. Fig. 10. Experimental and simulated fH’ vs |G| in FD-VGAs using Servo-loop: (a) Conventional Approach with Cc=15 pF. (b) Approach I with (Cc=15/|G|) pF. Fig. 11. Experimental frequency response of AC-coupled VGA with Approach II (Fig. 2b including switches in blue, Cc=7.5 pF) showing constant passband 2 Hz to 350 kHz. Simulated phase response shown in blue which remains the same for all gain settings. 1549-7747 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2808236, IEEE Transactions on Circuits and Systems II: Express Briefs Both chips were fabricated in 180 nm CMOS technology and tested with VDD=0.9 V, VSS=-0.9 V, and Ibias=25 µA. Note that FD or SE implementations do not affect the BW characteristics of any of the approaches. Figs. 9, and 10 show changes in fL’ and fH’ versus |G| for the Conventional Approach and Approach I which are seen to be consistent with the theory discussed in Section II and also with simulation results. Fig. 11 shows the experimental gain and simulated phase response validating the constant passband from fL’=2 Hz to fH’=350 kHz and constant phase for all gains using Approach II (Fig. 2b, Cc=7.5 pF). It can be seen that, as expected, from the discussion in Section II, Approach I has close to a factor 2 bandwidth variation while Approach II has true constant bandwidth, less area, and power dissipation than the other two approaches. Table I summarizes the results of the experimental characterization which are in good agreement with theory assuming CgdOUT~0.3 pF. Linearity is characterized in the Table I in terms of Total Harmonic Distortion THD and Output Intercept Point OIP3 with a 20 mVp-p and 1 kHz input signal for GMAX. The higher THD (lower OIP3) values for Approach II are attributed to the SE implementations. IV. CONCLUSION Two approaches to essentially reduce bandwidth variations in bandpass VGAs based on Miller op-amps were compared. In practice, Approach I has bandwidth variations by approximately a factor two while the second approach has true constant bandwidth/phase margin over the entire gain tuning range. Innovative features of the circuits are the simplicity of Approach I to digitally scale Cc with the reciprocal of the gain and the simple implementation of Approach II that achieves true constant bandwidth. Both approaches have a bandpass response starting from very low cut-off frequencies (~Hz), this prevents amplification of the op-amps offset and blocks the DC components of the input signals. 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TABLE I EXPERIMENTAL RESULTS OF DIFFERENT APPROACHES FOR CONSTANT BANDWIDTH + Parameters [4] 2006 [7] 2008a [5] 2012 [9] 2013 [3] 2014 [6] 2015 [2] 2017 Conv. App.b (Cc=15pF) App. Ib (Cc=15pF) App. IIb (Cc=7.5 pF) App. IIb (Cc=1 pF) CMOS Tech. (nm) 180 500 90 500 500 130 180 180 180 180 180 Supply (V) 1.8 ±3.3 1.2 ±1.65 3.3 1.2 1.8 ±0.9 ±0.9 ±0.9 ±0.9 Config. FD FD FD FD SE FD FD FD FD SE SE CL (pF) - 15 - - - - 2 22 22 22 22 fL’ (Hz) N.A. N.A. 6000000 N.A. - - N.A. 2.5~65 2.5~65 2 2 fH’ (MHz) 30 30a, c 255 1.4 1.9~2.9c 2.8 30 0.088~3.35d 3~5.8e 0.35 2.6 G (dB) -10~20 0~42a 0~40 5~20 0~23.6 0~20 0~14 0~36 0~36 0~23.52 0~23.52 THD (dB) - - - - -87.5 -55 -50.5 -52 -56 -47 -47 OIP3f (dBm) 29.2 - 14 30.5 36.2 - - 33.2 34 24 24 Input Noise (nV/√Hz) 11.2 - 12.5 3 0.54a 62 56 21.5a 21.5a 18a 18a Area (mm2) 0.3 - 0.062 0.25 0.127 0.025 0.052 0.144 0.39 0.028 0.013 Pdiss (mW) 2.43 1.98a 1.56~2.28 0.5 0.28 0.22~0.395 1.044 0.816 0.816 0.172 0.172 FOMg (MHz·pF/mW) N.A.h 227.3a N.A.h N.A.h N.A.h N.A.h 57.47 2.37~90.32 8.88~156.37 44.77 332.56 a Simulated. b Conv. App.: Conventional Approach (Fig. 2a without switches shown in blue and controlled with bi low), App. I: Approach I (Fig. 4 implemented in Fig. 2a without switches shown in blue and controlled with bi low) and App. II: Approach II (Fig. 2b including switches in blue and controlled with bi low). c Approximately constant bandwidth. d fH’ decreases from 3.35 MHz to 0.088 MHz when gain increases from GMIN to GMAX e fH’ increases from 3.35 MHz (at GMIN) to 5.8 MHz, then for |G|>>1, fH’ decreases to 3 MHz (at GMAX) [as discussed in section II-A, remark 3 and section III-A]. f OIP3=P0+HD3/2=P0-(P0-P3)/2 where P0 and P3 (in dBm) are power of fundamental and power of third harmonic respectively. g Figure of Merit FOM=BW·CL/Pdiss (MHz·pF/mW) which BW, and Pdiss are the bandwidth and power consumption of bandpass VGA respectively. h N.A. since CL is not given. View publication stats