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Gain Scheduling PI Voltage Control of Three-phase AC/DC Power Converters

Rodríguez Rubio, Francisco; Vázquez Pérez, Sergio; Castaño Castaño, Luis Fernando; Carrasco Solís, Juan Manuel; Ortega Linares, Manuel Gil

Abstract

This paper present a dc-Link voltage regulation strategy for a two-Level three-phase grid-connected power converter. Control objectives for this system are regulating the dc-link capacitor voltage to a user define set point and, tracking the grid current reference to inject or absorb the requested instantaneous active and reactive power. The proposed voltage controller has a PI Control structure, with adaptation of the gains depending on the observed error. In this way, the monitoring of the voltage reference can be intelligently optimized.

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Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an conference paper published 6th APCA International Conference on Automatic Control and Soft Computing available at: 10.1007/978-3-031-81724-3_49 “© 2025 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” Gain Scheduling PI Voltage Control of Three-phase AC/DC Power Converters Francisco R. Rubio1, Sergio Vazquez2, Fernando Casta˜no1, Juan Manuel Carrasco2, and Manuel G. Ortega1 [1]Dpto. Ingenier´ıa de Sistemas y Autom´atica. Univ. Sevilla. Spain. (e-mail: [email protected], [email protected], [email protected]) [2]Dpto. Ingenier´ıa Electr´onica. Univ. Sevilla. Spain. (e-mail: [email protected], [email protected]) Abstract. This paper present a dc-Link voltage regulation strategy for a two-Level three-phase grid-connected power converter. Control objectives for this system are regulating the dc-link capacitor voltage to a user define set point and, tracking the grid current reference to inject or absorb the requested instantaneous active and reactive power. The proposed voltage controller has a PI Control structure, with adaptation of the gains depending on the observed error. In this way, the monitoring of the voltage reference can be intelligently optimized. Keywords: Power Electronics; Multilevel Converters; PID Control; Adaptive Control 1 Introduction Three phase power converters play a key role in the integration of renewable energy applications. They have attracted extensive attention to academy and industry in the last decades [Carr(2006),Blaa(2004)]. In general, a grid-connected power converter is used as the interphase between the PV panels or the electric generator in wind turbines. The power converter should be able to regulate the dc-link voltage at a certain reference and draw the grid currents with the lowest possible harmonic content. An efficient control strategy cannot only obtain a desired voltage or current signals with low harmonic distortion but also make the structure of controller simple and easy for implementation. In recent years, researches proposed different control approaches to resolve the control problems for three phase power converters [Blaa(2006),Drag(2021)]. Among then, the cascaded linear PI-controller is one of the most popular controllers in practical applications due to its simplicity and easy tuning of parameters. However, one of the main drawbacks is its highly sensitive to the parameter uncertainties. In general, tuning the gains of the PI controller for the entire operating range of the system, means that one must set the gains to achieve a slow response. Therefore, having several sets of controller gains, at least one controller for large reference steps and another one for small changes, can result in a better system performance, theoretically. In this paper, a novel control strategy, namely gain scheduling control strategy, is proposed for the three-phase two-level power converter. Specifically, a 2 F.R. Rubio et al. gain scheduling controller is designed in the outer control loop regulating the dc-link capacitor voltage. The idea is to design several PI controllers at different operating points of the controller and switch the parameters of these PIs, so that the system response is enhanced in the complete operating range of the power converter. As a first approach, two sets of PI parameters are designed, one for situations in which the reference changes are large and another for small changes. In this way, the proposed gain scheduling scheme can solve the control problem keeping a simple control structure. The outline of the paper is as follows. After the Introduction, Section 2 describes the three-phase two-level grid-connected power converter used in this paper. Section 3 focuses on the design of the cascade control structure with adjustable gain. The Section 4 shows the simulation outcomes and provides analysis of the results. Section 5 summarizes the research and concludes the paper based on the previous results. 2 System Description The electric circuit of the system under research is depicted in Fig. 1. The system consists of a three-phase two-level voltage source inverter (VSI) connected to the grid through a smoothing inductive filter Lwith a series resistor rrepresenting the Joule’s losses in the filter. The output voltage vector generated by the VSI is uabc and its components uaN ,ubN and ucN can be computed as: uaN =vdcSa,(1) ubN =vdcSb,(2) ucN =vdcSc.(3) These components represent the voltages between points aN,bN and cN, respectively. The signals, Sa,Sband Scdescribe the state of the power switches. For the three-phase two-level VSI: Sx|x=a,b,c ∈ {0,1},(4) if Sx= 1 then the upper power switch of phase xis on and the lower is off. On the contrary, if Sx= 0 then the upper power switch is off and the lower is on. Taking into account (1)-(3) it is possible to define the relationship between uabc and the switching function vector Sabc as: uabc =vdcSabc,(5) The grid voltage and current vectors are represented by vabc and iabc, respectively. The voltage of the dc-link capacitor with capacitance Cis vdc. Finally, the load connected to the dc-link capacitor is characterized by the resistor RL. All system variables and parameters are collected in Table 1. Adaptive PI Voltage Control of Converters 3 load i L R load C dc v a u a u L an v n r a i bn v cn v r r L L b i c i b u c u b u c u N a b c + + + + - Fig. 1. Electric circuit of the three-phase two-level grid-connected power converter. Table 1. Variables and Parameter of the system Description Variable Unit VSI output voltage vector uabc = [uaN ubN ucN ]TV Grid voltage vector vabc = [vavbvc]TV Grid current vector iabc = [iaibic]TA Switching function vector Sabc = [SaSbSc]TA DC-Link capacitor voltage vdc V DC-Link capacitor capacitance CF Grid filter inductance LH Grid filter resistance r Ω Load resistance RLΩ Sampling frequency fsHz 2.1 System Dynamic Model As shown in Fig.1, the system under investigation is a three-phase two-level power converter connected to the grid. An unknown load RLis connected to dc-link capacitor of the power converter. This load is regarded as an unknown slow-varying external disturbance to the system. The mathematical model of the converter in dq synchronous reference frame is as follows [Blas(1997)]: Ldid dt =−rid+ωLiq+vd−ud,(6) Ldiq dt =−riq−ωLid+vq−uq,(7) Cvdc dvdc dt =udid+uqiq−vdciload,(8) 4 F.R. Rubio et al. where, vd, vqare grid voltages, id, iqare grid currents, vdc is the dc-link voltage, ωis the frequency of grid voltage, iload is the load current and ud, uqare the VSI voltage represented in the dq synchronous reference frame (SRF). The voltage vector udq ={uduq}Tis the system input, thus this value is used to control the system outputs. It is considered that the switching frequency fsw is much larger that the fundamental frequency of the grid current references, thus an average model describes the system and, the voltage udq are generated by means of a PWM stage [Leon(2016)]. In order to transform from abc frame to dq synchronous reference frame via Park’s transformation, a PLL should be included in the system [Vazq(2014]. 2.2 Control Objectives There are two control objectives concerning the three-phase two-level power converter connected to the grid: Voltage regulation The dc-link voltage vdc of the converter should be driven to a desired value v⋆ dc. vdc →v⋆ dc.(9) Current tracking The currents id,iqshould track the corresponding reference currents i⋆ d,i⋆ q. id→i⋆ d, iq→i⋆ q,(10) where, i⋆ dis calculated based on the vdc control, ensuring vdc to approach v⋆ dc, whereas, i⋆ qis set to a certain value to achieve a desired power factor. 3 Controller Scheme For the two control objectives described in the section 2.2, a cascaded control scheme is employed for the power converter, which includes a current tracking loop as inner control loop and a voltage regulation loop as outer control loop. Therefore, the separation principle must be considered when designing the controller gains. 3.1 Current Tracking Loop Fig.2 shows the current tracking loop based on conventional linear PI control under SRF [Blas(1997)]. µdand µqare the output signal of the PI controllers of d-axis and q-axis, which are defined as µd=kpideid +kiid Zeiddt, (11) µq=kpiqeiq +kiiq Zeiqdt, (12) Adaptive PI Voltage Control of Converters 5 where eid =i⋆ d−id, and eiq =i⋆ q−iq. Then, based on (6) and (7), the following signals can be obtained: ud= (−µd+vd+ωLiq),(13) uq= (−µq+vq−ωLid),(14) where udand uqare the final output control signals for both axes. 3.2 Voltage Regulation Loop Fig.3 shows the control structure of the voltage regulation loop, where µvdc is the output of a PI controller. From (8) and taking into account that current tracking loop is faster than the outer control loop, then, the dc-link voltage dynamic can be formulated as: Cvdc dvdc dt = (p⋆−pload),(15) where p⋆= (udi⋆ d+uqi⋆ q) (16) and pload =vdciload.(17) Denoting (v⋆ dc)2.2 = z⋆ 1,V2 dc2 = z1,p⋆=uas the control signal and pload =das an external disturbance, (15) can be rewritten as: C˙z1=u−d=µvdc −d, (18) where µvdc =Kpvdcev+Kivdc Zevdt, (19) and ev=z⋆ 1−z1. 3.3 Stability of the Voltage Regulation Loop From the equations (18) and (19) and differentiating, one can obtain the equation (20): C¨z1=Kpvdc ˙ev +Kivdcev −d, (20) and substituting the value ev =z∗ 1−z1(21): C¨z1+Kpvdc ˙z1+Kivdcz1=Kivdc ∗z∗ 1,(21) From the previous equation (21), it can be deduced that the system is stable for all Kpvdc,Kivdc, greater than zero. 6 F.R. Rubio et al. d i ? d i d v PI q i ? q i d u q u q v PI + - + + + + - - - -d ¹ q ¹ Fig. 2. Current tracking loop. 12 2 PI * dc V ? 1 z ¹ vdc 1 z dc V (•) 12 2 (•) - + Fig. 3. Voltage regulation loop compensated by disturbance observer. 3.4 Gain scheduling control Gain scheduling control is a control scheme with open-loop adaptation, which can be seen as a feedback control system in which the feedback gains are adjusted by a feed-forward compensation. Gain scheduling control is a nonlinear feedback of a special type: it posses a linear controller which parameters are modified depending on the operating conditions in a pre-specified manner. The working principle of this kind of controllers ([Rubio(1996]), is simple, and it is based on the possibility of finding auxiliary variables which guarantee a good correlation with process changing dynamics. This way, it is possible to reduce the effects of variations in the plant dynamics by adequately modifying the controller parameters as functions of auxiliary variables. So, an essential problem is the determination of the auxiliary variables. In the case studied here, the behaviour and changes in the system dynamics mainly depend on the reference voltage. So, the reference error are used to point the controller parameters table. Once the auxiliary variables have been determined, the controller parameters have to be calculated in a determinate number of operating points. This way, the controller is adjusted for those selected operating points. In this case, two PI controllers have been adjusted, one for large variations in the reference and another Adaptive PI Voltage Control of Converters 7 - - - - 6 r e Controller u Process y CC CCW  Adjustment mechanism Auxiliary variable Operating condition Fig. 4. Diagram of the gain scheduling structure for minor ones. When coping with gain scheduling control schema, stability and performance of the controlled system is usually evaluated by simulation studies. A crucial point here is the transition between different operating points. In those cases in which a non-satisfactory behaviour is obtained, the number of inputs to the table of controller parameters must be augmented. As has been mentioned, it is important to point out that there exists no feedback from the behaviour of the controlled system to the controller parameters. So, this control scheme is not considered as an adaptive one, but a special case of a nonlinear controller. 4 Simulation Results Simulations are provided to demonstrate the properties of the proposed controller, compared to a fixed gains set one. The simulation of the case of the fixed PI and the case in which it is adapted with two PIs are carried out. The gain scheduling is designed such as one set of parameter focuses for the part in which the reference is far from the voltage reference, and the other set deals with a situation were the dc-link capacitor voltage is close to the reference. The table 2 shows the parameters of the PI that have been designed for the outer control loop when fixed values are used. Two different sets are chosen, the first ones provides a slow response while the second one permits a fast transient. On the other hand, table 3 shows the PI gains when the scheduling mechanism is used. The gain scheduling is activated when the dc-link voltage is close to its reference. Therefore, the variable ∆vdc =v⋆ dc −vdc is chosen to activate the mechanism as defined in the table. Note that for large errors, |∆vdc| ≥ 10 V, the 8 F.R. Rubio et al. Table 2. PI gain values Kpvdc Kivdc Slow PI 0.2 5 Fast PI 0.8 22 Table 3. PI gain values with scheduling Kpvdc Kivdc |∆vdc| ≥ 10 V 0.2 5 |∆vdc|<10 V 0.8 22 PI gains are set equal to the slow PI. However, if the error is small |∆vdc|<10 V, then the fast PI gains are used. First, a simulation of the converter was carried out with the fixed set of gains for the controller corresponding to the slow PI in table 2. This tuning is suitable for the complete operating range of the converter. In Fig. 5, the results are shown, where the grid voltage, grid currents and dc-link capacitor voltage vdc can be observed. It can be seen how the voltage presents over and under voltage to reach the reference and to reject the disturbance, respectively. As the controller was designed taking into account the entire operating range, the settling time is slow. In Fig. 6, the simulation is shown for the case of having two set of gains for the PI of the outer control loop with the gain scheduling scheme. Results confirm that dc-link voltage regulation is better than the previous case, when using a controller with gain adjustment like the one in Fig. 4. Both the reference step tracking and the elimination of the disturbance are carried out more quickly and with a reduced oscillations. A third simulation in Fig. 7 shows the system response for the fixed set of gains corresponding to the fast PI in table 2. The idea is to confirm that this set is not suitable for the system operation. This is demonstrated as the currents during the initial transient reach values higher than 100 A, which can destroy the power semiconductors if they are not chosen considering this situation. This transient forces to oversize the power semiconductor increasing the cost of the system. To operate the gain scheduling scheme, the switching variable between the two controllers is the error between the reference and the measured voltage vdc. In Fig. 8, the signal used to switch between the two controllers is represented. The calculation of the control signal is carried out in a coordinated manner to avoid possible switching jumps. Finally, the grid current spectrum is shown for the fixed PI with slow gains in Fig. 9 and with the gain scheduling mechanism in Fig. 10. The results show that