CMOS RF front-end receivers for DVB-SH

        CMOS RF front-end receivers for DVB-SH   Hugo García Vázquez  !"# Diciembre de 2013 D. ………………………………………… SECRETARIO DEL INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA DE LA UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA, CERTIFICA, Que el Consejo de Doctores del Departamento en su sesión de fecha ……………………. tomó el acuerdo de dar el consentimiento para su tramitación, a la tesis doctoral titulada ”CMOS RF front-end receivers for DVB-SH” presentada por el doctorando D. Hugo García Vázquez y dirigida por los doctores D. Francisco Javier del Pino Suárez y D. Sunil Lalchand Khemchandani. Y para que así conste, y a efectos de lo previsto en el Artº 6 del Reglamento para la elaboración, defensa, tribunal y evaluación de tesis doctorales de la Universidad de Las Palmas de Gran Canaria, firmo la presente en Las Palmas de Gran Canaria, a ….. de Diciembre de dos mil trece. Departamento: Instituto Universitario de Microelectrónica Aplicada Programa de doctorado: Ingeniería de Telecomunicación Avanzada Título de la Tesis CMOS RF front-end receivers for DVB-SH Tesis Doctoral presentada por D. Hugo García Vázquez Dirigida por el Dr. D. Francisco Javier del Pino Suárez Codirigida por el Dr. D. Sunil Lalchand Khemchandani El Director, El Codirector, El Doctorando, (firma) (firma) (firma) Las Palmas de Gran Canaria, a _____ de_________________ de 20__ Agradecimientos En primer lugar quiero darles las gracias a mis directores el doctor F. Javier del Pino Su´arez y el doctor Sunil Lalchand Khemchandani por toda la ayuda que me han prestado en todos los sentidos a lo largo de estos a˜nos. A la Agencia Canaria de Investigaci´on Innovaci´on y Sociedad de la Informaci´on (ACIISI) que ha sido la que me ha financiado para poder realizar mi tesis doctoral a trav´es del ”Programa de ayudas de Formaci´on del Personal investigador, de la Agencia Canaria de Investigaci´on, Innovaci´on y Sociedad de la Informaci´on del Gobierno de Canarias y la cofinanciaci´on y tasa de cofinanciaci´on del F.S.E”. Adem´as, me ha financiado para poder realizar una estancia en la Universidad de Mons durante 3 meses a trav´es de las ”Ayudas destinadas a la Formaci´on de Personal Investigador para la realizaci´on de estancias breves en Espa˜na y en el extranjero”. Al doctor Carlos Valderrama, al doctor Carlos Fortunato y a Papy Ndungidi que me acogieron como uno m´as de su equipo durante mi estancia en la Universidad de Mons. Al Instituto Universitario de Microelectr´onica Aplicada (IUMA) por permitirme utilizar sus instalaciones y recursos. Sin olvidar por supuesto, al Servicio de Infraestructura de Red del IUMA que me han sacado de tantos apuros. A los compa˜neros del laboratorio Dailos, Roberto, Rub´en, Gustavo, Jonathan y Enara. A Tomasz, Krisnaya, V´ıctor y a todas esas personas que han estado ah´ı para todo lo que me hizo falta. Por ´ultimo quiero agradecer a mis amigos, a Sarah, a mis hermanos Teo y Laura y a mis padres Juan Antonio y MaAuxiliadora por todo, ya que son los m´as importante de mi vida. A mi familia Contents Contents i List of Figures v List of Tables xi Nomenclature xiii 1 Introduction 1 1.1 Introduction................................ 1 1.2 Objectives................................. 6 1.3 Outline of the research . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 DVB-SH overview and system approach 9 2.1 Introduction................................ 9 2.2 DVB-SH receiver specifications . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 Frequencyrange.......................... 15 2.2.2 C/Nrequirements......................... 15 2.2.3 Maximum input levels . . . . . . . . . . . . . . . . . . . . . . 16 2.2.4 Noisefigure ............................ 16 2.2.5 Sensitivity............................. 17 2.2.6 Dynamicrange .......................... 17 2.2.7 Dynamicgain........................... 18 ii CONTENTS 2.2.8 Linearity.............................. 18 2.2.9 Adjacent channel selectivity . . . . . . . . . . . . . . . . . . . 20 2.2.10Phasenoise ............................ 21 2.3 Multi-objectives optimisation method . . . . . . . . . . . . . . . . . . 23 2.4 Conclusion................................. 28 3 RF front-ends for a DVB-SH receiver 29 3.1 Introduction................................ 29 3.2 Description of the UMC 90 nm technology . . . . . . . . . . . . . . . 29 3.3 Receiver1................................. 32 3.3.1 Circuits analysis . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.1.1 Low noise amplifier . . . . . . . . . . . . . . . . . . . 33 3.3.1.2 Single to differential converter . . . . . . . . . . . . . 35 3.3.1.3 Mixer .......................... 37 3.3.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 Receiver2................................. 44 3.4.1 Circuits analysis . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.1.1 Low noise amplifier . . . . . . . . . . . . . . . . . . . 44 3.4.1.2 Mixer .......................... 47 3.4.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 Receiver3................................. 51 3.5.1 Circuits analysis . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.1.1 Low noise amplifier . . . . . . . . . . . . . . . . . . . 52 3.5.1.2 Single to differential converter . . . . . . . . . . . . . 54 3.5.1.3 Mixer .......................... 54 3.5.2 Experimental results . . . . . . . . . . . . . . . . . . . . . . . 56 3.6 Conclusions ................................ 60 4 Package 63 4.1 Introduction................................ 63 4.2 Packagemodelling ............................ 66 4.3 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4 Conclusions ................................ 77 CONTENTS iii 5 Conclusions and Areas for Further Research 79 5.1 Conclusions ................................ 79 5.2 Areas for further research . . . . . . . . . . . . . . . . . . . . . . . . 83 A Resumen en Castellano 85 A.1 Introducci´on................................ 85 A.1.1 Objetivos ............................. 87 A.1.2 Estructura de la memoria . . . . . . . . . . . . . . . . . . . . 88 A.2 An´alisis del sistema . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 A.2.1 Objetivos ............................. 91 A.2.2 Planteamiento y metodolog´ıa . . . . . . . . . . . . . . . . . . 91 A.2.2.1 Especificaciones del receptor de radiofrecuencia para DVB-SH......................... 91 A.2.2.2 M´etodo de optimizaci´on de multi-objetivos . . . . . . 100 A.2.3 Aportaciones originales . . . . . . . . . . . . . . . . . . . . . . 106 A.2.4 Conclusiones obtenidas . . . . . . . . . . . . . . . . . . . . . . 106 A.3 Cabezales de radiofrecuencia para un receptor de DVB-SH . . . . . . 107 A.3.1 Objetivos .............................107 A.3.2 Planteamiento y metodolog´ıa . . . . . . . . . . . . . . . . . . 107 A.3.2.1 Descripci´on de la tecnolog´ıa UMC 90 nm . . . . . . . 107 A.3.2.2 Receptor 1 . . . . . . . . . . . . . . . . . . . . . . . 110 A.3.2.3 Receptor 2 . . . . . . . . . . . . . . . . . . . . . . . 122 A.3.2.4 Receptor 3 . . . . . . . . . . . . . . . . . . . . . . . 129 A.3.3 Aportaciones originales . . . . . . . . . . . . . . . . . . . . . . 138 A.3.4 Conclusiones obtenidas . . . . . . . . . . . . . . . . . . . . . . 138 A.4 Encapsulado................................141 A.4.1 Objetivos .............................141 A.4.2 Planteamiento y metodolog´ıa . . . . . . . . . . . . . . . . . . 141 A.4.2.1 Modelado del encapsulado . . . . . . . . . . . . . . . 144 A.4.2.2 Resultados experimentales . . . . . . . . . . . . . . . 150 A.4.2.3 Aportaciones originales . . . . . . . . . . . . . . . . . 154 A.4.2.4 Conclusiones . . . . . . . . . . . . . . . . . . . . . . 154 A.5 Conclusiones y l´ıneas futuras . . . . . . . . . . . . . . . . . . . . . . . 157 A.5.1 Conclusiones ...........................157 iv CONTENTS A.5.2 L´ıneas futuras de trabajo . . . . . . . . . . . . . . . . . . . . . 161 References 163 B Publications 171 C Other Publications 173 List of Tables 1.1 FREQUENCY ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . 3 2.1 FREQUENCY ALLOCATIONS FOR SATELLITES . . . . . . . . . 14 2.2 C/N REQUIREMENTS FOR AWGN CHANNELS . . . . . . . . . . 15 2.3 C/N REQUIREMENTS FOR RICE AND RAYLEIGH CHANNELS 15 2.4 C/N REQUIREMENTS FOR COFDM-TU6 CHANNELS . . . . . . 16 2.5 LINEARITY PATTERNS . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 SELECTIVITY REQUIREMENTS FOR DVB-SH . . . . . . . . . . 20 2.7 MINIMUM AND MAXIMUM LEVELS FOR LO PHASE NOISE . . 22 2.8 RF FRONT-END SPECIFICATIONS . . . . . . . . . . . . . . . . . 22 2.9 PARAMETERS OF EACH BLOCKS . . . . . . . . . . . . . . . . . . 24 2.10FEASIBLEVALUES........................... 26 2.11 SPECIFICATIONS OF EACH BLOCK . . . . . . . . . . . . . . . . . 28 3.1 RF FRONT-END 1 RESULTS . . . . . . . . . . . . . . . . . . . . . 42 3.2 RF FRONT-END 2 RESULTS . . . . . . . . . . . . . . . . . . . . . 49 3.3 RF FRONT-END 3 RESULTS . . . . . . . . . . . . . . . . . . . . . 58 3.4 RF FRONT-ENDS RESULTS . . . . . . . . . . . . . . . . . . . . . . 61 4.1 EQUIVALENT INDUCTANCES . . . . . . . . . . . . . . . . . . . . 72 5.1 RF FRONT-ENDS RESULTS . . . . . . . . . . . . . . . . . . . . . . 81 A.1 FRECUENCIAS SAT´ ELITE ASIGNADAS . . . . . . . . . . . . . . . 92 xii LIST OF TABLES A.2 C/N PARA CANAL AWGN . . . . . . . . . . . . . . . . . . . . . . . 93 A.3 C/N PARA CANALES RICE Y RAYLEIGH . . . . . . . . . . . . . 93 A.4 C/N PARA CANAL COFDM-TU6 . . . . . . . . . . . . . . . . . . . 93 A.5 PATRONES DE LINEALIDAD . . . . . . . . . . . . . . . . . . . . . 97 A.6 REQUISITOS DE SELECTIVIDAD PARA DVB-SH . . . . . . . . . 98 A.7 NIVELES M´ INIMO Y M´ AXIMO PARA EL RUIDO DE FASE . . . 99 A.8 ESPECIFICACIONES DEL RECEPTOR . . . . . . . . . . . . . . . 100 A.9 PAR´ AMETROS DE CADA BLOQUE . . . . . . . . . . . . . . . . . 102 A.10 RANGO DE LOS BLOQUES . . . . . . . . . . . . . . . . . . . . . . 104 A.11 ESPECIFICACIONES DE CADA BLOQUE . . . . . . . . . . . . . . 105 A.12 RESULTADOS RECEPTOR 1 . . . . . . . . . . . . . . . . . . . . . 119 A.13 RESULTADOS RECEPTOR 2 . . . . . . . . . . . . . . . . . . . . . 126 A.14 RESULTADOS RECEPTOR 3 . . . . . . . . . . . . . . . . . . . . . 134 A.15 RESULTADOS OBTENIDOS RECEPTORES . . . . . . . . . . . . . 138 A.16 INDUCTANCIAS EQUIVALENTES ASOCIADAS . . . . . . . . . . 149 A.17 RESULTADOS OBTENIDOS RECEPTORES . . . . . . . . . . . . . 158 Nomenclature 3D-EM Three Dimensions-Electromagnetic 3G Third Generation A/D Analogue/Digital ACS Adjacent Channel Selectivity ADC Analogue-to-Digital Converter ADS Advanced Design System AIP3 Amplitude of the Third Order Intercept Point AWGN Additive White Gaussian Noise BER Bit Error Rate BW Bandwidth C/N Carrier-to-Noise ratio CCIII Third Generation Current Conveyor CCII Second Generation Current Conveyor CCI First Generation Current Conveyor CC Current Conveyor xiv CGC Complementary Ground Component CMOS Complementary Metal-Oxide-Semiconductor COFDM Coded Orthogonal Frequency Division multiplexing COX Oxide Capacitance CR Code Rate DC Direct Current DFM Design For Manufacturability DVB-H Digital Video Broadcasting for Hand-held terminals DVB-SH Digital Video Broadcasting, Satellite Services to Hand-held DVB-T Digital Video Broadcasting for Terrestrial services EDA Electronic Design Automation EICTA European Information and Communications Technology Industry Association EMDS Electromagnetic Design Simulator FDK Foundry Design Kit FEC Forward Error Correction FPGA Field Programmable Gate Array FNoise Factor GPU Graphics Processing Unit GSM Global System for Mobile Communications I2CInter-Integrated Circuit I/Q In-phase/Quadrature IC Integrated Circuit xv IF Intermediate Frequency IIP2 Second Order Intercept Point IMD3 Intermodulation Distortion from the third order IP3 Third-order Intercept Point IP Intellectual Property LNA Low Noise Amplifier LOS Line Of Sight LO Local Oscillator MBRAI Mobile Broadband Radio Air Interface MIM Metal Insulator Metal MOM Metal Oxide Metal MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor MS Mixed Signal NF Noise Figure NMOS Negative-channel Metal-Oxide Semiconductor NSGA Non-dominated Sorting Genetic Algorithm OCF Optimum Capacitor Finder OFDM Orthogonal Frequency Division multiplexing OIF Optimum Inductor Finder OTF Optimum Transformer Finder P1dB Compression Point PAL Phase Alternating Line xvi PCB Printed Circuit Board PLL Phase-Locked Loop QAM Quadrature Amplitude Modulation QFN Quad-Flat No-leads package QoS Quality of Service QPSK Quadrature Phase-Shift Keying QQuality RF Radio frequency SAW Surface Acoustic Wave SC Satellite Component SDC Single to differential converter SNR Signal-to-Noise Ratio SoC System on Chip TCXO Temperature Compensated Crystal Oscillator TDM Time Division Multiplexing TRs Terrestrial repeaters TU6 Typical Urban channel with 6 taps. TV Television UHF Ultra High Frequency UMC United Microelectronics Corporation UMTS Universal Mobile Telecommunications System USB Universal Serial Bus xvii VCO Voltage-Controlled Oscillator VHF Very High Frequency 1 Introduction 1.1 Introduction A report from the Cisco Visual Networking Index Services Adoption Forecast predicts that by the year 2017 mobile digital television will be demanded by over 400 million users worldwide [1]. The revolution that communication technologies are experiencing clearly shows how this demand is going to be satisfied. So, the media has to adapt itself to the mobile environment, developing new services and setting up new business possibilities. The problem is that nowadays, third generation mobile companies only offer some limited TV services (point-to-point). The solution to such a limitation is the deployment of broadcasting networks devoted to mobile TV (point to multipoint) and this is the idea behind the DV B-H(Digital Video Broadcasting for Hand-held terminals) [2] communication standard. This network forms part of the terrestrial infrastructure previously deployed for DV B-T(Digital Video Broadcasting for Terrestrial services) [3]. Both communication standards share the physical layer, along with transmission at UHF band. However, DV B-Hhas been developed so that the average receiver power consumption is smaller. UHF band was also an impediment to the development of DV B-H in Europe because of band saturation, at least until the analogue shutdown. Another problem is the amount of money needed for DV B-Hcoverage in large areas, larger than the investment required for DV B-T[4]. Therefore, DV B-Hdeployment far from urban areas is not feasible. DV B-SH (Digital Video Broadcasting, Satellite Services to Hand-held) [5][6][7] is a solution to the above mentioned drawbacks. DV B-SH is the evolution of DV B- 2 Hin the sense that the network is a hybrid terrestrial satellite network (see figure 1.1). Three kinds of terrestrial repeaters (TRs) are envisaged: •TRs(a) are broadcast infrastructure transmitters which complement reception in areas where satellite reception is difficult, especially in urban areas; they may be collocated with mobile cell sites or standalone. Local content insertion at that level is possible, relying on adequate radio frequency planning and/or waveform optimizations. •TRs(b) are personal gap-fillers of limited coverage providing local retransmission, on-frequency and/or with frequency conversion; typical application is indoor coverage provision, locally repeating the satellite signal available outdoor. No local content insertion is foreseen. •TRs(c) are mobile broadcast infrastructure transmitters creating a ”moving complementary infrastructure” on board moving platforms (cars, trains, bus). Depending on waveform configuration and radio frequency planning, local content insertion may be possible. Figure 1.1: DVB-SH system architecture (extracted from [5]). 2 DVB-SH overview and system approach 2.1 Introduction DV B-SH [5][6][7] is based on the DV B-Hstandard (see figure 2.1). DV B-H merges the two best-selling consumer products in history, TV s and cellular phones. DV B-Htechnology adapts the system for digital terrestrial television (DV B-T), to the specific requirements of hand-held, battery-powered receivers. DV B-Hcan offer a downstream channel at high data rates which can be used standalone or as an enhancement of mobile telecom networks which many typical hand-held terminals are able to access anyway [11][12]. DV B-SH includes some improvements in error correction algorithms in the physical and link layer levels in comparison with DV BH. There are key differences from DV B-Hthat should be kept in mind, due to the hybrid-network nature of DV B-SH: •When the 2 GHz S-band is used, synergy with 3Gtelephony infrastructure should be exploited, especially in areas where such infrastructure exists. Network planning for DV B-SH in urban areas could be similar to the 3Gplanning with the benefit that indoors coverage could be made essentially the same. •ADV B-SH coverage is always composed of satellite coverage complemented by terrestrial coverage. The services offered by these two kinds of coverage are strongly linked but not necessarily the same. •As a consequence of the above, DV B-SH services are a mix of common services and local services. Common services are services that are available in 10 Figure 2.1: DV B-SH supported spectrum (extracted from [13]). the satellite component (SC) and must be transmitted in the complementary ground component (CGC). Local services are services that are available in the CGC only. Common services are usually those with very large audiences while local services have more fragmented audiences, possibly with geographical dependencies. A local service package for one city/town may differ from the package for another city/town. •There are challenges for DV B-SH due to higher mobility, satellite specific propagation channels, and, in some cases, higher frequency bands. •Although the common services are available in both the SC and the CGC, the service attributes may differ depending on the user location, more precisely between different reception modes: satellite-only, terrestrial-only and combined satellite-terrestrial receptions. For example, specific physical parameters may be selected so that higher user speed is possible with satellite-only reception. •DV B-SH interactive services would rely mainly on a terrestrial return channel which could be independent from its CGC. It should be noted that the technical possibility exists, in the 2 GHz S-band, to establish a direct return path via satellite. Such a possibility could be invaluable in catastrophic events leading to unavailability of terrestrial infrastructures. DVB-SH overview and system approach 11 This network uses COFDM (Coded orthogonal frequency division multiplexing) in the complementary network and COFDM or TDM (Time division multiplexing) signals in satellite transmission. COFDM allows single frequency network deployment, and if that is the case, receivers may combine all signals arriving from nearby transmitters (including the satellite), under the assumption that signal delays are smaller than the guard interval of OFDM signals. TDM signals allow larger transmitted power levels from the satellite. As two physical layers are available, there are more system configurations. Two different architectures have been defined: •SH-Aarchitecture: both satellite/terrestrial components use OFDM. •SH-Barchitecture: the satellite component uses TDM, and the terrestrial component uses OFDM. SH-Aarchitecture allows both single frequency networks and multi-frequency networks. SH-Bterminals are compatible with SH-Aarchitectures but they can operate in a single frequency network or in a multi-frequency network. The opposite is not true. In order to cope with a wide market, DV B-SH offers great flexibility in the development of terminals. The standard identifies up to three different categories: •Category 1: car-mounted terminals (vehicular). •Category 2: portable TV devices, with two subcategories: –2.a Large screen ( ≥10”) portable devices, battery or mains powered. –2.b Pocket table (hand-held) TV devices, mainly battery powered. •Category 3: hand-held terminal with embedded cellular telecom modem. Figures 2.2 and 2.3 show two proposals for categories 1 y 3. 12 Figure 2.2: Category 1: proposed architecture. Figure 2.3: Category 2: proposed architecture. In most common cases the channel conditions are those produced by a pedestrian user (<3 km/h). Due to the relatively low speed, continuity of service is in general achieved by increasing the link margin, rather than by increasing the time interleaving depth. When in satellite-only reception mode, some cooperation may be required from the user, i.e. to maintain good LOS (Line Of Sight) with the satellite. Some challenges are associated with the specifications of hand-held terminals. These include: •Antenna diversity (an order more than 2 is very challenging). •Small battery requires an efficient power saving management. •Antenna gain is in general low (can be less than -3 dBi). DVB-SH overview and system approach 13 •Antenna polarisation is most often linear and not optimized to satellite reception. •Embedding telecom modems like GSM or 3Ginside the terminal without reducing the satellite receiver sensitivity. •RF filtering, antenna design rules and compactness constraints have an impact on the achievable receiver sensitivity and immunity to high level blockers coming from the terminal. •Memory limitation may, in some architectures, not allow the support of a large Physical Layer interleaver. A category 3 terminal was chosen for its use in SH-Bnetworks. On the one hand, a category 3 terminal involves a bigger challenge since its requirements for a correct demodulation are more difficult to achieve. On the other hand, a terminal compatible with SH-Bnetworks allows its use in SH-Anetworks. 2.2 DVB-SH receiver specifications In this section, the requirements for the tuner performance are extracted. To derive these requirements, the DV B-SH implementation guide [5] was used as well as EICTA MBRAI [14]. Despite [14] not being a document which belongs to the DV B-SH standard, some of its assumptions are still considered valid. A direct conversion receiver architecture (zero-IF) was chosen for this work. Figure 2.4 shows the direct conversion receiver block diagram, where the LO frequency is equal to the input carrier frequency. Note that channel selection only requires a low pass filter with relative sharp cut-off characteristics. This architecture has several issues. First, in a direct conversion topology, the down converted band extends to zero frequency. As a result, offset voltages can corrupt the signal and saturate the following stages. This issue is also related to the LO leakage because the LO radiation could appear as a DC voltage at the receiver output. Secondly, phase and frequency modulation require shifting either RF or LO signal output by 90o. This shifting generally introduces errors and noise. Due to this error I/Qmismatches could appear, thereby raising the bit error rate. Thirdly, in baseband, the even-order harmonics could be inside the desired channel. 14 Figure 2.4: Reference receiver used in the design. Fourthly, due to the fact that the desired channel is translated directly to baseband, the flicker noise could affect the signal. On the contrary, the simplicity of the direct conversion architecture offers two important advantages. Firstly, the problem of the image frequency does not appear. As a result, no image filter is required. Secondly, the IF-SAW filter and other down-conversion stages, used for instance in heterodyne receivers, are replaced with low-pass filters and baseband amplifiers, so this architecture is more suitable for a monolithic integration with a relatively low area and low power consumption. The receiver performance is defined according to the reference point shown in figure 2.4. Freq. band designation Frequency range 2 GHz S Band 1980-2010 MHz(uplink) 2170-2200 MHz(downlink) S-DARS S Band 2320-2345 MHz(downlink) 2.5 GHz S Band 2670-2690 MHz(uplink) 2.5 GHz S Band 2500-2520MHz(downlink) 2.5 GHz S Band 2520-2670 MHz(downlink) TABLE 2.1: FREQUENCY ALLOCATIONS FOR SATELLITES DVB-SH overview and system approach 15 2.2.1 Frequency range Due to the versatility of the DV B-SH standard, it can be implemented in UHF, Land SBands. The downlink frequency for the Sband is allocated (see table 2.1) between 2170 MHz and 2200 MHz [15]. 2.2.2 C/N requirements The C/N values are a function of the modulation type, the physical layer code rate and the physical layer interleaving time. Tables 2.2, 2.3 and 2.4 show the different requirements for the different channels and modulations. The worst case is for the QPSK in a TDM-AWGN channel. The minimum theoretical carry to noise ratio C/N required by the system is -3.9 dB. OFDM-AWGN channel TDM-AWGN channel CR QPSK 16QAM QPSK 8PSK 16 PSK 1/5 -3.6 0.7 -3.9 -1.3 0.4 2/9 -3.1 1.3 -3.4 -0.7 1.0 1/4 -2.5 1.9 -2.8 -0.1 1.6 2/7 -1.8 2.8 -2.1 0.7 2.5 1/3 -0.9 3.7 -1.2 1.6 3.4 2/5 0.1 5.0 -0.2 2.7 4.7 1/2 1.4 6.8 1.1 4.4 6.5 2/3 3.5 9.7 3.2 6.9 9.4 TABLE 2.2: C/N REQUIREMENTS FOR AWGN CHANNELS TDM-Rice channel(K=3dB) TDM-Rayleigh channel CR QPSK QPSK 1/5 -3.4 -3.2 1/4 -2.2 -2.1 1/3 -0.4 -0.2 1/2 2.2 2.9 TABLE 2.3: C/N REQUIREMENTS FOR RICE AND RAYLEIGH CHANNELS 16 QPSK 16QAM CR-INT 3 km/h 50 km/h CR-INT 3 km/h 50 km/h 1/2-S 6.5 dB 4.5 dB 1/3-S 8.5 dB 6.5 dB 1/2-UL 5.5 dB 4 dB 1/3-UL 7 dB 6 dB 1/3-S 3.5 dB 1.5 dB 1/4-S 6.5 dB 5 dB 1/3-UL 2.5 dB 1 dB 1/4-UL 5 dB 4 dB 1/5-S 5.5 dB 3 dB 1/5-UL 4 dB 3 dB TABLE 2.4: C/N REQUIREMENTS FOR COFDM-TU6 CHANNELS 2.2.3 Maximum input levels The maximum total average power that can be present at the antenna for wanted and unwanted signals is 15 dBm assuming 15 to 18 dB coupling between UMTS and DV B-SH antennas. If the RF filter has a minimum attenuation of 40 dB at UMTS uplink band, the maximum total average power at reference point is -25 dBm. For the in-band interferers, there is no description given in [5]. So, the EICTA MBRAI [14] is going to be used as a reference to follow. It is possible because DV B-SH and DV B-Hare both similar mobile TV broadcasting standards. So, if the same specifications of DV B-Hare used for DV B-SH, at least the same QoS (Quality of Service) can be expected. According to [14], the maximum power for desired signals is -28 dBm at the antenna, when there is no other signal present. For the undesired signals, there are some masks defined according to some linearity and selectivity patterns that are going to be explained in the next sections. Regarding the UMTS downlink band which is the adjacent band to the DV B-SH band, [5] assures that the total power level will always be below -25 dBm, so it can be considered as an interferer with a maximum power of -28 dBm at the antenna. Taking into account the RF filter, the maximum input level at the reference point is -29.5 dBm. 2.2.4 Noise figure According to [5], a reference receiver for category 3, should have a noise figure of 4.5 dB at the antenna. When a system is preceded by a passive filter whose input thermal noise temperature is T0= 290oK and with an ambient temperature DVB-SH overview and system approach 17 of 290oK, the noise figure of the attenuator is equal to its attenuation. So, applying the well-known Friis equation, the required noise factor for the RF front-end can be calculated with the following equation: F=Ffilter +Ffront−end −1 Gfilter (2.1) where Ffilter and Gfilter are the noise factor and the gain of the filter, and Ffront−end is the front-end noise factor. The filter’s desired specifications are defined in [5]. The passband attenuation of the filter is 1.5 dB and the out of band attenuation is 40 dB. As a result, the noise figure NF specification for the RF front-end is 3 dB, which is a significant challenge. 2.2.5 Sensitivity The sensitivity of a receiver is the minimum detectable signal. The sensitivity of the receiver depends directly on the noise figure and the signal to noise ratio: Pinmin =−174dBm/Hz + 10log(BW) + NF +C N(2.2) where the minimum signal bandwidth is 1.52 MHz, and the noise figure for the RF front-end without filter is 3 dB. The minimum carrier to noise ratio required by the system is -3.9 dB. A 0.5 dB implementation margin has been taken into account according to [5]. The sensitivity of the RF front-end is -112.55 dBm. 2.2.6 Dynamic range The minimum input signal power level has been calculated in the previous section and the maximum total power level is -28 dBm for wanted and unwanted signals at the input of the RF filter and -29.5 at the reference point. Therefore, the dynamic range of the RF front-end can be calculated as: DynamicRange =Pmax −Pmin (2.3) Thus, the dynamic range of the RF front-end is: DynamicRange =−29.5−(−112.55) = 83.05dBm (2.4) 18 2.2.7 Dynamic gain The rail-to-rail voltage of the ADC used is 1 Vpp, which means that the maximum allowed input power to the ADC is: Pmax = 10log V pp 2√22 =−9dBV = 4dBm (2.5) The maximum gain required by the front-end can be obtained by fixing the noise floor of the receiver just above the Nyquist noise of the ADC. In this case, the ADC used has 70 dB of SNR, so: NQ=Pmax −SNR = 4 −70 = −66dBm (2.6) and the maximum gain is calculated as: Gmax =NQ−Pinmin =−66 −(−112.55) = 46.55dB (2.7) To obtain the minimum gain required by the system, the non saturation of the ADC is fixed as a condition. For this reason, the maximum output power of the front-end must be below the maximum input power of the ADC, thus: Gmin =PinmaxADC −Pinmaxfront−end = 4 −(−29.5) −6 = 27.5dB (2.8) where the margin of 6 dB has been added to prevent the saturation of the ADC. Finally, the dynamic gain is calculated as the difference between the maximum and minimum gain values previously calculated: DynamicGain =Gmax −Gmin = 46.55 −27.5 = 19.05dB (2.9) 2.2.8 Linearity The third order input interception point can be calculated by means of the third order inter-modulation products using: IIP3 = IMD3 2+Pin (2.10) DVB-SH overview and system approach 25 of each block and the parameters defining the global specifications of the receiver. Those relationships can be expressed through formulas involving the parameters of the blocks connected in cascade [23]. The cost functions that will be considered in this work are the global noise factor (F) and the amplitude of the third order intercept point (AIP3). In agreement with the common practice, we consider that the RF filter is built into the low noise amplifier (LNA). Thus it becomes the first block. The two cost functions that make possible the constraints distribution are: F=FLNA +FM IX −1 GLNA +FCF −1 GLNAGMIX +FAGC −1 GLNAGMIX GCF +FAAF −1 GLNAGMIX GCF GAGC (2.19) 1 AIP 32=1 AIP 32 LNA +GLNA AIP 32 MIX +GLNAGM IX AIP 32 CF +GLNAGM IX GCF AIP 32 AGC +GLNAGMIX GCF GAGC AIP 32 AAF (2.20) A common mistake in the optimisation of electronic blocks is to find optimal results without constraining them to be feasible. To avoid this, the range of variation of the parameters to optimize each block can be fixed, taking into account the state of the art. To take into account both cost functions, a multi-objectives non-linear optimisation problem has been defined. A genetic algorithm NSGA [20] which is based on the biological evolution theory of natural selection was used to obtain more accurate solutions. From a set of initial solutions, the algorithm selects randomly some of these initial solutions and uses them to produce another set of solutions called new generation. Through the successive generations, the set of solutions evolves towards an optimum that minimizes both cost functions. At each step, the algorithm creates new generation from the current generations by using mainly three types of operations: •The selection for choosing some solutions from the current set, which produce a new set of solutions. •The crossover for combining two current solutions to form new solutions for the next generation. •The mutation for applying random changes to current solutions to form new solutions. 26 A general formulation of a multi-objectives problem is given below:            min f(x) = [f1(x), f2(x), ...fk(x)]; x∈ <n subject to gj(x)≤0; j= 1,2, ...J li≤xi≤ui;i= 1,2, ...n (2.21) where f(x) is a vector of kcost functions, gjare Jconstraints of inferiority (with the use of the principle of duality if necessary), xa vector of nvariables xi,liand uirespectively lower and upper bounds of each variable xi. These variables represent the parameters of each block of the architecture, in terms of gain, noise factor and third order input intercept point. An exhaustive list is given for the chosen architecture: x(1) = GLNA, x(2) = GM IX , x(3) = GCF , x(4) = GAGC , x(5) = GAAF , x(6) = FLNA, x(7) = FM IX , x(8) = FCF , x(9) = FAGC , x(10) = FAAF , x(11) = AIP3LNA, x(12) = AIP3MIX , x(13) = AIP3CF , x(14) = AIP3AGC, x(15) = AIP3AAF . (2.22) Gain(dB) NF(dB) IIP3(dBm) LNA 5 to 10 1 to 4 -22 to 5 Mixer 5 to 20 5.5 to 25 -12 to 24 Channel filter -1.5 1.5 13.42 to 22 AGC 5 to 50 5 to 35 4.38 to 20 AA Filter -1.5 1.5 13.42 to 22 TABLE 2.10: FEASIBLE VALUES For this work, the Matlab Optimization tool (Optimtool) was used for optimizing both cost functions Fand AIP3. In this case, the solutions are suitable for several standards using the same architecture. However, this choice can be expensive, depending on the standard. It is not necessary to have the best performances for all the blocks, because it can cost in terms of area and consumption. So, the designer can optimize only the most sensitive blocks in order to relax the others blocks of the receiver. To limit the set of solutions to only feasible solutions, the achievable DVB-SH overview and system approach 27 range was defined for each block parameter, depending on design experience of the state of the art (see table 2.10). After optimisation, a Pareto front was obtained as is shown in figure 2.7. This means that no single solution is dominated by another. All these solutions optimize both cost functions simultaneously and can be refined or filtered taking into account the reality of each design (e.g., keep only the solutions that have a minimum noise figure for the low noise amplifier and a maximum linearity for the mixer). Figure 2.7: Pareto front of achievable solutions. Table 2.11 shows some practical results obtained with this method. The solutions have been filtered to show the maximum total IP3 and the minimum total noise figure. In this case, the solution for the minimum total noise figure can be used for this standard. However, the solution for the maximum total IP3 cannot be used with this standard due to the total noise figure, but it is possible to filter other solutions. In all the cases obtained with this method, the NF of the low noise amplifier tends to be the lowest possible in order to reduce the constraints of the other blocks. This method is reusable with the newly designed blocks. For example, if there is 28 a new block designed, it is possible to use the parameters of this block as an input requirement for the method. Therefore, it is possible to obtain a new set of feasible solutions improving the results. This step can be repeated sequentially for different blocks with the purpose of always obtaining the best solutions for the other blocks. IIP3T otalmax NFT otalmin NFT otal (dB) 7.60 2.54 IIP3T otal (dBm) 3.83 -2.78 GLNA (dB) 7.57 8.72 GMIX (dB) 3.49 16.50 GCF (dB) -1.5 -1.5 GAGC (dB) 22.44 25.1 GAAF (dB) -1.5 -1.5 NFLNA (dB) 1.25 1.1 NFMIX (dB) 6.77 5.61 NFCF (dB) 1.5 1.5 NFAGC (dB) 15.42 15.55 NFAAF (dB) 1.5 1.5 IIP3LNA (dBm) 4.98 4.78 IIP3MIX (dBm) 18 12.61 IIP3CF (dBm) 19.93 19.72 IIP3AGC (dBm) 18.22 16.46 IIP3AAF (dBm) 21.94 21.8 TABLE 2.11: SPECIFICATIONS OF EACH BLOCK 2.4 Conclusion In this chapter, a brief introduction of the standard was given. After this, a zero-IF front-end architecture was chosen and the specifications for this architecture were obtained with a system analysis. The application of a genetic algorithm optimisation method for an optimal distribution of the parameters for the RF receiver for the given architecture was presented. This method has been applied to the DV B-SH standard, optimizing system constraints such as noise figure and total third order distortion. 3 RF front-ends for a DVB-SH receiver 3.1 Introduction This chapter deals with the design of three RF front-ends for a DV B-SH receiver (2.17-2.20 GHz). A direct conversion to zero-IF front-end architecture has been selected for this work. As was explained in the previous chapter, the simplicity of this architecture, due to the lesser amount of components, causes two important consequences: the reduction of the size and the cost of the receiver. This chapter begins with a description of the used technology. 3.2 Description of the UMC 90 nm technology United Microelectronics Corporation (UMC)[24][25] was founded in 1980 as Taiwan’s first semiconductor company. It is a leading global semiconductor foundry that provides advanced technology and manufacturing services for applications spanning every major sector of the Integrated Circuits industry. UMC has been shipping customer products based on its 90 nm process since March of 2003. Currently, UMC is in volume production for a wide range of 90 nm products from multiple customers. UMC 90 nm technology meets a broad range of market sectors, including wireless RF, baseband, high speed graphics and FPGAs. UMC 90 nm includes multiple transistor options, design flows and tools, Intellectual Property IP solutions, Design For Manufacturability (DFM) resources, fast yield feedback service, and advanced packaging options. UMC 90 nm SoC solution has a flexible technology design platform. There are a variety of process device op- 30 tions optimized for their specific application (see figure 3.1), such as High Speed or Low Leakage transistors. Figure 3.1: Applications of the UMC 90 nm technology (extracted from [25]). Figure 3.2: 90 nm Logic/MS/RF devices (extracted from [25]). The MS/RF (Mixed Signal/Radiofrecuency) devices were used to implement the developed circuits in this research. The MS/RF devices (see figure 3.2) have bipolar transistors, MOSFETs, diodes, resistors, MIM/MOM capacitors, varac- RF front-ends for a DVB-SH receiver 31 Figure 3.3: MS/RF design flow and FDK (extracted from [25]). tors, inductors and transformers. The FDK (Foundry Design Kit) offers 27 different metal options [26]. Each metal option defines the layers of metal to be used. The chosen metal option is Option 13, which uses 9 levels of metal layers and one poly (1P9M). The FDK provides an automatic design environment (see figure 3.3). The methodology provides access to circuit-level design and simulation, circuit layout, and layout verification with accurate RF device models. UMC has an optimum inductor finder (OIF), an optimum capacitor finder (OCF) and an optimum transformer finder (OTF) in the FDK package [27]. These optimum finders give the ability to quickly access a large library of inductors, capacitors and transformers. It also allows the performance optimisation of inductors, capacitors and transformers through just a few simple steps with a user interface. Figure 3.4 shows the EDA supported tools for the design of integrated circuits. In this work, the software and the FDK used were: 32 Figure 3.4: Analogue design methodology (extracted from [25]). •Cadence, Custom IC Design Tools, Virtuoso R Front Back Design Environment 5.10.41 USR5.90.69 [28][29]. •Assura 3.2 [28]. •Mentor Graphics Corporation, Calibre Skill Interface v2008.2 33.26 [30]. •Agilent Technologies, Advanced Design System (ADS) 2009 Update 1 [31]. •UMC 90 nm fcdk B14 PB and fcdk B15 PB [24][25][26][27]. 3.3 Receiver 1 The circuit described in this section is composed of a cascode low noise amplifier (LNA), a single to differential converter and a differential double balanced Gilbert mixer. RF front-ends for a DVB-SH receiver 33 Figure 3.5: Narrow band low noise amplifier. 3.3.1 Circuits analysis 3.3.1.1 Low noise amplifier Figure 3.5 shows the typical schematic of a narrow band low noise amplifier (LNA) [23][32][33][34][35][36][37][38]. The cascode low noise amplifier consists of a common source configuration (M1) followed by a common gate configuration (M2) as output stage. The main difference between the cascode amplifier and the common source amplifier is the bandwidth, being higher in the cascode configuration. Also, the cascode stage is used to improve input-output isolation and reduce the Miller effect. The resonant circuit formed by LLand CLis the load of the cascode stage. This permits a high gain with a low voltage supply. The tank resonant frequency is adjusted to be the frequency of interest (2.17-2.2 GHz). The resonant frequency is given by f≈1 2π√LLCL (3.1) where LLand CLare the inductance and the capacitance of the tank circuit. The inductive source degeneration is used for input matching. It consists of 34 introducing a series inductance (LS) at the source as is shown in figure 3.5. LS changes the real part of the input impedance, and to modify the imaginary part another inductor LGis introduced at the gate as presented in figure 3.5. The input impedance of the amplifier with inductive degeneration is given by ZIN =gm LS Cgs +1 sCgs +s(LG+LS) (3.2) where gm is the transconductance of M1 and Cgs is the gate-source capacitance of M1. To obtain a 50 Ω input impedance, the real part should be equal to 50 Ω, gm Cgs LS=RS= 50Ω (3.3) and the imaginary part should be zero at the frequency of interest (between 2.17-2.2 GHz). 1 sCgs +s(LG+LS) = 0 (3.4) The quality factor of the RLC input circuit of the amplifier is given by Q=p(LS+LG)/Cgs RS (3.5) The noise factor is approximately the same as the common source amplifier due to the noise contribution from the cascode is small. So the input transistor (M1) is the main contributor to the circuit noise and its minimum noise factor is given by [23][32] Fmin ≈1 + Rg RS +γ αw wT2 gmRS(3.6) where γis the excess noise (typically 1-2 for short-channel NMOS devices), αis gm/gd0,gd0is the drain-source conductance at zero VDS,Rgis the gate impedance, RSis the output impedance of the input source, wis the working frequency, wTis the maximum frequency of the technology and gmis the transconductance of M1. A method for simultaneously matching the LNA for power and noise was used [39][40]. It is outlined in the following steps: RF front-ends for a DVB-SH receiver 41 •Inductances have to be placed as close together as possible to minimise the effect of series resistance. •Do not use excessively long paths because they introduce capacitance and resistance parasitics. When it is not possible to avoid long paths the top metals have been used. •Place substrate contacts in all the free space except inside the inductors. It avoids unwanted currents interfering in the performance of the circuit (they are derived to the chip substrate). •In order to decouple the noise coming from the supply, a capacitor has been added between the supply and ground. •Use the common centroid technique. •Try to place the differential circuits as symmetrical as possible. •Use guard rings. •Use dummy structures to reduce the tolerance of the components. •Avoid the use of polisilice. •Use multiple-finger configuration for the transistors. The circuit was designed to be measured on wafer using a Cascade SUMMIT 9000 probe station. The chip area, excluding the test pads, is 0.52mm x 0.28mm (including the test pads, it is 0.79mm x 0.59mm). The circuit was simulated using ADS and CADENCE and the layout verification and parasitic extraction were made with ASSURA and CALIBRE. The results of the simulation and measurements are summarized in table 3.1 and discussed below. 42 Parameters Simulation Measurements RF frequency(GHz) 2.17-2.2 Architecture zero-IF Channel bandwidth(MHz) 8 S11(dB) -14.9 -12 Conversion gain(dB) 16.5 15.5 NF@4MHz(dB) 2.24 - Output P1dB(dBm) 0.3 1.92 VCC (V) 1.2 PDC (mW) 21.7 22 Area(mm x mm) 0.52 x 0.28 TABLE 3.1: RF FRONT-END 1 RESULTS Figure 3.11: Input return loss (S11). As seen in figure 3.11 the receiver has a S11 of -12 dB in the band. The minimum peak of S11 is at 2.4 GHz in simulations, while in measurements it has been shifted to 2.53 GHz due to parasitics not taken into account in simulation. Conversion gain of the receiver is 15.5 dB as shown in figure 3.12. Unfortunately, the noise figure could not be measured due to the lack of measuring equipment. RF front-ends for a DVB-SH receiver 43 Thus, the simulated value is a good indicator of the actual performance. The noise figure simulation results are shown in figure 3.13, the value in the band is less than 2.24 dB (IF=4MHz). Figure 3.12: Conversion gain. Figure 3.13: Noise figure. 44 Figure 3.14: Measured P1dB at 2.185 GHz. The linearity of the receiver was evaluated with the P1dB test. The measurements are plotted in figure 3.14. The test was performed at 2.185 GHz and a P1dB of 1.92 dBm was obtained. 3.4 Receiver 2 The circuit described in this section is composed of a resistive feedback low noise amplifier and a double balanced Gilbert mixer. 3.4.1 Circuits analysis 3.4.1.1 Low noise amplifier Figure 3.15 shows the schematic of a common feedback low noise amplifier [56][57][58][59][60]. The voltage gain of the amplifier is approximately given by AV=RL(1 −gm1RF) RF+RL (3.10) RF front-ends for a DVB-SH receiver 45 where gm1is the transconductance of M1,RFis the feedback resistance and RLis the load resistance. Figure 3.15: Feedback low noise amplifier. The input and output impedances are respectively given by ZIN =RF+RL 1−gm1RL // 1 sCgs1 (3.11) and ZOUT =RL// RS+RF 1−gm1RS (3.12) The noise factor of the amplifier is given by F= 1 + 2 3 1 gm1RS1 RS +RS R2 F+f fT22 3gm1RS+RS RF (3.13) where fTis the cut-off frequency of M1. In this section it is proposed to combine a resistive loaded low noise amplifier, with the conventional resistive shunt-feedback, in order to achieve a low power and low noise for the amplifier. Figure 3.16 shows the proposed topology. As it can be seen, this circuit uses only one inductor reducing the required chip area. The low noise amplifier consists of two stages: the input stage, composed of two 46 transistors (M1and M2) and the inductor (LG), and the output stage, which is the load resistance (RL). Figure 3.16: Feedback cascode low noise amplifier. The input stage is a cascode for a number of reasons. The Miller effect tends to substantially decrease the input impedance, making it difficult to match the input. In addition to mitigating the Miller effect, the use of a cascode improves the LNA’s reverse isolation. It is important in the present application in order to allow suppressing local oscillator feed-through from the mixer back to the LNA’s RF input. Finally, the inclusion of the cascode device M2allows the gain variation through the VG2bias voltage. The final values of the transistors have been chosen for a low noise figure and a high gain as was explained for the cascode low noise amplifier. Through resistive shunt-feedback it is possible to match the input and the output achieving an excellent trade-off between conjugate matching and minimum noise. The first step to doing this is to select the values of RLand RFin order to match the real part of the input and output impedances. The imaginary part of the input impedance is then matched using inductor LG. RF front-ends for a DVB-SH receiver 47 3.4.1.2 Mixer The double balanced Gilbert mixer is used again in this receiver (figure 3.17). The number of probes for measuring the circuit on wafer are limited and for this reason, while Receiver 1 had two Gilbert cells in this case Receiver 2 has only one Gilbert cell. The size of the transistors and the value of the DC currents were optimized, so that they provide the best trade-off between linearity, noise figure, conversion gain, power consumption, and bandwidth for the mixer. Figure 3.17: Double balanced Gilbert mixer. 3.4.2 Experimental results Figures 3.18 and 3.19 show the layout and a photograph of the RF front-end composed of the low noise amplifier and the double balanced Gilbert mixer. For the design of the layout of this circuit the same considerations of Receiver 1 have been taken into account. The chip area, excluding the test pads, is 0.475mm x 0.194mm (including the test pads it is 0.79mm x 0.59mm). The simulation and measurement results are summarized in table 3.2 and discussed below. 48 Figure 3.18: Layout of the DVB-SH Receiver 2. Figure 3.19: Photograph of the DVB-SH Receiver 2. RF front-ends for a DVB-SH receiver 49 Parameters Simulation Measurements RF frequency(GHz) 2.17-2.2 Architecture zero-IF Channel bandwidth(MHz) 8 S11(dB) -17.8 -11.9 Conversion gain(dB) 23.8 24.1 NF@4MHz(dB) 2.4 3 Output P1dB(dBm) -1 -2.2 VCC (V) 1.2 PDC (mW) 10.2 12.4 Area(mm x mm) 0.475 x 0.194 TABLE 3.2: RF FRONT-END 2 RESULTS Figure 3.20 shows the input return loss of the receiver. This receiver has a measured S11 in the band of -11.9 dB. Figure 3.20: Input return loss (S11). Conversion gain and noise figure are shown in figures 3.21 and 3.22 respectively. The receiver has an in band conversion gain of 24.1 dB and the noise figure is less than 3 dB. 50 Figure 3.21: Conversion gain. Figure 3.22: Noise figure. RF front-ends for a DVB-SH receiver 57 Figure 3.28: Layout of the DVB-SH Receiver 3. Figure 3.29: Photograph of the DVB-SH Receiver 3. 58 Parameters Simulation Measurements RF frequency(GHz) 2.17-2.2 Architecture zero-IF Channel bandwidth(MHz) 8 S11(dB) -11.2 -14.3 Conversion gain(dB) 22.7 20.8 NF@4MHz(dB) 14.1 14.5 Output P1dB(dBm) 1.9 -3.9 VCC (V) ±1.2 PDC (mW) 32.5 28.4 Area(mm x mm) 0.26 x 0.13 TABLE 3.3: RF FRONT-END 3 RESULTS Figure 3.30 shows the input return loss of the receiver. This receiver has an in band S11 of -14.3 dB. Figure 3.30: Input return loss (S11). Conversion gain and noise figure are shown in figures 3.31 and 3.32 respectively. The receiver has an in band conversion gain of 20.8 dB and a noise figure of 14.5 dB. RF front-ends for a DVB-SH receiver 59 Figure 3.31: Conversion gain. Figure 3.32: Noise figure. 60 Figure 3.33: Measured P1dB at 2.185 GHz. The linearity of the receiver was evaluated with the P1dB test. The measurements are plotted in figure 3.33. The test was performed at 2.185 GHz, and an output P1dB of -3.9 dBm was obtained. 3.6 Conclusions Three fully integrated RF front-ends for DV B-SH were implemented with the UMC CMOS 90 nm process. The measurement results are summarized in table 3.4. The first receiver (Receiver 1) includes a low noise amplifier, a single to differential converter and a mixer. The low noise amplifier is based on cascode topology combined with a narrow band impedance matching and LC tank load. The single to differential converter generates a pair of differential output signals from a single input, which have balanced amplitude and phase. This converter is followed by a Gilbert cell based quadrature mixer. This combination draws 22 mW from a 1.2 V supply. The measurements show a conversion gain of 15.5 dB, an input return loss (S11) of -12 dB and an output compression point (P1dB) of 1.92 dBm. The simulated noise figure was 2.24 dB. This classical architecture was chosen with the RF front-ends for a DVB-SH receiver 61 objective of guaranteeing that the receiver covered the specifications of the standard of digital TV DV B-SH. The main problem of this topology is the area used and the necessary power consumption. Parameters Receiver 1 Receiver 2 Receiver 3 RF frequency(GHz) 2.17-2.2 Architecture zero-IF Channel BW(MHz) 8 S11(dB) -12 -11.9 -14.3 Conversion gain(dB) 15.5 24.1 20.8 NF@4MHz(dB) 2.24∗3 14.5 Output P1dB(dBm) 1.92 -2.2 -3.9 VCC (V) 1.2 1.2 ±1.2 PDC (mW) 22 12.4 28.4 Area(mm x mm) 0.52 x 0.28 0.475 x 0.194 0.26 x 0.13 Technology UMC 90 nm ∗Simulated TABLE 3.4: RF FRONT-ENDS RESULTS The second receiver (Receiver 2) includes a feedback low noise amplifier and a double balanced mixer. This topology was chosen with the objective of reducing the area and the power consumption. Measurements show a conversion gain of 24.1 dB, a 3 dB noise figure, an input return loss (S11) of -11.9 dB and an output compression point (P1dB) of -2.2 dBm. This combination draws 12.4 mW from a 1.2 V supply. The area was reduced more than 30 % because two inductors were eliminated. The third receiver (Receiver 3) includes a low noise amplifier, a single to differential converter and a mixer. The low noise amplifier and the mixer are based on current conveyors topologies. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of -14.3 dB and an output compression point (P1dB) of -3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply. This novel proposal was used with the objective of reducing the area and the power consumption. However, the power consumption was not reduced because at high frequencies it is necessary to increase the power consumption in order to reduce the noise figure. 62 Figure 3.34: Receivers summary. Figure 3.34 shows that all the receivers have a similar input return loss S11, less than -10 dB. The conversion gains are between 15.5 dB and 24.1 dB, the biggest being for Receiver 2. The lowest noise figure is for Receiver 1, followed by Receiver 2. The output compression point is similar for all of them, Receiver 1 being the best. The lowest power consumption is for Receiver 2, but it only has one Gilbert cell while Receiver 1 has two Gilbert cells. The area of Receiver 3 is considerably smaller than the areas of the other receivers. 4 Package 4.1 Introduction Integrated circuit packaging is the final stage of semiconductor device fabrication, where the semiconductor piece is encased in a supporting case. Integrated circuits need to be packaged for several reasons. A package is a mechanical protection that keeps chip temperature stable and prevents physical damage and corrosion. Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. The package must be chosen according to the application which will be allocated to it. In order to select one of the packages available on the market some factors have to be considered: •Size of the chip. •Necessary pins. •Temperature. •Frequency. •Plastic, ceramic. •Wire-Bonding, flip-chip, tape automatic bonding. •Surface mount, insertion. •Footprint. 64 •Mass production, prototyping. •Cost. At radio frequency, the parasitics generated by the packaging affect the circuit performance [70][71][72][73][74] and for this reason it is very important to analyse the effects of the package on the circuit. In this chapter, the package influence on an RF front-end receiver for DV B-SH (Digital Video Broadcasting, Satellite Services to Hand-held) has been studied. In this work the QFN16 package was selected (see figure 4.1) considering the factors shown above. The 3DElectromagnetic simulator (3D-EM) of Agilent ADS (Advanced Design System) has been used to obtain the QFN16 package model and the bonding model. Figure 4.1: Photograph of the QFN16. The schematic and the layout of the packaged circuit are shown in figures 4.2 and 4.3. As can be seen, it is the Receiver 2 designed in Chapter 3. This circuit was chosen to be packaged for different reasons. On one hand, it has fewer pins than the other receivers, and for this reason the analysis is simpler. On the other hand, this receiver perfectly satisfies the specification of the DV B-SH standard with lower power consumption. However, either one of the receivers could have been used for this study. As was explained in Chapter 3, the RF front-end consists of a resistive feedback low noise amplifier and a double balanced Gilbert mixer. Package 65 Figure 4.2: Schematic of Receiver 2. Figure 4.3: Layout of Receiver 2. 66 4.2 Package modelling The Advanced Design System ADS of Agilent Technologies has three different 3D Electromagnetic simulation technologies: •Finite difference time domain: –3Darbitrary structures. –Full wave electromagnetic EM simulations. –Handles much larger and complex problems. –Time domain EM. –Simulate full size cell phone antennas. –EM simulations per/each port. –GPU based hardware acceleration. •Method of moments: –3DPlanar structures. –Full wave and quasi-static. –Dense and compressed solvers. –Frequency domain. –Multi-port simulation at no additional cost. –High Q. •Finite element method: –3DArbitrary structures. –Full wave EM simulation. –Direct, iterative solvers. –Frequency domain EM. –Multi-port simulation at no additional cost. –High Q. Package 73 to errors with program memory. The time needed for carrying out the simulations was significant but it is less than required for other electromagnetic simulators. In order to obtain the package influence over the RF front-end specifications, these simulation results will be included in the RF receiver simulations in the next section. 4.3 Experimental results After obtaining the package model, the next step was to study its influence on the RF receiver. As is shown in figures 4.12, 4.13 and 4.14, the performance of the circuit is reduced when the package is introduced. Observing figure 4.12 it is possible to see that the conversion gain has decreased more than 2 dB within the working frequency. As seen in figure 4.13 the minimum peak of S11 is at 2.3 GHz before introducing the package, while after introducing the package it has been shifted close to 1.8 GHz. Regarding the noise figure, it has also been negatively affected as is shown in figure 4.14. The noise figure has increased 0.7 dB within the working frequency. Although it is not a large increase, it is significant in this case because the maximum noise figure of the receiver for this standard (DV B-SH) is 3 dB. Figure 4.12: Conversion gain with the package. 74 Figure 4.13: Input return loss (S11) with the package. Figure 4.14: Noise figure with the package. Package 75 Figure 4.15: Input of Receiver 2. To improve the performance of the circuit after introducing the package and the bond-wires, different tests were carried out, for example, modifying bias voltages. The best result was obtained modifying the value of the inductance of the input match network of the receiver. Figure 4.16: Conversion gain with the package after modifying LG. 76 As is shown in figure 4.15, the LNA of the receiver has an inductor (LG) in the input to get an input matching of 50 Ω. The value of the inductor is 6 nH. When the effects of the package and the bond-wires are introduced, an inductance of approximately 2.11 nH is added, and for this reason its input match deteriorates. The solution carried out was reducing the value of the inductor LGby approximately 2.11 nH. In this way, it is possible to get the adequate value of the inductance in the input of the receiver. Figures 4.16, 4.17 and 4.18 show the results obtained after modifying the value of LG. In particular, these figures show the simulation results of the circuit without the model of the package and bond-wires, simulation results of the circuit with the effects of the package and the bond-wires and the simulation results after modifying the value of the inductor LG. Looking at figure 4.16, it can be seen that the conversion gain increases 0.6 dB within the working frequency after modifying the value of LG. Figure 4.17 shows the input match S11. In this case the minimum peak of S11 has been shifted close to 2.1 GHz. In addition, S11 is better adapted than the circuit without the package and the bond-wires. Regarding the noise figure, it is possible to see in figure 4.18 that the noise figure improved when the inductor LGwas modified, in particular the noise figure was reduced 0.24 dB after modifying the value of LG. Figure 4.17: Input return loss (S11) with the package after modifying LG. Package 77 Figure 4.18: Noise figure with the package after modifying LG. 4.4 Conclusions In this chapter the influence of the package and the bonding on an RF front-end for DV B-SH implemented in a CMOS 90 nm process (UMC) has been analysed. The electromagnetic simulator (EMDS) of ADS was used to simulate a QFN16 package model. The influence of the package and the bond-wires on each node was studied. The performance of the circuit was reduced when the package model was included. To improve the performance, the inductance of the LNA input matching network LGwas reduced. As a final conclusion, we consider that this method can be used to model several kinds of packages. 5 Conclusions and Areas for Further Research 5.1 Conclusions The main objective of this research work was to present different alternatives for implementing RF receivers for digital TV based on DV B-SH specifications. To carry out this objective, the main requirements of DV B-SH and some possible commercial implementations were studied. After this, a zero-IF front-end architecture was chosen because it has fewer components than others and it also reduces the power consumption. The RF front-end specifications for this architecture were obtained with a system analysis. The specifications obtained were quite restrictive, specially regarding the noise figure. A multi-objectives optimization method for an optimal distribution of the parameters of each block was presented for the given architecture. This method has been applied to the standard DV B-SH, optimizing system constraints such as the noise figure and total third order distortion. As expected, after applying this method it was corroborated that the noise figure of the low noise amplifier is critical in the design of the RF front-end. After this work, the main objective was carried out. Three fully integrated RF front-ends for DV B-SH were designed, fabricated, and tested with the UMC CMOS 90 nm process: •Receiver 1 includes a low noise amplifier, a single to differential converter and a mixer. The LNA is based on cascode topology combined with a narrow band 80 impedance matching network and an LC tank load. The SDC generates a pair of differential output signals from a single input. This converter is followed by a Gilbert cell based quadrature mixer. •Receiver 2 includes a resistive feedback low noise amplifier and a double balanced mixer (Gilbert cell). •Receiver 3 includes a LNA, a single to differential converter and a mixer. The LNA and the mixer are based on current conveyors topology. Figure 5.1: Receivers summary. Conclusions and Areas for Further Research 81 The first implementation was Receiver 1. This classical architecture was chosen with the objective of guaranteeing that the receiver covered the specifications of the standard of digital TV DV B-SH. The main problem of this topology is the area used and the power consumption. For this reason, for Receiver 2 a feedback topology for the low noise amplifier was chosen, reducing the area and the power consumption. The area was reduced more than 30 % because two inductors were eliminated. Also, in this case, due to the fact that the circuits were going to be measured on wafer, and the number of RF probes was limited, this time only one Gilbert cell was integrated in the circuit. For Receiver 3 a novel proposal was implemented and current conveyors were used for the low noise amplifier and the mixer. This topology was used with the objective of reducing the area and the power consumption. Although, the power consumption of the current conveyors is insignificant at low frequencies, at high frequencies it is necessary to increase the power consumption in order to avoid an incrementation in the noise figure. Parameters Receiver 1 Receiver 2 Receiver 3 RF frequency(GHz) 2.17-2.2 Architecture zero-IF Channel BW(MHz) 8 S11(dB) -12 -11.9 -14.3 Conversion gain(dB) 15.5 24.1 20.8 NF@4MHz(dB) 2.24∗3 14.5 Output P1dB(dBm) 1.92 -2.2 -3.9 VCC (V) 1.2 1.2 ±1.2 PDC (mW) 22 12.4 28.4 Area(mm x mm) 0.52 x 0.28 0.475 x 0.194 0.26 x 0.13 Technology UMC 90 nm ∗Simulated TABLE 5.1: RF FRONT-ENDS RESULTS Figure 5.1 shows that all the receivers have a similar input return loss S11, less than -10 dB. The conversion gains are between 15.5 dB and 24.1 dB, the biggest being for Receiver 2. The lowest noise figure is for Receiver 1, followed by Receiver 82 2. The output compression point is similar for all of them, Receiver 1 being the best. The lowest power consumption is for Receiver 2. The area of Receiver 3 is considerably smaller than the areas of the other receivers. The measurement results are summarized in table 5.1. In addition to the main objective, the influence of the package and bond-wires on Receiver 2 has been studied. This circuit was chosen to be packaged for different reasons. On one hand, it has fewer pins than the other receivers, and for this reason the analysis is simpler. On the other hand, this receiver perfectly satisfies the specification of the DV B-SH standard with the lowest power consumption and low area. However, any one of the receivers could have been used for this study. To do this, all the layers that make up the package were drawn, taking into account the dimensions of the layers, the properties and the connections between the layers. Moreover, the bond-wires were added in order to connect the package with the receiver. Once this was completed, a component was generated with the intention of simulating and obtaining a model. The 3Delectromagnetic simulator (EMDS) of ADS was used to simulate the QFN16 package model. As a result of the fact that the 3D-EM simulator was relatively new, some problems occurred when the substrate was modelled. One of the problems occurred with the placing of some layers of the package, but with the 3Dview and the integrated error log, it was solved without much inconvenience. Another problem was with respect to the simulations; sometimes the simulator was interrupted by convergence errors. It was solved by restarting the simulator. The time needed for carrying out the simulations was significant but it is less than required for other electromagnetic simulators. The influence of the package and the bond-wires on each node was studied. The parasitics obtained in each node were similar due to the fact that the bond-wires had a similar length. The equivalent inductance in some nodes was higher because the bond-wires were longer. The performance of the circuit was reduced when the package model was included. The proposed solution to improve the performance of the circuit was modifying the input matching network. To do this, the inductance LGof the LNA input matching network was reduced. This technique can be used to modelling different kinds of packages in a short time. Resumen en Castellano 89 cada una de las diferentes implementaciones de los receptores para radiofrecuencia desarrollados. En el Cap´ıtulo 4 est´a dedicado al modelado de un encapsulado QFN16 y su influencia sobre uno de los receptores, para ello se utiliza el simulador electromagn´etico 3D-EM de ADS. Finalmente, en el Cap´ıtulo 5 se presentan las principales conclusiones obtenidas del trabajo realizado y las posibles l´ıneas futuras de trabajo. Resumen en Castellano 91 A.2 An´alisis del sistema A.2.1 Objetivos Los principales objetivos de este cap´ıtulo son: llevar a cabo un estudio del est´andar de televisi´on digital DV B-SH, hacer el an´alisis del sistema y obtener las especificaciones de los bloques que componen el receptor de radiofrecuencia. A.2.2 Planteamiento y metodolog´ıa DV B-SH [5][6][7] est´a basado en el est´andar DV B-H.DV B-Hsurge de dos de los productos de consumo m´as vendidos en la historia, televisiones y tel´efonos m´oviles. DV B-Hadapta la televisi´on digital terrestre (DV B-T) a los requisitos particulares de los dispositivos m´oviles. DV B-Hofrece un canal de descarga de alta velocidad que puede ser usado independientemente o como una mejora de las redes de telecomunicaci´on m´oviles [11][12]. DV B-SH incluye mejoras frente a DV B-Hen los algoritmos de correcci´on de errores, en la capa f´ısica y en la capa de enlace. Los requisitos del receptor se extraen a partir de la Gu´ıa de Implementaci´on DV B-SH [5] y del documento EICTA MBRAI [14]. Existen 3 categor´ıas diferentes de terminales DV B-SH: La categor´ıa 1 es para terminales montados en veh´ıculos, categor´ıa 2 para dispositivos port´atiles de televisi´on y categor´ıa 3 para dispositivos de bolsillo con tel´efono m´ovil/m´odem integrado. DV B-SH tiene dos capas f´ısicas que aumentan las posibilidades de configuraci´on del sistema, y da lugar a dos arquitecturas diferentes: SH-Aemplea OFDM para la componente sat´elite y para la terrestre y SH-Bque emplea TDM en la componente sat´elite y OFDM para la componente terrestre. Se ha elegido una categor´ıa 3 para uso en SH-B. Por un lado, los requisitos de los terminales de la categor´ıa 3 son mayores y m´as dif´ıciles de conseguir. Por otro lado, un terminal compatible con la red SH-Bse puede usar en una red SH-A. A.2.2.1 Especificaciones del receptor de radiofrecuencia para DVB-SH La figura A.4 muestra una arquitectura cero-IF que es la utilizada para el receptor. Para obtener las especificaciones de radiofrecuencia se usa el punto de referencia que se muestra, justo despu´es del filtro de radiofrecuencia. Rango de frecuencia 92 Figura A.4: Receptor de referencia. Designaci´on Rango de frecuencia Banda 2 GHz S 1980-2010 MHz(uplink) 2170-2200 MHz(downlink) Banda S S-DARS 2320-2345 MHz(downlink) Banda S 2.5 GHz 2670-2690 MHz(uplink) Banda S 2.5 GHz 2500-2520MHz(downlink) Banda S 2.5 GHz 2520-2670 MHz(downlink) TABLA A.1: FRECUENCIAS SAT´ ELITE ASIGNADAS Debido a su versatilidad el est´andar DV B-SH puede ser implementado en las bandas UHF,LyS. Para la componente sat´elite (ver tabla A.1) se asign´o el espectro de frecuencia que va desde 2170 MHz hasta 2200 MHz [15]. Requisitos C/N El tipo de modulaci´on, la tasa de c´odigos y la capa f´ısica marcan el valor de C/N. En las tablas A.2, A.3 and A.4 se muestran las especificaciones de la C/N dependiendo del canal y de la modulaci´on. La m´ınima relaci´on entre portadora y ruido que requiere el sistema es -3.9 dB. Nivel m´aximo entrada La potencia total media de se˜nales deseadas e indeseadas que puede estar presente en la antena como m´aximo es 15 dBm asumiendo un acoplamiento entre las antenas UMTS yDV B-SH de entre 15 y 18 dB. Si el filtro de radiofrecuencia aten´ua un Resumen en Castellano 93 Canal OFDM-AWGN Canal TDM-AWGN CR QPSK 16QAM QPSK 8PSK 16 PSK 1/5 -3.6 0.7 -3.9 -1.3 0.4 2/9 -3.1 1.3 -3.4 -0.7 1.0 1/4 -2.5 1.9 -2.8 -0.1 1.6 2/7 -1.8 2.8 -2.1 0.7 2.5 1/3 -0.9 3.7 -1.2 1.6 3.4 2/5 0.1 5.0 -0.2 2.7 4.7 1/2 1.4 6.8 1.1 4.4 6.5 2/3 3.5 9.7 3.2 6.9 9.4 TABLA A.2: C/N PARA CANAL AWGN Canal TDM-Rice(K=3dB) Canal TDM-Rayleigh CR QPSK QPSK 1/5 -3.4 -3.2 1/4 -2.2 -2.1 1/3 -0.4 -0.2 1/2 2.2 2.9 TABLA A.3: C/N PARA CANALES RICE Y RAYLEIGH QPSK 16QAM CR-INT 3 km/h 50 km/h CR-INT 3 km/h 50 km/h 1/2-S 6.5 dB 4.5 dB 1/3-S 8.5 dB 6.5 dB 1/2-UL 5.5 dB 4 dB 1/3-UL 7 dB 6 dB 1/3-S 3.5 dB 1.5 dB 1/4-S 6.5 dB 5 dB 1/3-UL 2.5 dB 1 dB 1/4-UL 5 dB 4 dB 1/5-S 5.5 dB 3 dB 1/5-UL 4 dB 3 dB TABLA A.4: C/N PARA CANAL COFDM-TU6 94 m´ınimo de 40 dB las bandas de subida UMTS, la potencia total media m´axima en el punto de referencia es -25 dBm. En [5] no se da ninguna descripci´on respecto a las interferencias dentro de la banda. Para ello, se utiliza el EICTA MBRAI [14] como referencia ya que DV BSH yDV B-Hson est´andares de difusi´on de televisi´on m´ovil. Por esta raz´on, es razonable asumir que la relaci´on de potencia de las se˜nales deseadas e interferentes dentro de la banda son similares. Usando las mismas especificaciones de DV B-H para DV B-SH, es de esperar que se obtenga el mismo QoS (Quality of Service). De acuerdo a [14], en la antena la potencia m´axima de las se˜nales deseadas es -28 dBm cuando no hay otras se˜nales presentes. Para las se˜nales indeseadas, depende de la linealidad y la selectividad lo que se explicar´a m´as adelante. Con respecto a las bandas adyacentes a DV B-SH (bandas de bajada de UMTS), [5] asegura que el nivel de total de potencia estar´a siempre por debajo de -25 dBm. Esta puede estar considerada como una interferencia en la antena con una potencia m´axima de -28 dBm. En el punto de referencia el nivel m´aximo es -29.5 dBm. Figura de ruido De acuerdo a [5], la figura de ruido m´axima de un receptor de categor´ıa 3 en la antena es de 4.5 dB. Para calcular la figura de ruido del receptor en el punto de referencia hay que tener en cuenta el filtro de radiofrecuencia. Teniendo en cuenta que la figura de ruido de un filtro pasivo es su propia atenuaci´on, se obtiene que la figura de ruido se calcula como: F=Ffilter +Ffront−end −1 Gfilter (A.1) donde Ffilter yGfilter son el factor de ruido y la ganancia del filtro, y Ffront−end el factor de ruido del receptor. Las especificaciones del filtro est´an definidas en [5]. El filtro tiene una atenuaci´on paso banda de 1.5 dB y una atenuaci´on fuera de la banda de 40 dB. El receptor en el punto de referencia tiene una figura de ruido de 3 dB, lo que es un gran desaf´ıo. Sensibilidad La sensibilidad de un receptor es la m´ınima se˜nal detectable. La sensibilidad del receptor depende directamente de la figura de ruido y de la relaci´on se˜nal ruido: Pinmin =−174dBm/Hz + 10log(BW) + NF +C Nreg (A.2) Resumen en Castellano 95 donde el m´ınimo ancho de banda de la se˜nal es 1.52 MHz, la figura de ruido del receptor despu´es del filtro es 3 dB. La m´ınima relaci´on portadora ruido requerida para el sistema es -3.9 dB. Se ha tomado un margen de 0.5 dB de acuerdo a [5]. La sensibilidad del cabezal de radiofrecuencia es -112.55 dBm. Rango din´amico El nivel m´ınimo de potencia de la se˜nal de entrada se ha calculado anteriormente. El nivel total de potencia m´aximo es -28 dBm para las se˜nales deseadas e indeseadas a la entrada del filtro de radiofrecuencia y -29.5 dBm en el punto de referencia. El rango din´amico se puede calcular como: RangoDin =Pmax −Pmin =−29.5−(−112.55) (A.3) Por lo tanto, obtenemos un rango din´amico de 83.05 dBm. Ganancia din´amica La tensi´on rail to rail del ADC es 1 Vpp, lo que quiere decir que la m´axima potencia permitida a la entrada del ADC es: Pmax = 10log V pp 2√22 =−9dBV = 4dBm (A.4) Fijando el ruido de suelo por encima del ruido de Nyquist del ADC se puede obtener la ganancia m´axima requerida por el receptor. En este caso, el ADC tiene una SNR de 70 dB, por lo tanto: NQ=Pmax −SNR = 4 −70 = −66dBm (A.5) y la m´axima ganancia se calcula como: Gmax =NQ−Pinmin =−66 −(−112.55) = 46.55dB (A.6) Para obtener la m´ınima ganancia que requiere el sistema se fijo como condici´on que no se sature el ADC. Para ello, la potencia m´axima de salida del receptor debe estar por debajo de la potencia m´axima a la entrada del ADC, por lo tanto: Gmin =PinmaxADC −Pinmaxfront−end = 4 −(−29.5) −6 = 27.5dB (A.7) 96 Figura A.5: IIP3, patr´on L3 MBRAI. se le ha a˜nadido un margen de 6 dB para prevenir la saturaci´on del ADC. Finalmente, la ganancia din´amica se calcula como la diferencia entre la ganancia m´axima y la m´ınima: GananciaDin =Gmax −Gmin = 46.55 −27.5 = 19.05dB (A.8) Linealidad El punto de intercepci´on de tercer orden a la entrada se puede calcular por medio de los productos de intermodulaci´on de tercer orden como: IIP3 = IMD3 2+Pin (A.9) Para poder calcular el IIP3 es necesario saber los valores de IMD3 y Pin. El est´andar DV B-SH no tiene ninguna especificaci´on de estos datos del receptor como en el caso de MBRAI [14]. Por lo tanto, se tienen que hacer nuevamente una serie de suposiciones. Como DV B-SH es un est´andar de TV derivado DV B-H, parece razonable asumir que los niveles de se˜nal en la banda (2170 MHz-2200 MHz) y su relaci´on de potencias van a ser similares a los definidos para DV B-H. MBRAI [14] define tres patrones para la linealidad: L1, L2 y L3. La tabla A.5 muestra los valores de los patrones. L1 y L2 no se van a considerar en este an´alisis, ya que est´an basados en la presencia de PAL anal´ogico y se˜nales digitales en la Resumen en Castellano 97 banda UHF [16]. Patr´on Interferencia canal N+2 Int. canal N+4 Atenuaci´on canal N(dB) L1 DVB-T/H PAL 45 L2 PAL PAL 45 L3 DVB-T/H DVB-T/H 40 TABLA A.5: PATRONES DE LINEALIDAD L3 presenta dos se˜nales interferentes en los canales N+2 y N+4 y la se˜nal deseada en el canal N(ver figura A.5). De acuerdo a [14], la amplitud m´axima en la antena para las se˜nales interferentes es -35 dBm y la relaci´on m´axima de potencia entre las se˜nal deseada y las interferentes es 42 dB. Se puede observar, que como los canales de las interferentes est´an en N+2 y N+4 sus productos de intermodulaci´on caer´an en el canal deseado N. Normalmente se utiliza el ruido de suelo del sistema para establecer el valor m´ınimo de la potencia de los productos de intermodulaci´on, por eso, el valor de potencia de los productos de intermodulaci´on puede ser tan grande como el ruido de suelo. En DV B-SH, el m´ınimo ruido de suelo ocurre cuando BW=1.52 MHz, estableciendo la condici´on m´as restrictiva para el receptor de radiofrecuencia, entonces: PIM3=Pnoisefloor = 10log(KToBW) + NFfront−end (A.10) Esto nos da un PIM3= -109.15 dBm. El IIP3 se puede calcular aplicando (A.9): IIP3 = −36.5−(−109.15) 2−36.5 = −0.175dBm (A.11) Obteni´endose un IIP3 de -0.175 dBm. Selectividad canal adyacente La tabla A.6 muestra los requisitos de selectividad del est´andar DV B-SH. La selectividad del canal adyacente (ACS) de un receptor de DV B-SH debe ser al menos 50 dB para un canal adyacente de 5 MHz y 60 dB para un canal adyacente de 10 MHz [5]. 98 Especificaciones Valor(dB) Selectividad canal adyacente(fuera-banda) 5 MHz 50 10 MHz 60 Selectividad canal adyacente(dentro-banda) n±1 29 n±m 40 TABLA A.6: REQUISITOS DE SELECTIVIDAD PARA DVB-SH Ruido de fase Para calcular el ruido de fase teniendo en cuenta las se˜nales interferentes de fuera del canal se usa la siguiente ecuaci´on: PN=Pdesired −Pinterferer −10log(BW)−C N−3 (A.12) donde Pdesired es la potencia de la se˜nal deseada, Pinterferer es la potencia de la se˜nal interferente, BW es el ancho de banda de la se˜nal interferente, se a˜nadieron 3 dB debidos a la contribuci´on de las 2 bandas y C/N es la relaci´on entre portadora y ruido requerida. Sin embargo, este no es el ´unico problema. Como parte del ruido de fase del oscilador controlado por tensi´on (V CO) est´a presente en el canal deseado, el ruido de fase va a degradar la C/N de la se˜nal deseada debido a la interferencias dentro del canal. La degradaci´on de la SNR debida a la interferencias dentro del canal viene dada por: D(dB) = 11 6ln(10)4πβT Es No (A.13) donde βes el single sided -3 dB line-width de la potencia espectral del ruido de fase, 1/T espacio de las subportadoras y Es/N0es la energ´ıa por s´ımbolo, la cual de acuerdo con [5] se relaciona con la C/N como: Es No≈C N(A.14) Resumen en Castellano 105 Despu´es de la optimizaci´on, se obtiene el frente de Pareto como se muestra en la figura A.7. Lo que significa que ninguna soluci´on est´a dominada por otra. Todas estas soluciones optimizan ambas funciones de trabajo al mismo tiempo y pueden ser refinadas o filtradas teniendo en cuenta la realidad de cada dise˜no (por ejemplo las soluciones para m´ınima figura de ruido del amplificador de bajo ruido o para m´axima linealidad del mezclador). IIP3T otalMax NFT otalMin NFT otal (dB) 7.60 2.54 IIP3T otal (dBm) 3.83 -2.78 GLNA (dB) 7.57 8.72 GMIX (dB) 3.49 16.50 GCF (dB) -1.5 -1.5 GAGC (dB) 22.44 25.1 GAAF (dB) -1.5 -1.5 NFLNA (dB) 1.25 1.1 NFMIX (dB) 6.77 5.61 NFCF (dB) 1.5 1.5 NFAGC (dB) 15.42 15.55 NFAAF (dB) 1.5 1.5 IIP3LNA (dBm) 4.98 4.78 IIP3MIX (dBm) 18 12.61 IIP3CF (dBm) 19.93 19.72 IIP3AGC (dBm) 18.22 16.46 IIP3AAF (dBm) 21.94 21.8 TABLA A.11: ESPECIFICACIONES DE CADA BLOQUE La tabla A.11 muestra algunos resultados pr´acticos obtenidos con este m´etodo. Las soluciones se han filtrado para mostrar el m´aximo IP3 total y la m´ınima figura de ruido total. En este caso concreto, las soluci´on para m´ınima figura de ruido total puede usarse para el est´andar DV B-SH. Sin embargo, la soluci´on para m´aximo IP3 total no puede usarse debido a la figura de ruido total que tiene. Es posible filtrar otras soluciones en funci´on de las necesidades. En todos los casos obtenidos con este m´etodo, la figura de ruido del amplificador 106 de bajo ruido tiende a ser lo m´as baja posible, de esta forma se consiguen reducir las restricciones de los otros bloques. Este es un m´etodo reutilizable, por ejemplo, si hay un bloque dise˜nado es posible utilizar los par´ametros de este bloque como requisito para el m´etodo. De esta forma se obtienen un nuevo grupo de soluciones. Este paso se puede repetir secuencialmente para los diferentes bloques con el prop´osito de obtener siempre las mejores soluciones para el resto de los bloques. A.2.3 Aportaciones originales Como principales aportaciones de este cap´ıtulo cabe destacar el dise˜no de una cadena de recepci´on a nivel de bloques, as´ı como la verificaci´on del sistema y distribuci´on de las especificaciones globales en especificaciones particulares de cada uno de los bloques que constituyen el sistema aplicando un m´etodo de optimizaci´on de multiobjetivos. A.2.4 Conclusiones obtenidas En este cap´ıtulo se ha visto una introducci´on del est´andar DV B-SH. Despu´es de elegir la arquitectura m´as id´onea (cero-IF) se ha hecho el an´alisis del sistema. Para acabar se ha realizado la distribuci´on de las especificaciones globales en las diferentes especificaciones locales de cada uno de los bloques. Para ello, se ha aplicado un m´etodo de optimizaci´on de multi-objetivos. Resumen en Castellano 107 A.3 Cabezales de radiofrecuencia para un receptor de DVB-SH A.3.1 Objetivos El objetivo de este cap´ıtulo es el dise˜no de tres cabezales de radiofrecuencia para un receptor de televisi´on digital DV B-SH (2.17-2.20 GHz). Para ello, se utilizar´a la arquitectura cero-IF que reduce el tama˜no y el coste del receptor debido a que tiene un n´umero menor de componentes como fue explicado anteriormente. El cap´ıtulo comienza con una descripci´on de la tecnolog´ıa propuesta para implementar los circuitos. Figura A.8: Aplicaciones de la tecnolog´ıa UMC 90 nm (extra´ıdo de [25]). A.3.2 Planteamiento y metodolog´ıa A.3.2.1 Descripci´on de la tecnolog´ıa UMC 90 nm United Microelectronics Corporation (UMC)[24][25] se fund´o en 1980 como la primera compa˜n´ıa de semiconductores de Taiwan. Se trata de un l´ıder global en la fundici´on de semiconductores que provee tecnolog´ıa avanzada y servicios industriales para el sector de la industria de los circuitos integrados. Ofrece productos basados en su tecnolog´ıa de 90 nm desde marzo de 2004. La tecnolog´ıa UMC 90 nm abarca un amplia rango del mercado incluyendo radiofrecuencia, banda base, gr´aficos de alta velocidad y FPGAs. Incluye m´ultiples opciones de transistores, flujo de dise˜no y herramientas, IP (Intellectual Property), recursos para el dise˜no para manufacturabilidad (DFM), opciones de encapsulado avanzado. Seg´un la aplicaci´on espec´ıfica se puede elegir entre las distintas opciones de dispositivos (ver figura A.8), como 108 pueden ser transistores de alta velocidad o de bajas p´erdidas. Para la implementaci´on de los circuitos desarrollados se han elegido los dispositivos de se˜nal mixta y radiofrecuencia MS/RF (Mixed Signal/RadioFrequency). Los dispositivos MS/RF (ver figura A.9) incluyen transistores bipolares, MOSFETs, condensadores, diodos, resistencias, bobinas y transformadores. El kit de dise˜no (Foundry design kit,FDK) tiene 27 opciones de metal diferentes [26]. Cada opci´on de metal define las capas de metal que pueden ser usadas. La opci´on elegida es la 13, la cual usa 9 niveles de metales diferentes y un polisilicio (1P9M). Figura A.9: Dispositivos l´ogicos/MS/RF 90 nm (extra´ıdo de [25]). La figura A.10 muestra el flujo de dise˜no. Se trata de una metodolog´ıa que permite simular los esquem´aticos y verificar los layout con precisi´on. Para el caso de las bobinas, condensadores y transformadores incluye optimizadores que permiten acceder r´apidamente a una extensa librer´ıa de bobinas, condensadores y transformadores. Adem´as, permite ajustar los componentes con la interfaz en pocos pasos. La figura A.11 muestra las herramientas EDA (Electronic Design Automation) soportadas por la tecnolog´ıa para el dise˜no de circuitos integrados. El software y los Resumen en Castellano 109 Figura A.10: Flujo de dise˜no y FDK para MS/RF (extra´ıdo de [25]). Figura A.11: Metodolog´ıa dise˜no anal´ogico (extra´ıdo de [25]). 110 FDKs utilizados para este trabajo son: •Cadence,Custom IC Design Tools,V irtuoso R Front Back Design Environment 5.10.41 USR5.90.69 [28][29]. •Assura 3.2 [28]. •Mentor Graphics Corporation,Calibre Skill Interface v2008.2 33.26 [30]. •Agilent Technologies,Advanced Design System (ADS) 2009 Update 1 [31]. •UMC 90 nm fcdk B14 PB and fcdk B15 PB [24][25][26][27]. A.3.2.2 Receptor 1 En esta secci´on se describe el primer receptor compuesto por un amplificador cascodo de bajo ruido, un convertidor de asim´etrico a diferencial y un mezclador doble balanceado basado en la c´elula de Gilbert. Amplificador de Bajo Ruido La figura A.12 muestra el cl´asico amplificador de bajo ruido que se utiliza para banda estrecha [23][32][33][34][35][36][37][38]. El amplificador cascodo de bajo ruido consta de un amplificador en configuraci´on fuente com´un (M1) seguido de un puerta com´un (M2) como etapa de salida. La principal diferencia de un amplificador cascodo frente a un fuente com´un es el ancho de banda, siendo mayor en el cascodo. Adem´as, la configuraci´on cascodo mejora el aislamiento entre la entrada y la salida. La carga de la etapa cascodo es un circuito resonante formado por LLyCL. Con esta carga se consigue una ganancia alta usando una baja tensi´on de alimentaci´on. La frecuencia del tanque resonante se ajusta a la frecuencia de inter´es (2.17-2.2 GHz). La frecuencia de resonancia viene dada por f≈1 2π√LLCL (A.22) donde LLyCLson la inductancia y la capacidad del circuito tanque. La degeneraci´on inductiva se utiliza para adaptar la impedancia de entrada. Consiste en introducir una inductancia LSen serie en la fuente del transistor M1 como se muestra en la figura A.12. LScambia la parte real de la impedancia de entrada, y para modificar la parte imaginaria se introduce otra inductancia LGen la puerta del transistor M1como se muestra en la figura A.12. Resumen en Castellano 111 Figura A.12: Amplificador de bajo ruido para banda estrecha. La impedancia de entrada del amplificador con degeneraci´on inductiva viene dada por ZIN =gm LS Cgs +1 sCgs +s(LG+LS) (A.23) donde gm es la transconductancia del transistor M1yCgs es la capacidad puertafuente del transistor M1. Para obtener una impedancia de entrada de 50 Ω la parte real debe ser igual a 50 Ω, gm Cgs LS=RS= 50Ω (A.24) y la parte imaginaria deber´ıa ser cero a la frecuencia de inter´es (entre 2.17-2.2 GHz). 1 sCgs +s(LG+LS) = 0 (A.25) El factor de calidad del circuito RLC a la entrada del amplificador viene dada 112 por Q=p(LS+LG)/Cgs RS (A.26) El factor de ruido es aproximadamente el mismo que el de un amplificador en configuraci´on fuente-com´un debido a que la contribuci´on de ruido del cascodo es peque˜na. El transistor de entrada M1es el principal contribuidor al ruido y su factor de ruido m´ınimo viene dado por [23][32] Fmin ≈1 + Rg RS +γ αw wT2 gmRS(A.27) donde γes el exceso de ruido (entre 1-2 para dispositivos NMOS de canal corto), αes gm/gd0,gd0es la conductancia drenador-fuente para una VDS de cero, Rges la impedancia de la puerta, RSes la impedancia de salida de la fuente a la entrada, w es la frecuencia de trabajo, wTes la frecuencia m´axima de la tecnolog´ıa y gmes la transconductancia de M1. Para dise˜nar el circuito se ha usado un m´etodo de adaptaci´on conjunta para m´ınimo ruido y m´axima transferencia de potencia [39][40]. Este m´etodo consta de los siguientes pasos: 1. Encontrar la densidad de corriente del transistor que proporciona la m´ınima NF. 2. Elegir el ancho del transistor (manteniendo la longitud constante) de forma que la parte real de la impedancia optima para m´ınimo ruido sea 50 Ω. La corriente se debe ajustar de forma que se mantenga la densidad de corriente calculada en el paso 1. 3. Insertar la bobina de degeneraci´on de fuente (LS) que haga que la parte real de la impedancia de entrada sea 50 Ω. 4. El ´ultimo paso consiste en insertar una bobina en serie con la puerta del transistor (LG) que haga que la parte imaginaria de la impedancia de entrada se anule. De este modo la impedancia de entrada quedar´a adaptada a 50 Ω. Hay que tener especial atenci´on con los valores de las inductancias LGyLSobtenidos para la m´ınima figura de ruido porque pueden ser no realizables o que ocupen Resumen en Castellano 113 un ´area extremadamente grande. Para solucionarlo se puede optar por modificar la densidad de corriente y as´ı obtener valores de los componentes que se puedan fabricar. El valor del transistor M2se elige teniendo en cuenta tambi´en la impedancia de entrada del siguiente bloque al que va conectado el amplificador de bajo ruido, en este caso al convertidor de asim´etrico a diferencial. Convertidor de asim´etrico a diferencial El convertidor de asim´etrico a diferencial genera a la salida un par de se˜nales diferenciales a partir de una se˜nal de entrada (ver figura A.13). La configuraci´on diferencial es com´unmente utilizada para construir circuitos integrados anal´ogicos porque es menos sensible al ruido y a las interferencias que en los circuitos asim´etricos. Esta t´ecnica es apropiada para la fabricaci´on de circuito integrados con CMOS porque es f´acil aparear los transistores. Figura A.13: Convertidor de asim´etrico a diferencial. La corriente viene dada por ID2−ID3=1 2µnCOX W L(VIN+−VIN−)s4ISS µnCOX W L−(VIN+−VIN−)2(A.28) 114 donde ID2yID3son las corrientes de drenador de M2yM3,µnes la movilidad de los electrones, COX es la capacidad del ´oxido por unidad de ´area, WyLson el ancho y la longitud de los transistores M2yM3yISS es la corriente del transistor M1. La ganancia en tensi´on diferencial en peque˜na se˜nal del circuito en condiciones de equilibrio viene dada por |AV|=rµnCOX W LISSRD(A.29) Debido a las capacidades par´asitas, aparecen una serie de errores entre las fases a la frecuencia de trabajo [41][42][43]. Para poder reducir el error se ha introducido un condensador Ccomo se muestra en la figura A.13. Con este condensador se consiguen reducir los errores en la amplitud y en la fase sin a˜nadirle un consumo de potencia adicional. El tama˜no de los transistores y la corriente de polarizaci´on se tienen que elegir de tal forma que se adapte lo mejor posible la impedancia de entrada del convertidor a la impedancia de salida del amplificador de bajo ruido. Adem´as, junto con la impedancia de carga se tiene que adaptar la impedancia de salida del convertidor a la impedancia de entrada del siguiente bloque, en este caso el mezclador. Todo ello, tratando de conseguir una figura de ruido baja y que la ganancia sea lo mayor posible. Mezclador La topolog´ıa elegida del mezclador es la configuraci´on doble balanceada, conocida como c´elula de Gilbert [44][45][46][47][48][49] (ver figura A.14). Este dise˜no se suele elegir por sus caracter´ısticas de aislamiento, los mezcladores doble balanceados usan la simetr´ıa para cancelar las componentes indeseadas del oscilador local al mismo tiempo que aumentan las componentes deseadas de la mezcla a la salida. Resumen en Castellano 121 del rendimiento actual. La simulaci´on de la figura de ruido se muestra en la figura A.20, el valor en la banda es menor de 2.24 dB (IF=4MHz). Figura A.20: Figura de ruido. Figura A.21: Medida del P1dB a 2.185 GHz. 122 Para evaluar la linealidad del receptor se ha utilizado el test del P1dB. Las medidas obtenidas se presentan en la figura A.21. El test se realiz´o a 2.185 GHz y se obtuvo un P1dB de 1.92 dBm. A.3.2.3 Receptor 2 El circuito descrito en esta secci´on est´a compuesto de un amplificador de bajo ruido realimentado resistivamente y un mezclador Gilbert doble balanceado. Amplificador de bajo ruido La figura A.22 muestra el esquem´atico de un amplificador de bajo ruido realimentado cl´asico [56][57][58][59][60]. La ganancia en tensi´on del amplificador es aproximadamente AV=RL(1 −gm1RF) RF+RL (A.31) donde gm1es la transconductancia del transistor M1,RFes la resistencia de realimentaci´on y RLes la resistencia de carga. Figura A.22: Amplificador de bajo ruido realimentado. Las impedancias de entrada y salida son respectivamente ZIN =RF+RL 1−gm1RL // 1 sCgs1 (A.32) Resumen en Castellano 123 y ZOUT =RL// RS+RF 1−gm1RS (A.33) El factor de ruido del amplificador realimentado resistivamente viene dado por F= 1 + 2 3 1 gm1RS1 RS +RS R2 F+f fT22 3gm1RS+RS RF (A.34) donde fTes la frecuencia de corte del transistor M1. En esta secci´on se propone combinar un amplificador cascodo con carga resistiva y una realimentaci´on resistiva para obtener mejores resultados en el amplificador. La figura A.23 muestra la topolog´ıa propuesta, como se puede observar el circuito solo tiene una bobina para mejorar la adaptaci´on. Figura A.23: Amplificador de bajo ruido cascodo realimentado. El amplificador de bajo ruido consta se los siguientes elementos: la etapa cascodo formada por los transistores M1yM2, la bobina LG, la resistencia de carga RLy la resistencia de realimentaci´on RF. Se ha utilizado la topolog´ıa cascodo por diferentes razones: mitiga el efecto Miller mejorando la adaptaci´on y el ancho de banda, mejora el aislamiento entre la entrada y la salida del amplificador y adem´as permite variar la ganancia del amplificador a trav´es de la tensi´on de alimentaci´on VG2. 124 A trav´es de la resistencia de realimentaci´on se puede adaptar la entrada y la salida del amplificador obteniendo una m´ınima figura de ruido. El primer paso es seleccionar el valor de RLyRFpara poder adaptar la parte real de las impedancias de entrada y salida. La parte imaginaria de la impedancia de entrada se adapta utilizando la bobina LG. El tama˜no de los transistores se han elegido de forma que se obtenga un compromiso entre una ganancia alta, m´ınima figura de ruido y consumo de potencia reducido. Mezclador La figura A.24 muestra el mezclador Gilbert doble balanceado utilizado en este receptor. El n´umero de puntas que se pueden utilizar a la hora de medir un circuito sobre oblea est´a limitado. Por esta raz´on, en esta ocasi´on a diferencia del mezclador del Receptor 1 se opt´o por utilizar una sola c´elula de Gilbert. Al igual que en el caso del mezclador del Receptor 1, el tama˜no de los transistores y de las corrientes de polarizaci´on se optimizaron de forma que se obtuviera el mejor compromiso entre linealidad, figura de ruido, ganancia y consumo de potencia. Figura A.24: Mezclador Gilbert doble balanceado. Resumen en Castellano 125 Figura A.25: Layout del Receptor 2. Figura A.26: Fotograf´ıa del Receptor 2. 126 Resultados experimentales Las figuras A.25 y A.26 muestran el layout y una fotograf´ıa del cabezal de radiofrecuencia compuesto por un amplificador de bajo ruido realimentado resistivamente y del mezclador Gilbert doble balanceado. A la hora de realizar el layout se han tenido en cuenta las mismas consideraciones que se tuvieron al realizar el layout del Receptor 1. El ´area de chip del receptor excluyendo los pads es 0.475mm x 0.194mm (incluyendo los pads es 0.79mm x 0.59mm). El circuito fue simulado usando ADS yCADENCE y la verificaci´on del layout y la extracci´on de par´asitos fue hecha con ASSURA yCALIBRE. Los resultados de las simulaciones y de las medidas se resumen en la tabla A.13 y son discutidos debajo. Par´ametros Simulaciones Medidas Frecuencia RF(GHz) 2.17-2.2 Arquitectura cero-IF Ancho banda canal(MHz) 8 S11(dB) -17.8 -11.9 Ganancia de conversi´on(dB) 23.8 24.1 NF@4MHz(dB) 2.4 3 P1dBsalida(dBm) -1 -2.2 VDD(V) 1.2 PDC (mW) 10.2 12.4 ´ Area(mm x mm) 0.475 x 0.194 TABLA A.13: RESULTADOS RECEPTOR 2 La figura A.27 muestra que el Receptor 2 tiene un S11 medido dentro de la banda por debajo de -11.9 dB. Al igual que en el caso del Receptor 1 se ha desplazado el pico m´ınimo del S11 a frecuencias mayores debido a los par´asitos que no se tienen en cuenta en las simulaciones. La ganancia de conversi´on y la figura de ruido se muestran respectivamente en las figuras A.28 y A.29. El receptor tiene una ganancia de conversi´on de 24.1 dB en la banda de trabajo y una figura de ruido menor a 3 dB. Para evaluar la linealidad del receptor se ha utilizado el test del P1dB. Las medidas obtenidas se presentan en la figura A.30. El test se realiz´o a 2.185 GHz y se obtuvo a la salida un P1dB de -2.2 dBm. Resumen en Castellano 127 Figura A.27: S11. Figura A.28: Ganancia de conversi´on. 128 Figura A.29: Figura de ruido. Figura A.30: Medida del P1dB a 2.185 GHz. Resumen en Castellano 129 A.3.2.4 Receptor 3 El consumo de potencia es la principal preocupaci´on en el dise˜no de circuitos para dispositivos m´oviles. Para hacer frente a este problema en este trabajo se propone el uso de convertidores de corriente (current conveyors ,CC) para implementar el cabezal de radiofrecuencia. Los convertidores de corriente [61][62][63][64] son elementos activos con tres puertos, X,Yand Z, descritos por:    iy vx iz   =   0a0 1 0 0 0b0   .   vy ix vz   (A.35) donde bcaracteriza el paso de la corriente de XaZ. Para a= 1, se trata de un convertidor de corriente de primera generaci´on (CCI). Para a= 0 es un convertidor de corriente de segunda generaci´on (CCII) y para a=−1 se llama convertidor de corriente de tercera generaci´on (CCIII)[65]. Con a= 0 y b= 1, tienen ganancia unidad y VX=VY(A.36) IZ=IX(A.37) Desde su primera introducci´on por A. Sedra and K. Smith en 1970 [62] los convertidores de corriente han sido usados para construir diferentes bloques de circuitos anal´ogicos para implementar funciones como filtros, giradores, convertidores de impedancias, osciladores y amplificadores [65][66]. Los convertidores de corriente presentan una mayor linealidad, un rango din´amico m´as amplio y un mejor rendimiento en alta frecuencia comparado con sus hom´ologos en modo tensi´on los amplificadores operacionales. Por estas razones, en los ´ultimos a˜nos se est´an utilizando los convertidores de corriente para el dise˜no de elementos para radiofrecuencia [67][68]. En esta secci´on se describe el circuito compuesto por un amplificador de bajo ruido basado en convertidores de corriente con entrada y salida asim´etrica, un convertidor de asim´etrico a diferencial y un mezclador pasivo con dos convertidores de corriente como amplificadores de transimpedancia. 130 Amplificador de bajo ruido La figura A.31 muestra el amplificador de bajo ruido basado en convertidores de corriente propuesto para este receptor. Esta arquitectura est´a compuesta de un amplificador en configuraci´on puerta com´un (M1) seguido de una etapa seguidora (M2). Io1yIo2son las fuentes de corriente que se utilizan para polarizar los transistores [67][68]. La ganancia del amplificador viene dada por G(s) = VOUT (s) VIN (s)=gm1 gm2+CTs(A.38) donde gm1ygm2son las transconductancias de los transistores M1yM2respectivamente y CTrepresenta la capacidad par´asita total en el nodo de salida. Esta funci´on de transferencia presenta en un polo dominante que determina el ancho de banda del amplificador y es aproximadamente f3dB =gm2 2πCT (A.39) Figura A.31: Amplificador de bajo ruido basado en convertidores de corriente. El factor de ruido de un amplificador en configuraci´on puerta com´un es aproxi-