Design of radio frequency integrated circuits for ultra wide band communications

! ! ! ! ! ! ! ! "#$%$!&'("')*+! ! &,-./0!12!)34.1!56,78,09:!%0;,/63;,4!(.698.;-! 216!<=;63!>.4,!?304!(1@@80.93;.10-! ! ! ! ! ! ! ! &A!)1B,6;1!&C3D!'6;,/3! %0-;.;8;1!<0.E,6-.;36.1!4,!F.961,=,9;6G0.93!*H=.9343! +3-!I3=@3-!4,!J630!(3036.3K!F3:1!LMNL! D/Dª..........................................................................SECRETARIO/A INSTITUTO UNIVERSITARIO DE MICROELECTRONICA APLICADA DE LA UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA, CERTIFICA, Que el Consejo de Doctores del Departamento en su sesión de fecha..................................tomó el acuerdo de dar el consentimiento para su tramitación, a la tesis doctoral titulada “Design of Radio Frequency Integrated Circuits for Ultra Wide Band Communications” presentada por el doctorando D. Roberto Díaz Ortega y dirigida por los doctores D. Francisco Javier del Pino Suárez, D. Sunil Lalchand Khemchandani y D. Antonio Hernández Ballester. Y para que así conste, y a efectos de lo previsto en el Artº 6 del Reglamento para la elaboración, defensa, tribunal y evaluación de tesis doctorales de la Universidad de Las Palmas de Gran Canaria, firmo la presente en Las Palmas de Gran Canaria, a…....de.............................................de dos mil............ Departamento: Instituto Universitario de Microelectrónica Aplicada Programa de doctorado: Doctorado en Tecnologías de Telecomunicación. Título de la Tesis Design of Radio Frequency Integrated Circuits for Ultra Wide Band Communications Tesis Doctoral presentada por D. Roberto Díaz Ortega Dirigida por el Dr. D. Francisco Javier del Pino Suárez Codirigida por el Dr. D. Sunil Lalchand Khemchandani Codirigida por el Dr. D. Antonio Hernández Ballester El Director, Los Codirectores, El Doctorando, (firma) (firma) (firma) Las Palmas de Gran Canaria, a _____ de_________________ de 20__ “The most incomprehensible thing about our universe is that it can be comprehended.” Albert Einstein. Agradecimientos Quiero comenzar agradeciendo a mis directores, los doctores Javier del Pino, Sunil Lalchand y Antonio Hern´andez que siempre han estado ah´ı ayud´andome a encaminar y sacar adelante este trabajo que presento ahora. Sin lugar a dudas, sin su ayuda los resultados que presento hoy no habr´ıan sido posibles. Tambi´en quisiera darles las gracias a Hugo, Rub´en, Dailos, Jonathan, Enara y Gustavo, que me han acompa˜nado durante estos a˜nos de trabajo, porque de una forma u otra tambi´en est´an presentes en este trabajo. Este trabajo no podr´ıa haberse llevado a cabo sin la colaboraci´on del IUMA que ha puesto a mi alcance todos los medios necesarios para poder hacer los dise˜nos que se presentan en este trabajo as´ı como el instrumental para la medida de los mismos. Por otro lado quiero agradecer tambi´en a la Agencia Canaria de Investigaci´on Innovaci´on y Sociedad de la Informaci´on, que a trav´es del programa de movilidad de personal investigador, me permiti´o llevar a cabo mi estancia en la Universidad Mons, donde me incorpor´e al equipo de trabajo del Dr. Valderrama y el Dr. Dualibe. Quisiera tambi´en agradecer a ellos el trato que me dieron durante los tres meses de estancia como si fuera uno m´as del equipo. Para terminar, quiero agradecer a mis padres y a Gema, que son los que al fin y al cabo me aguantan a diario, pero que gracias a ellos, soy lo que soy y he llegado hasta aqu´ı gracias a su apoyo incondicional. Contents Contents i List of Figures v List of Tables xi 1 Introduction 1 1.1 Introduction................................ 1 1.2 Objectives................................. 3 1.3 Outline of the Research . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Ultra Wide Band Overview and System Approach 5 2.1 Introduction................................ 5 2.2 History of Ultra Wide Band Communications . . . . . . . . . . . . . 5 2.3 ECMA-368 / ISO/IEC 26907 Receiver Specifications . . . . . . . . . 7 2.3.1 Operating Frequency Band . . . . . . . . . . . . . . . . . . . . 7 2.3.2 Receiver Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Receiver System Design . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.1 NoiseFigure............................ 10 2.4.2 Channel Filter and ADC Specifications . . . . . . . . . . . . . 11 2.4.3 ADC and Frontend Gain Specifications . . . . . . . . . . . . . 13 2.4.4 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . 14 2.4.5 Linearity Requirements . . . . . . . . . . . . . . . . . . . . . . 15 iv CONTENTS 2.4.6 Synthesizer Requirements . . . . . . . . . . . . . . . . . . . . 15 2.4.7 Budget Simulations . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Conclusion................................. 19 3 Distributed Amplifiers 21 3.1 Introduction................................ 21 3.2 TheoreticalApproach........................... 21 3.3 AreaOptimization ............................ 25 3.3.1 CompactDesign ......................... 25 3.3.2 Stacked Inductors . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 ExperimentalResults........................... 29 3.5 Conclusions ................................ 34 4 Wide Band Low Noise Amplifiers 37 4.1 Introduction................................ 37 4.2 Wide Band Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . 37 4.2.1 Narrow Band Inductively Degenerated Amplifier . . . . . . . . 37 4.2.2 Wide Band Inductively Degenerated Amplifier . . . . . . . . . 39 4.2.3 Wide Band Low Noise Amplifier Design . . . . . . . . . . . . 41 4.2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 FlatnessImprovement .......................... 47 4.3.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 Wide Band Folded Cascode Amplifier . . . . . . . . . . . . . . . . . . 50 4.4.1 Narrow Band Folded Cascode Amplifier . . . . . . . . . . . . 52 4.4.2 Wide Band Folded Cascode Amplifier Topology . . . . . . . . 54 4.4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 Conclusions ................................ 58 5 Feedback Wide Band Low Noise Amplifiers 59 5.1 Introduction................................ 59 5.2 CircuitAnalysis.............................. 59 5.3 Modified Miniatured 3D Inductor . . . . . . . . . . . . . . . . . . . . 64 5.4 CircuitDesign............................... 66 5.5 ExperimentalResults........................... 68 CONTENTS v 5.6 Conclusions ................................ 72 6 Inductorless Techniques 75 6.1 Introduction................................ 75 6.2 CommonGateLNA ........................... 75 6.2.1 Input Matching and Voltage Gain . . . . . . . . . . . . . . . . 75 6.2.2 Noise of a CG Stage . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.3 Differential Operation of CG Stage . . . . . . . . . . . . . . . 78 6.3 MixerDesign ............................... 78 6.3.1 QuadratureMixers ........................ 78 6.3.2 Mixers with Current Boosting . . . . . . . . . . . . . . . . . . 79 6.4 Inductorless Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5 ExperimentalResults........................... 81 6.5.1 FrontendI............................. 81 6.5.2 FrontendII ............................ 82 6.6 Conclusions ................................ 86 7 Conclusions and Areas for Further Research 89 7.1 Conclusions ................................ 89 7.2 Areas for Further Research . . . . . . . . . . . . . . . . . . . . . . . . 91 A Resumen en Castellano 93 References 147 B Publications 153 C Other Publications 203 vi CONTENTS List of Tables 2.1 Bandgroupallocation........................... 8 2.2 Sensitivity versus data rate. . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Receivernoisefigure............................ 11 2.4 Channel filter and ADC specifications. . . . . . . . . . . . . . . . . . 12 2.5 Minimum receiver gain specifications. . . . . . . . . . . . . . . . . . . 14 2.6 Receiver blocks specifications. . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Budget simulation results. . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 Low noise amplifier specifications. . . . . . . . . . . . . . . . . . . . . 19 3.1 Calculated components values. . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Inductors Geometrical Parameters. . . . . . . . . . . . . . . . . . . . 31 3.3 Sumary of LNA performance and comparison with previously publisheddesigns................................ 32 3.4 Distributed amplifiers specifications. . . . . . . . . . . . . . . . . . . 34 4.1 Comparison with recently published wide band amplifiers. . . . . . . 47 4.2 Comparison between cascode and folded cascode LNA. . . . . . . . . 58 4.3 Wide band amplifiers specifications. . . . . . . . . . . . . . . . . . . . 58 5.1 ComparativeResults............................ 72 5.2 Wide band feedback amplifiers specifications. . . . . . . . . . . . . . . 72 6.1 Frontends performance summary. . . . . . . . . . . . . . . . . . . . . 86 xiv LIST OF TABLES 7.1 Designed circuits specifications. . . . . . . . . . . . . . . . . . . . . . 90 A.1 Dstribuci´on de canales. . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A.2 Sensibilidad para las diferentes tasas de transferencia. . . . . . . . . . 100 A.3 Resultados de simulaci´on del sistema. . . . . . . . . . . . . . . . . . . 102 A.4 Especificaciones del LNA. . . . . . . . . . . . . . . . . . . . . . . . . 105 A.5 Valores de los componentes calculados. . . . . . . . . . . . . . . . . . 109 A.6 Especificaciones de los amplificadores distribuidos. . . . . . . . . . . . 113 A.7 Comparaci´on entre el cascodo convencional y el cascodo doblado. . . 125 A.8 Especificaciones de los amplificadores desarrollados. . . . . . . . . . . 127 A.9 Especificaciones de los amplificadores. . . . . . . . . . . . . . . . . . . 135 A.10 Resumen de especificaciones de los receptores. . . . . . . . . . . . . . 143 A.11 Especificaciones de los circuitos dise˜nados. . . . . . . . . . . . . . . . 145 1 Introduction 1.1 Introduction In the last years the so-called wireless personal area network (WPAN) systems are becoming popular replacing cables and enabling new consumer applications. Such systems are nowadays dominated by standards like Bluetooth and Zigbee, which operate in the 2.4 GHz ISM band. In order to improve the data rate to several hundreds of Mb/s with a low power transmission, it has been proposed Ultra Wide Band (UWB) communications. Since ultra wide band communications has appeared such as a suitable solution for high data rate wireless transmission, a great number of companies have focused their effort to develop commercial solutions based on it. Some examples of these companies could be the following: Alereon [1]: Alereon is a fabless semiconductor company based on Austin (Texas) which develops high-bandwidth, high-performance low-power Certified Wireless USB and WiMedia ultra wide band chipsets. One of their products is the AL5100/AL5301 Worldwide ultra wide band Chipset. The Alereon AL5100 transceiver integrates sensitive analog frontend components including synthesizer VCO/PLL, anti-alias filters, LNAs, PAs, and transmit/receive (T/R) switches it supports a single-ended connection to the antenna eliminating external baluns. When combined with the Alereon AL5301 BBP/MAC, the AL5100 RF transceiver supports all current mandatory WiMedia specifications for worldwide band groups 1, 3, 4, and 6. Wisair [2]: Wisair is a fabless semiconductor company based on Israel which 2 Figure 1.1: Veebeam HD system. provides single-chip ultra wide band and wireless USB solutions for computing, consumer electronics and mobile devices. One of their products is the Wisair WSR601. The Wisair WSR601 is a single-die CMOS chip that implements PHY, MAC and wireless USB subsystem based on ultra wide band communications. The WSR601 chip is suitable for a wide range of applications such as notebooks, PC peripherals, consumer electronic and portable devices. Veebeam: [3] Based in Cambridge (UK), Veebeam Ltd is a technology company that architechs, designs and develop wireless technology products. Veebeam has focused its efforts in wireless device-to-device video stream systems. One of their products is Veebam HD. Veebam HD (Figure 1.1) is a solution which combines of an ultra wide band transmitter and receiver, enabling the possibility to stream video and audio content from a laptop to a HDTV system. The reception architecture of ultra wide band commercial solutions is usually similar to the structure shown in Figure 1.2. The antenna signal is filtered by an external passive pre-select filter to reduce the level of out-of-band interferers. The frontend consists of a wide band low noise amplifier (LNA) and a quadrature mixer that converts the signal down to low or zero-IF. The synthesizer provides the frequency quadrature LO signals. The baseband filter provides both filtering and variable gain. The filtered baseband signal is digitized by the ADC, which is followed by the digital baseband processor. In this architecture one of the most challenging components is the LNA. This Introduction 3 Figure 1.2: Generic receiver architecture. circuit must have a precise amplification over a wide range of frequencies with a wide band input matching and a low noise contribution. Due to these strict requirements, the low noise amplifiers are usually composed by a large numbers of inductors having a high power consumption. In mobile applications the power consumption is directly related to battery life. On the other hand, the area consumption is related to fabrication costs. In order to get commercial solutions, it is fundamental to obtain a low cost implementation with a low power consumption. 1.2 Objectives The aim of this research work is to present different alternatives to implement power and area efficient low noise amplifiers for ultra wide band communications based on ECMA-368 / ISO/IEC 26907 specifications. The results of the present work are integrated in other more ambitious research projects: •SR2 - Short Range Radio, Spanish Ministry of Industry, Tourism and Trade. 2010-2011. •SR2 - Short Range Radio, Spanish Ministry of Industry, Tourism and Trade. 2009-2010. •WITNESS - WIreless Technologies for small area Networks with Embedded and Security & Safety. MEDEA+ from UE - Spanish Ministry of Industry, Tourism and Trade. 2005 - 2007. 4 In order to achieve the objective, the following milestones have been determined and achieved: 1. From the ECMA-368 / ISO/IEC 26907 is important obtain a reference system in order to stablish the low noise amplifier specification. 2. Explore different alternatives to implement low noise amplifiers for ultra wide band in order to optimize the power and area consumption. 3. Explore different inductors structures in order to reduce the area consumption. 4. Explore the inductorless techniques to avoid the use of inductors in order to reduce the area consumption. 1.3 Outline of the Research This work consists of seven chapters, which are briefly outlined in this section. Chapter 1 (the current chapter) introduces the reader to ultra wide band communications, shows some commercial implementations and outlines the research objectives. After getting an insight into the research context, the system design is presented in Chapter 2. In this chapter the main requirements of ECMA-368 / ISO/IEC 26907 are presented. With those requirements a reference system is designed and the low noise amplifier specifications are extracted. Chapter 3 is devoted to the most classical wide band amplifier architecture, the distributed amplifiers. After this first approach and with the objective of solving the distributed amplifiers drawbacks, in Chapter 4 different implementations of wide band low noise amplifier are presented. In order to continue improving the area and power consumption, in Chapter 5 feedback techniques and some inductors structures suited for that topologies are explored. Chapter 6 is devoted to explore inductorless techniques to improve the area saving of low noise amplifiers. Finally some conclusions and areas for further research are presented in Chapter 7. 2 Ultra Wide Band Overview and System Approach 2.1 Introduction As a starting point of this work, this chapter will cover a study about ECMA-368 / ISO/IEC 26907 specification. After a brief summary about the history and the main specifications adopted by the standard, a receiver system analysis will be developed. This process will take into account the restrictions and specifications imposed by the standard. The obtained receiver specifications will be taken as a reference point for the circuits designed in the rest of the work. 2.2 History of Ultra Wide Band Communications The origins of UWB technology has been established around 1962 and it was referred to impulse radio or baseband carrier-free communications. However, the term “ultra wide band” was first used in 1989 in a patent document by U.S. defence department. In 2002, the Federal Communications Commission (FCC), with the inform 0248, allocates an unlicensed radio spectrum from 3.1 GHz to 10.6 GHz. In order to define a device as an UWB device, it must be considered that channels have to occupy a band greater than 20 percent of the centre frequency or a minimum channel bandwidth of 500 MHz. After the first attempt of standardization by the FCC, the MultiBand OFDM Alliance (MBOA), was established in 2003. It is dedicated to promoting the global standard for ubiquitous UWB wireless solutions. The MBOA created a complete 6 Figure 2.1: WiMedia layers stack. specification for a Physical Layer (PHY) and a Media Access Controller layer (MAC). In parallel to the MBOA, in January of 2003 was created the IEEE 802.15.3a task group in order to study the possibility of using the new FCC spectrum specifications in wireless local area networks and personal area networks. Outside the IEEE 802.15.3a, different companies formalized their relationships to provide a legal context. From this formalization, in 2004 the WiMedia Alliance was born to promote wireless connectivity and interoperability among multimedia devices. The objective of WiMedia is developing a common abstraction platform as shown in Figure 2.1, which enable multiple applications to run over one common radio. The WiMedia radio platform is based technically on MB-OFDM specifications. The combination of MB-OFDM and this convergence platform allows the implementation of wireless version of USB, IEEE 1394, DLNA and other IP-based application protocols. On January 2006, after three years of a jammed process, the IEEE 802.15.3a was abandoned without conclusion. At this moment, without the support of the IEEE, the WiMedia Alliance had to seek for a new alternative to standardize UWB communications. After this process of seeking and hard work, in 2007 was approved the first version of standard ECMA-368 / ISO/IEC 26907 that regulate the UWB communications at Physical and Media Access Controller layers. Ultra Wide Band Overview and System Approach 7 2.3 ECMA-368 / ISO/IEC 26907 Receiver Specifications 2.3.1 Operating Frequency Band The physical layer operates in a frequency range from 3.1 to 10.6 GHz. The relationship between the centre frequency (fc) and the channel number (BAND ID number or nb)isgivenbyEquation 2.1. fc(nb)=2904+528·nbMHz where nb=1, ..., 14 (2.1) Figure 2.2: UWB operating bands limitations. This definition provides a unique numbering system for all channels that have a spacing of 528 MHz. As defined in Figure 2.2, six band groups are defined. Band groups 1 to 4 consist of 3 bands each, spanning the band 1 to 12. Band group 5 contains the two bands 13 and 14. Band group 6 contains the bands 9, 10 and 11. The allocation band is summarized in Table 2.1. In spite of this recommendation about the allocation bands, each country can create more restrictive rules about the frequency band use. 8 Band Group Band ID (nb) Lower Frequency (MHz) Center Frequency (MHz) Upper Frequency (MHz) 1 1 3168 3432 3696 23696 3960 4224 34224 4488 4752 2 4 4752 5016 5280 55280 5544 5808 65808 6072 6336 3 7 6336 6600 6864 86864 7128 7392 97392 7656 7920 410 7920 8184 8448 11 8448 8712 8976 12 8976 9240 9504 513 9504 9768 10032 14 10032 10296 10560 6 9 7392 7656 7920 10 7920 8184 8448 11 8448 8712 8976 Table 2.1: Band group allocation. Ultra Wide Band Overview and System Approach 15 ADC input signal level is: -43.8 dBm. On the other hand, for the weak signal and the minimum gain established in 48.81 dB, so in this condition the power level at the ADC input is -32dBm. As a conclusion from the previous results, the AGC is not needed because in the minimum and maximum input power level condition, the ADC input is not saturated. 2.4.5 Linearity Requirements The interference scenario is dominated by IEEE 802.11a. In a typical case, a IEEE 802.11a channel at a distance of 0.2m could reach a power level of -31.9 dBm. This interference should coexist with a desired ECMA-368 / ISO/IEC 26907 signal with a power level of -80.8 dBm. From this interference scenario, the linearity is defined by the following expression: IIP3=Sdesired +3 2·(Sinterference −Sdesired)⇒IIP3≥−8.65 dBm (2.15) where Sdesired is the desired signal power and Sinterference is interference signal power. 2.4.6 Synthesizer Requirements As the radio has to cover the six bands defined in the ECMA-368 / ISO/IEC 26907 and a zero-IF architecture is proposed, the synthesizer should provide the center frequencies of the bands shown in Table 2.1. In the MBOA proposal, frequency hopping between sub-bands occurs once every symbol period of 312.5 ns. This period contains a 60.6 ns suffix, which is followed by a 9.5 ns guard interval. The frequency generator used to drive the switching core of both, the down-conversion mixer in the receive path and up-conversion mixer in the transmit path, needs to switch within this 9.5 ns to accomplish the frequency hopping. The demands on the purity of the generated carriers are also very stringent due to the presence of strong interferer signals. For example, for Mode 1 operation all spurious tones in the 5 GHz range must be below 50 dBc to avoid down-conversion of strong out-of-band Wireless LAN (WLAN) interferers into the wanted bands. For 16 Figure 2.6: System simulations schematic. Component Gain (dB) Noise Figure (dB) IIP3 (dBm) LNA 15 3-20 Mixer 20 12 -9 Baseband filter -3 3 - Baseband amplifier 19 25 -8 Table 2.6: Receiver blocks specifications. the same reason, the spurious tones in the 2 GHz range should be below 45 dBc to allow co-existence with the systems operating in the 2.4 GHz ISM band, such as 802.11 b/g and Bluetooth. Finally, to ensure that the system SNR will not be degraded by more than 0.1 dB due to the LO generation, the VCO phase noise specification is set to 100 dBc/Hz at 1 MHz offset and the overall integrated phase noise should not exceed 3.5 degrees rms [5, 6]. 2.4.7 Budget Simulations In order to obtain the receiver block specifications, the simulation tool ADS has been used. The budget simulation checks the receiver chain performance to verify that the specifications of each block of the receiver allow to the entire reception chain to fulfil the specifications stated in above sections. As starting point, a first assumption for each block parameter has been set, with the help of the state of art and the design group experience. The final value of the specifications have been set using the simulation tool ADS with the budget analysis and a iterative simulation process. Figure 2.6 shows the simulation schematic for the budget analysis. It can be observed how the entire receiver chain follows the Ultra Wide Band Overview and System Approach 17 Receiver parameter Specification Budget simulation Sensitive (dBm) -80.8 -85 Noise Figure (dB) 7.32 7.27 Gain (dB) 48.81 50.9 Maximum input level (dBm) -41 -35 IIP3 (dBm) -8.65 -8.15 Table 2.7: Budget simulation results. Figure 2.7: SNR budget simulation. schematic shown in Figure 2.3. Table 2.6 summarizes the final specifications of each receiver component, obtained from simulations. As it can be observed in Table 2.7, the budget simulation results are compliant with the global receiver requirements. Figure 2.7 shows the SNR variation through the receiver. Obviously, at the receiver input, the SNR is the highest; however as the signal moves through the receiver chain, it is corrupted by noise and in consequence the SNR drops. The difference between the SNR at the input and output of the receiver is the noise figure. In this case, there is a different between input and output of 7.2 dB. Figure 2.8 shows the gain contribution of each block to the entire receiver. As it can be observed, the gain specification is divided equally between the LNA, the mixer and the baseband amplifier. This situation provides a relaxed scenario for circuit designers because if one block does not reach the proposed gain, this situation could be solved increasing the gain in a subsequent block. As it can be observed in Figure 2.9, the noise figure contribution depends mainly 18 Figure 2.8: Gain budget simulation. Figure 2.9: Noise figure budget simulation. on the LNA and Mixer, so the design of those circuits will be fundamental to satisfy the noise figure specifications. Ultra Wide Band Overview and System Approach 19 Figure 2.10: Linearity budget simulation. Finally, Figure 2.10 shows the contribution of each individual block to the receiver linearity. In this case, the main contribution are stablished by the mixer and the baseband amplifier. In this situation the circuit designers will have to center their effort to obtain the maximum linearity in both circuits. 2.5 Conclusion In this chapter, the history and the main characteristics of the ultra wide band standard ECMA-368 / ISO/IEC 26907 have been presented. From these specifications, a receiver system analysis has been done and validated through simulations, obtaining the individual block specifications. Parameter value Gain (dB) 15 Noise Figure (dB) 3 IIP3 (dBm) -20 Power Comsuption (mW) minimum Area Comsuption (mm2)minimum Table 2.8: Low noise amplifier specifications. As a summary, Table 2.8 shows the low noise amplifier specifications. These specifications will be taken as reference to develop low noise amplifiers in the following 20 chapters. The next chapter is devoted to the distributed amplifier, one of the most classical structure to develop wide band low noise amplifiers. 3 Distributed Amplifiers 3.1 Introduction The design of low noise amplifiers for ultra wide band communications has a big challenge to solve, the huge bandwidth. Distributed amplifiers is the first approach to obtain a low noise amplifier for ultra wide band systems. With this structure a high bandwidth with a relative low noise and a moderate gain can be obtained. 3.2 Theoretical Approach The frequency response of a MOS device degrades due to the pole formed by the input/output capacitance of the transistor and the resistance it sees. The MOSFET’s transconductance rapidly falls with frequency and any attempt to increase the transconductance by increasing the size of the device will also increase its input/output capacitance. Thus, while low-frequency gain has been increased, the gain-bandwidth product remains about the same. The distributed amplification (DA) was proposed to overcome this limitation. Distributed amplifier employs a topology in which the gain stages are connected such that their capacitances are separated, yet the output currents still combine in an additive fashion (Figure 3.1). Series inductive elements are used to separate capacitances at the inputs and outputs of adjacent gain stages. The resulting topology, given by the interlaying series inductors and shunt capacitances, forms a lumped-parameter artificial transmission line. The additive nature of the gain 22 Figure 3.1: Distributed amplifier schematic. dictates a relatively low gain; however, the distributed nature of the capacitance allows the amplifier to achieve very wide bandwidths. Distributed amplification overcomes the gain bandwidth limitation absorbing the MOS input/output capacitance as part of the lumped elements of the artificial transmission line, formed with the series inductance that connects adjacent drains and gates. The characteristic impedance (Z0) and cut-offfrequency(fc) of lossless transmission line are given at a first approximation by: Z0=�LTL CTL (3.1) fc=1 π√LTLCTL (3.2) where subindex TL accounts for the drain and gate transmission lines. Since Z0and fcof both the drain and gate lines are the same, their capacitances and inductances should be the same. As the drain-to-bulk capacitance Cdb of a MOSFET is usually less than its gate-to-source capacitance Cgs, a capacitor Cdis added to the drain to make the capacitances equal. Lg=Ld(3.3) Distributed Amplifiers 23 Cgs =Cdb +Cd(3.4) As the amplified signals at each stage travels towards the load, the signal gets attenuated due to non-zero losses associated with the transmission lines. Finite inductors quality factor (Q) are the primary source of losses in the gate line. Losses in the drain line can be attributed to lossy inductors Ldand the drain-to-source resistance (rds). The gain of the DA can be expressed as [7]: A=−gm Z0 2�1−�f fc�2. e−N(Ag+Ad) 2.sinh �NAd−Ag 2� sinh �NAd−Ag 2�(3.5) where Adand Agare the attenuation of the drain and gate lines, gmis the MOSFET transconductance and N is the total number of stages. This equation assumes the following: •Unilateral MOSFET model (ignores Cgd). •Image impedance matched terminations. •Equal gate and drain phase velocities. The optimum number of stages that maximizes the gain is a function of gate and drain line attenuation. Those attenuations are complex functions and depend on the specific MOSFET parameters and also on the operating and cut-offfrequencies. As the signal propagates along the gate line towards the termination, less signal is available for each MOSFET because of attenuation and, as a consequence, the overall gain degrades with further increase in the number of stages. The number of stages for this work is chosen as 4. Knowing the gain, number of stages, and drain-line inductance and capacitance, the required gmcan be found from the low frequency gain using Equation 3.5: gm=2.A N�Cd Ld⇒gm=2.A N.Z0 (3.6) Then, the transistor width-length ratio can be derived from: W L=gm µnCox(Vgs −VT)(3.7) 24 Component Value Lg=Ld1.465 nH Lg/2=Ld/21.15 nH Cd586 fF L (transistor length) 0.425 µm W (transistor width) 4.42 µm Table 3.1: Calculated components values. where •Wtransistor gate width. •Ltransistor gate length. •nelectron mobility. •Cox gate oxide capacitance per unit area. •VTthreshold voltage. •Vgs gate-source voltage. Finally, the device length and width can be found by combining Equation 3.7 with the following expression: W.L =Cg Cox (3.8) Taking into consideration the previous equations and a four stage structure, a DA with a gain of 10 dB and a cut-offfrequency of 11 GHz has been designed. Table 3.1 shows the calculated component values. An important conclusion can be extracted from the previous analysis: this kind of circuits is composed by a considerable number of inductors. As it will be pointed out in the next section, inductors occupy a big amount of layout area and, as a consequence, it is very important to study the effect of inductors and their distribution over the circuit area. Distributed Amplifiers 31 Figure 3.9: Inductors employed in the DA. s(µm) nr(µm) W(µm) Conventional 22.5 100 16 Stacked 22x1.5 40 10 Table 3.2: Inductors Geometrical Parameters. flowing through this line is too high to be supported by stacked inductors. Due to the very high frequency of operation, special attention has been paid to the layout. Thus, enough design accuracy has been achieved by adding accurate high-Q inductor model and optimizing parasitic effects coming from discontinuity and interconnection. The designed DAs utilize a transistor size of 130 µm(equivalent to a 13 gates with 10 µm gate width) and a capacitance Cdof 150 fF. The DA1 circuit occupies an area of 0.74 mm2, which includes the pad frame. In contrast to the conventional design, the compact design DA2 occupies a total area of 0.61 mm2, i.e. 17% a reduction of area. Finally, the Compact design with stacked inductors DA3 occupies a total area of 0.47 mm2which implies a 36% of saving area. After the measurement of several samples, the frequency response is shown in Figure 3.10. The power gain of DA1 is 6 dB with ±0.6 dB flatness from 1 GHz to 5 GHz and a unity gain around 8.6 GHz. The input and output matching are better than -10 dB over the bandwidth. The increase in gain at low frequency is due to the higher impedance of the blocking capacitance at low frequency. All measurements were taken under identical DC bias condition, 3 V on the drain and 0.8 V on the gate. At this bias point the DA consumes 30 mA giving a total power dissipation 32 Ref. Gain (dB) BW (GHz) NF (dB) P1dB (dBm) Area (mm2) ft∗(Tech.) PDC (mW) FOM1FOM2 [7] 6.1 5.5 6.8 8.8 1.12 10.5(0.6µ)83.4 151 132 [17]5.5 8.5 10.85 N/A 2.86 10.5(0.6µ)286 57 - [18]7.3 22 5.2 10 1.6 33.7(0.18µ)52 108 95 [18]10.6 14 4.35 5.3 1.35 33.7 (0.18µ)52 124 106 [19] 6 27 610 1.62 33.7 (0.18µ)68 107 94 [20]485.4 80.84 33.7 (0.18µ)23 208 182 [21]10 11 4.6 N/A 1.44 33.7 (0.18µ)19.6 119 - [21]16 11 4.5 N/A 1.44 33.7 (0.18µ)100 110 - DA1 7 6.5 512.3 0.74 8.13 (0.35µ)90 231 207 DA2 7 6.5 4.5 12.4 0.61 8.13 (0.35µ)90 282 253 DA3 5.5 6.5 611.2 0.47 8.13 (0.35µ)90 364 325 1FOM not including P1dB,2FOM including P1dB Table 3.3: Sumary of LNA performance and comparison with previously published designs. of 90 mW. Finally, Figure 3.10 shows the noise response. The noise figure is under 5 dB from 1 GHz to 6.5 GHz, and it is around 7.5 dB at 8.5 GHz. The frequency response of DA2 is approximately the same of DA1. Regarding to the noise figure, DA2 performance is better than DA1 mainly because the parasitics associated to the connection tracks have been reduced. With respect to DA3, in spite of the stacked inductor performance is worse than the conventional ones, its response is very similar to DA1 and DA2. The noise figure is a little bit higher than that of the conventional design. This is due to the series resistance associated to stacked inductors is larger than that of conventional inductors. Table 3.3 summarizes the performance of the presented amplifiers, with comparison to previously published DAs. To provide an objective method to compare the developed circuits and other similar works, a figure of merit has been used: FOM =P1dB Pnoise 1 PDC fh f∗ t 1 AREA (3.11) This expression includes the DC power consumption (PDC) and output noise power (Pnoise =PthFGain), where Pth =kT is the thermal noise floor given by -174 Distributed Amplifiers 33 Figure 3.10: S21 and noise figure measurements. dBm/Hz at T=290K. In addition, in order to quantify how efficient the available bandwidth of the technology is utilized, a relative measure for bandwidth is introduced through the fh/f∗ tfactor, where fhis the upper LNA corner frequency and f∗is the technology unity current gain bandwidth (ft) around the maximum of the product (gm/ID)ft. Finally, AREA is the area occupied by the circuit and it allows comparing the designs in terms of area consumption. The proposed FOM includes the output 1-dB compression power (P1dB) as a measure for linearity. However, some authors do not include this measurement and, as a consequence, two FOMs have been plotted in Table 3.3: one including the P1dB and the other one without any linearity reference. The DA presented in [7] has an excellent FOM, mainly because it utilizes very efficiently the available bandwidth of the technology. However, the area of this circuit almost doubles our designs and, as a consequence, its FOM is lower than ours. The same authors utilize a fully differential topology in [17]toachievea wider bandwidth than its single-ended counterpart. However both, area and power consumption double and the achieved FOM is low. The works of [18] exhibit both higher gain and bandwidth than our designs. Also the power dissipated is low being the NF similar than our designs. However, our DAs achieve better FOMs mainly because they utilize more efficiently the available area. The low power techniques presented in [20] and [21]usealowPDC to achieve low noise figure and good gain, but they are, however, fundamentally limited by large 34 area. Finally the DA reported in [19]usescoplanarwaveguidestoimplementtherequired inductances. This technique achieves a very high frequency of operation but at the cost of a very large area. Regarding to the presented designs, the best FOM is achieved, as expected, by DA3. This design employs stacked inductors to reduce area. This kind of inductor occupies less chip area than that of planar spiral since the turn is expanded vertically. Usually, top metal is thicker than lower metal layers, and thus the Q-factor of stacked inductors is lower than that of planar spiral inductors. However, as the area occupation is much smaller, substrate losses are smaller, so only little performance degradation of the stacked inductor circuit is achieved over the planar spiral inductor one. This result demonstrates that it is possible to reduce the area with a minimum influence over the circuit response. 3.5 Conclusions Design Gain (dB) BW (GHz) NF (dB) P1dB (dBm) Area (mm2) PDC (mW) DA1 7 6.5 512.3 0.74 90 DA2 7 6.5 4.5 12.4 0.61 90 DA3 5.5 6.5 611.2 0.47 90 Table 3.4: Distributed amplifiers specifications. In this chapter, a first approach to low noise amplifier for ultra wide band communications has been presented. Distributed amplifiers are the most classical way to implement amplifiers with a huge bandwidth and a relative gain. The main drawbacks of this structure are the high power consumption and the elevated area. In order to reduce the area, in this chapter two different techniques have been reported. The first one consists on reallocate the drain and gate line inductors but minimizing the mutual inductance between them. The other technique employs stacked inductors. Although the quality factor of stacked inductor is lower than planar inductor, as the area is much smaller, substrate losses are also smaller, and only little circuit performance degradation is achieved when stacked inductors Distributed Amplifiers 35 are used. Using the above techniques, three fully integrated distributed amplifiers have been designed, fabricated and tested. Table 3.4 shows a summary of their specifications. The next chapter will explore other alternatives to implement low noise amplifiers for ultra wide band communications trying to reduce the power consumption and the occupied area. 36 4 Wide Band Low Noise Amplifiers 4.1 Introduction The distributed amplifiers developed in the previous chapter exhibit a high power consumption and occupy a considerable area. In this chapter, different alternatives of low noise amplifiers will be exposed in order to reduce the power consumption and area. 4.2 Wide Band Low Noise Amplifier 4.2.1 Narrow Band Inductively Degenerated Amplifier In this section, the typical narrow band inductively degenerated amplifier configuration is studied as it is the base of the wide band LNA. Figure 4.1 shows the typical schematic of a narrow band LNA. The input transistor (QCAS1) is in common emitter configuration and it is the mainly contributor to the circuit noise. The noise figure of the LNA depends directly on the emitter area and on the bias of QCAS1.Thecascodestage,composedbyQCAS1and QCAS2, reduces the Miller capacitance, decreasing the effective base collector capacitance (Cbc)of(QCAS2). This makes the amplifier unilateral, i.e., with low S21. This is a requisite of many communication systems to prevent leakage of local oscillator power from the mixer back to the antenna [22]. The cascode also enhances the overall gain by increasing the output impedance. The resonant circuit composed by L and C is the load of the cascode stage. This allows a high gain with a low 38 Figure 4.1: Simplified schematic of the LNA with inductive degeneration. voltage supply. The tank resonant frequency is adjusted to the frequency of interest (ω0). The noise in a transistor is proportional to the transistor base and emitter resistances, rband re, and to the transistor small signal transconductance gm=1/re =IC/VT (VTis the thermal voltage and ICis the collector current). To minimize rb, the transistor must have a large area and to maximize gm,ICmust be high. If the transistor area is increased, the input capacitance will also increase. This will attenuate the input signal and it will raise the NF. As a result the NF will reach a minimum for a particular combination of area and polarization current. The next step in minimizing the noise is matching the LNA input. The antenna output impedance is 50 Ωand through inductive degeneration it is possible to match the input having an excellent trade-offbetween conjugate matching and minimum noise. The inductive degeneration consists on introducing a series inductance (LE) at the emitter as it is shown in Figure 4.1. The inductance value is approximately given by Equation 4.1: LE≈Z0 ωT (4.1) The higher transistor ωT=gm/Ci,thelowerthevalueofLEneeded for matching, and the lower the amount of noise added to the LNA by the series resistance of the Wide Band Low Noise Amplifiers 39 inductor. LEchanges the real part of the input impedance, and to modify the imaginary part another inductor LBis introduced as shown in Figure 4.1. An expression of the noise factor for the LNA with inductive degeneration that takes into account the above discussion is shown in Equation 4.2 [8]: F=1+Rb+Re Z0 +gm 2·Z0·�ω0 ωT�2 (4.2) Alternatively this expression can be expressed as: F=1+rb+re Z0 +1 2·gm·Z0·Q2(4.3) where Q is the quality factor of the input matching network. The noise factor improves with a higher Q because more voltage gain is seen across the input capacitance of the transistor. The input impedance is resistive only in a narrow bandwidth (ω0/Q) around the resonance frequency ω0. To obtain a wide band impedance matching, the Q of the matching circuit should be significantly lowered. This will largely degrade the noise figure which defeats the purpose. As a result, this type of amplifier cannot be used for wide band applications. 4.2.2 Wide Band Inductively Degenerated Amplifier Wide band impedance matching expands the use of an inductively degenerated amplifier, by embedding the input network of the amplifying device in a multisection reactive network so that the overall input reactance is resonated over a broad bandwidth. In this way, a wide band input match is achieved and, at the same time, good noise performance is attained. In the proposed design, shown in Figure 4.2, a fourth-order doubly terminated band-pass filter is used to resonate the reactive part of the input impedance over the whole band. As long as the upper and lower cutofffrequencies (ωUand ωL) of the filter are far from each other, this second-order band-pass filter can be seen as a combination of two filter sections, one in a low-pass configuration and the other one in a high-pass configuration. The high-pass filter section is composed by LBand Cπand its cutofffrequency is given by: high −pass �LB=R ωL ;Cπ=1 ωLR(4.4) 40 On the other hand, the low-pass filter section is composed by LEand CBand its cutofffrequency is given by: low −pass �LE=R ωU ;CB=1 ωUR(4.5) These two circuits provide an input impedance equal to R in the pass-band between ωUand ωL. In order to provide a wide band operation, one would think on replacing the resonant load in the narrow band circuit by a resistor. However, this would lead to gain response falling with the frequency due to the pole generated by the resistor load (RL) and the capacitance of the output node (COUT ). A technique commonly used to increase the bandwidth is to replace the load resistor by a shunt-peaking resistor [8]composedbyLLand RL(see Figure 4.2). The addition of an inductance in series with the load resistor provides an impedance component that increases with frequency (i.e. introduces a zero), which helps offset to decrease the impedance of the load capacitance, leaving a net impedance that remains roughly constant over a broader frequency range than that of the original RC network. RLshould be sufficiently low so that the inductive region of the impedance spans the pass-band. Figure 4.2: Simplified schematic of the LNA with wide band impedance matching and wide band load. Wide Band Low Noise Amplifiers 47 Author BW 3 dB Max. Gain Max. NF IIP3 PDC Technology Year (GHz) (dB) (dB) (dBm) (mW) [24]3.1-10.6 9.18 7.2 7.25 23.5 0.18 µm 2007 [25]2.0-4.6 9.8 5.2 -7 12.6 0.18 µm 2005 [26]3.1-4.8 15 4.9 -2.2 20 0.25 µm 2006 [27]3.0-5.0 12.7 5.02 -9.7 16.4 0.18 µm 2005 [28]3.1-7.5 19.1 3.8 -2.2 32 0.18 µm 2006 [29]3.0-5.0 12 4.5 -20 0.18 µm 2009 This work 1.7-5.3 12.5 5.0 -4 32 0.35 µm 2011 Table 4.1: Comparison with recently published wide band amplifiers. 4.3 Flatness Improvement One of the main drawbacks of the wide band amplifier is the gain flatness. Usually, to extend the gain bandwidth, the load is composed of a shunt-peaking resistor. This technique imposes an upper limit to maximum gain and flatness. To overcome this issue, a modification of the conventional shunt-peaking will be presented. In this case a CMOS technology has been used. 4.3.1 Circuit Description The schematic of the wide band input matched CMOS LNA is shown in Figure 4.11. As in the previous circuit, it consists of a wide band input matching circuit, a gain stage with inductive degeneration (Lgand Ls) and a wide band output load. In order to buffer the output to an external 50 Ωload, an emitter follower (M3) has been included. As the figure shows, the input matching circuit consists of a filter embedded with the input impedance of M1. In this case, a third-order bandpass Chebyshev filter in T configuration was selected. In order to increase the flexibility of the filter, CPis introduced between the gate and source of M1. The gain stage is composed of a cascode stage where the width and polarization current of the transistors are optimized for noise and power consumption. Figure 4.12 shows the typical shunt peaking resistor load used to provide a wide band operation [8]. With this configuration the overall amplifier gain should be flat across the pass-band. The amplifier gain is given by the product of the transistor transconductance (gm) and the magnitude of the impedance of the shunt-peaking 48 Figure 4.11: Wide band LNA simplified schematic with wide band input impedance matching. load, given by: ZL(jω)= RL+ωLL 1−ω2LLCout +jωCoutRL (4.6) where Cout represents the equivalent capacitance at the output node, which includes the transistor output capacitance, the loading by interconnections and subsequent stages, and the parasitic capacitance of the inductor. This expression contains a zero and two complex poles. The extended bandwidth comes from the |Z(jω)| increase due to the poles below the LLCout resonance (ω0=1/LL·Cout) and to the zero (ωz=RL/LL). Unfortunately, this leads to a peak in the frequency response, thus degrading the flatness. As explained above, a possible solution is to keep both resonances out-of-band by using a low value of LL, which in turn implies a low gain. In order to have a large gain, RLshould be chosen sufficiently high to improve the gain at lower frequencies. However, the voltage headroom imposes an upper limit to RLand, as a consequence, to maximum gain and flatness. To overcome this issue, a modification of the conventional shunt-peaking load is proposed. The proposed shunt-peaking load is shown in the Figure 4.12 (b). It is based on a conventional shunt-peaking resistor, decoupled from the cascode stage through a Wide Band Low Noise Amplifiers 49 Figure 4.12: Conventional shunt-peaking load (a) and modified shunt peaking load (b). capacitor CC. To bias the active stage, an inductance LCis placed between VDD and the M2drain. The impedance of the new shunt-peaking load is given by: Z(jω)= jωLCRL�jωLL RL+1 � 1−jω3LCLLCout −ω2LCRLCout +jω(LC+LL)(4.7) The CCvalue has been chosen high; consequently, its effect is neglected and it does not appear in Equation 4.7. With this configuration, RLcan be chosen higher than in a conventional shunt-peaking load, overcoming the voltage headroom limitation. The immediate consequence is that a flatness improvement is achieved. 4.3.2 Experimental Results To demonstrate the practical viability of the proposed structure in CMOS technology, both the proposed topology and the conventional one have been applied to a 3.1 to 4.8 GHz wide band amplifier, based on a 0.35 µm standard CMOS process. Both circuits were optimized with the pads and on-chip spiral inductors analysed with the Momentum electromagnetic simulator [30]. Figure 4.13 shows the photos of two LNAs, one with shunt-peaking load and the other with the modified shunt-peaking load, respectively. As it can be observed, the layouts are very similar with the exception of the LCinductor in the upper right corner. In both designs the chip size, including the probe pads, is 949 x 760 µm. Each amplifier draws 17 mA from a 3.3 V supply. The measured forward gain and input return loss of the amplifiers are shown in 50 Figure 4.13: Photograph of the LNA with the shunt-peaking load and modified shunt-peaking load respectively. Figure 4.14 for frequencies from 2 to 6 GHz. For the proposed shunt-peaked LNA, the power gain is fairly flat at approximately 10 dB for frequencies ranging from 3.1 to 5 GHz. However, the same cannot be said for the conventional case, where a peak is evident. To flatten the insertion gain, the zero pole frequency should be placed as close as possible to the upper edge of the band by lowering LL. However, this entails a gain reduction, as can be seen in Figure 4.15,wherethesimulatedS21 is plotted for different ideal LLinductors. As the inductance decreases, the flatness and bandwidth increase but the gain drops. In both amplifiers, the input return losses remain the same, because both circuits share identical input matching circuits. As a consequence, the noise figure (see Figure 4.16)isalsothesameinbothcases. 4.4 Wide Band Folded Cascode Amplifier In previous sections, two different alternatives to implement wide band amplifiers based on cascode topology have been presented. One of the drawbacks of the cascode amplifier is that this topology suffer from reduced linearity due to the stacking of two transistors, which reduces the available output swing. In order to solve this problem, single transistor topologies are preferred for low voltage operation like the folded cascode LNA presented in this section. Wide Band Low Noise Amplifiers 51 Figure 4.14: Measured S-parameters for LNA with shunt-peaking load and modified shunt-peaking load. Figure 4.15: Gain simulation for different LLinductance using conventional shuntpeaking. 52 Figure 4.16: Measured noise figure for both LNAs. 4.4.1 Narrow Band Folded Cascode Amplifier Figure 4.17 shows the typical schematic of a narrow band folded cascode LNA. The input transistor (Q1) is in common emitter configuration and it is the main contributor to the circuit noise. The folded cascode stage is formed by Q1and Q2, and the resonant circuit formed by LLand the output capacitance (Cout) is the load of the circuit. This folded structure permits a high gain with a low voltage supply. To ensure that the circuit operates as a cascode amplifier, two conditions must be met simultaneously. First, to reduce the Miller effect, the signal gain at the collector of Q1, relative to the input RF signal, should be near unity, and second, the entire RF signal current (gm·|vbe|)generatedbyQ1shouldbefedintotheemitterofQ2. This is done by setting the LCtanks (LT1and LT2) to resonate (i.e., have high impedances) at the frequency of interest. However, due to the finite quality factors of the integrated inductors, the impedances of the LC tanks at resonance are also finite. They are given by the following Equations: Rtank1=(Qtank1+1)·RL1(4.8) Rtank2=(Qtank2+1)·RL2(4.9) Wide Band Low Noise Amplifiers 53 Figure 4.17: Simplified schematic of the LNA with inductive degeneration. where Rtankn and Qtankn are impedances and the quality factors of the LC tanks at resonance, and RLn is the series resistance of the inductors. To avoid signal losses along the signal path, two considerations must be taken into account: to minimize signal divider losses, the LC tank impedance Rtank1must be much larger than the impedance looking into the coupling capacitor CC. Similarly, to avoid signal losses to ground, the LCtank impedance Rtank2must be larger than the impedance looking into the emitter of Q2(re2). The above constraints are summarized as follow: Rtank1>> 1 jωCC +Rtank2||re2(4.10) Rtank2>> re2=1 gm2 (4.11) The main benefit of using a folded cascode topology is its ability to operate at low supply voltages or, in other words, to exhibit a high linearity operation. Linearity is an important parameter that specifies the ability of the circuit to handle large signals. The linearity is typically measured in terms of the input referred third-order intercept point (IIP3). The IIP3 of the amplifier is equal to the IIP3 of the degenerated transistor multiplied by 2 because of the potential divider at the input across the source impedance Z0. Neglecting the effect of the non linearity of 54 Figure 4.18: Simplified schematic of the LNA with wide band impedance matching. the transistor parasitic capacitor, the amplifier IIP3 is given by [8]: VIIP3=4·�2·VT·�1+�ICωLE VT�2�3 4 (4.12) This means that, unlike the noise factor, IIP3 gets better with frequency and, to obtain a wide band operation, special care should be taken at the lower end of the band. 4.4.2 Wide Band Folded Cascode Amplifier Topology In the proposed wide band design, shown in Figure 4.18 as in previous circuits a fourth order doubly terminated band-pass filter is used to resonate the active part of the input impedance over the whole band. The typical cascode has been divided in two different branches. The LT1and LT2has been added in order to bias the collector of Q1and the emitter of Q2respectively. On the other hand, the capacitor CChas been added in order to decouple the signal between the two branches. The output load is formed with a shunt-peaking as in previous designs. Wide Band Low Noise Amplifiers 55 Figure 4.19: (a) Cascode LNA and (b) folded cascode photograph. 4.4.3 Experimental Results To verify the functionality of the proposed low-voltage topology, a comparison is made between two UWB LNAs: (a) the conventional cascode topology developed in section 4.2.3 and (b) the folded topology. The circuit was fabricated in the same 0.35 µm BiCMOS process than the conventional cascode amplifier. The die photographs of those circuits are shown in Figure 4.19. As it can be seen, thanks to the use of MLS inductors for LT1and LT2, the total chip size of both circuits is the same (665 x665µm). For our comparison, we have ensured that both designs were similar except for the use of the capacitively coupled resonating element in the low-voltage topology; i.e., the same transistor geometries and the same biasing conditions were used in both designs. Figures 4.20 –4.23 show the measurements of both LNAs. Note that the measurements include the probe pads and buffer. This worsens the performance comparing with the typical applications. In most of the wireless transceivers, the following stage of the LNA is a mixer which is a capacitive load rather than a 50 Ωload. Figure 4.20 shows the S21 and S11 measurements of both LNAs. As expected, the response of the two designs is approximately the same. As shown in Figure 4.21, the folded cascode shows an enhanced NF with respect to the cascode LNA. This is due to the Q2shot noise filtering associated with the capacitively coupled resonating elements and the fact that the gain at Q1collector is greater than 0 dB because of the RF tanks [31]. The measured IIP3 for the cascode and folded cascode LNAs are shown in Figures 56 Figure 4.20: Measured S21 and S11 versus frequency. Figure 4.21: Measured noise figure versus frequency. Feedback Wide Band Low Noise Amplifiers 63 Figure 5.4: S21 Vs. LBsimulation. bandwidth to higher frequencies, excessive peaking is undesirable for broadband communications systems which require a flat group delay. The quality factor (Q) of this inductor is only of minor importance in this application, due to its low noise contribution in the signal path. Indeed, the lower the quality factor, the higher the series resistance associated to it. This series resistance adds to RFenhancing the circuit noise performance. In this work, we propose two options to implement LB:aconventionalspiral inductor and a modified miniature 3D inductor. A detailed study of the latter will be presented in next section. The inductor Linput is used to achieve a good response the whole frequency range (from 0 GHz to 15 GHz). This coil is in the direct path of the signal but its inductance value is low. Fortunately, as low inductance spirals are achieved with a small number of turns, the quality factor is high and, in consequence, its contribution to the total noise figure will be low. 64 Figure 5.5: Layout and geometric parameter of and on-chip inductor. Figure 5.6: Microphotograph and measured quality factor and inductance of the proposed inductor. 5.3 Modified Miniatured 3D Inductor As explained earlier, the conventional approach to design an integrated inductor on silicon is to layout a simple metallic spiral directly on the substrate (see Figure 5.5). At least two metal levels must be available, because an underpass is required to give access to one of the inductor’s port. The challenge is to choose, for a given technology with fixed metal properties, the optimum combination of the number of turns (n), the metal width (w), the spacing between tracks (s), and the external radio (r) to provide a specific inductance and optimum quality factor at the frequency we are working on. This task is disturbed at high frequencies by the eddy current effects in substrate and metal turns and skin effect in the metal conductor. Large inductance values typically combine with large areas and small QS:an Feedback Wide Band Low Noise Amplifiers 65 increase of the number of turns in the spiral coil or an increase of the coil radii results in an increased magnetic flux and thus a higher inductance value, but also in a proportionally higher series resistance. This can be seen in Figure 5.6,wherethe micro photograph and measured L and Q of a conventional high inductance spiral coil is shown (n=3.5, w=10 µm,s=2µm and r=120 µm). The low-cost employed technology, SiGe 0.35 µm, provides four metal levels. Three of them are similar, with equal thickness and conductivity, and the top level metal is thicker and more conductive. Standard coils are designed using this top metal, which presents a lower series resistance and is far from substrate enough to work at high frequencies. As discussed in section 3.3.2, to save some silicon area, some authors employ stacked inductors. As it can be seen in Figure 3.6,itconsistsofseriesconnected spiral inductors in different metal layers. Since the spirals are identical, the inductance value of each spiral separately will be the same. Spiral inductor segments in different layers, close to each other, have positive mutual inductance between them because current flows to the same direction. So, the total inductance value of the structure will increase due to the strong mutual coupling between them, and it can be achieved high inductance in small area. However, the use of more metal layers makes the capacitive parasitic effects amplify because of the metal-to-metal new capacitance and the increase of the metalto-substrate oxide capacitance. Thus, the stacked inductor suffers from low selfresonance frequency. In an attempt to preserve the advantages of stacked inductor, and at the same time, to increase the resonant frequency and the quality factor, Tang et al. proposed in 2002 the miniature 3D inductors [33]. This structure consists of at least two or more stacked inductors by series connections, and every stacked inductor has only one turn in every metal layer. For example, if there are two stacked inductors with different diameters, and one of them is a one-turn stacked inductor from the metal layer 4 to the metal layer 1, and the other is a one turn stacked inductor from the metal layer 1 to the metal layer 3, then the miniature 3D inductor is formed by connecting two stacked inductors at the metal 1, as Figure 5.7 shows. The proposed structure for inductor LBconsists of two 3D rectangular coils serially connected through the lower metal level, as shown in Figure 5.8.This way, part of the magnetic flux generated by the coils is shared. Consequently, the structure total inductance is greater than the addition of both 3D inductance values 66 Figure 5.7: Miniature 3D Inductor. separately. Figure 5.9(a) shows a micro photograph of the implemented inductor. The structure occupies an area of 98 x 98 µm2, which corresponds to the 25% of the area occupied by a standard inductor with similar inductance response versus frequency. Figure 5.9(b) shows the measured quality factor and inductance value of the proposed inductor. With this structure, in addition to reducing the occupied area a larger inductance is obtained. 5.4 Circuit Design To test the proposed technique, two LNAs, LNA1 and LNA2 were designed using conventional and modified miniature 3D inductor for LB. Except for the structure employed to implement LB, both circuits follow the same design considerations. The LNAs were fabricated using AMS SiGe 0.35 µm BiCMOS technology. It is readily seen from Equation 5.3 that the noise factor of the amplifier is determined by the collector and base shot noise of the first stage transistor Q1,the thermal noise of the shunt feedback resistor, and the thermal noise of Q1’s base and emitter parasitic resistors. The bias current of Q1shall be optimized together with its emitter length for minimum noise. In our final design, the effective emitter area Feedback Wide Band Low Noise Amplifiers 67 Figure 5.8: Modified miniature 3D Inductor. Figure 5.9: Microphotograph and measured quality factor and inductance of the proposed modified 3D inductor. 68 of Q1is 36 µm2.TheemitterfollowerQ2contributes only little to the output noise and an effective emitter area of 1.6 µm has been chosen. The feedback resistor, RF, has a large impact on the noise factor. To reduce its noise contribution, a large value shall be used in conjunction with the consideration for input impedance match. The choice of the feedback resistor determines the operating bandwidth. Low RFincreases the operating bandwidth with the sacrifice of the gain and noise performance. The use of the peaking inductor LBin the feedback path allows alleviating this trade-off, and its inductance value should be chosen as high as possible up to where it can meet the bandwidth requirement without excessive peaking. As explained in previous sections, the quality factor of inductor LBis not relevant. In this case, achieving a high-value inductance in a small area is the major requirement. For that reason a modified miniature 3D inductor could be a better solution for LB.AdifferentsituationisobservedforLinput. This inductor is in series with the input and is used to help matching the input impedance within the entire band. Its quality factor should be as high as possible, since its value affects the overall noise performance. As the required inductance value is low, a conventional spiral inductor can be used in the implementation (1.5 turns). The load, consisting of a poly-silicon resistor RL,isdesignedtoachieveaflat broadband gain over the entire UWB band. According to analysis showed in previous sections, amplifier linearity depends on VCE1selection through the feedback circuit. The value of RBis chosen to maximize IIP3 and is calculated using bias current and supply voltage to bias the device at its low tolerance point to the distortion. 5.5 Experimental Results The die photographs of LNA1 and LNA2 are shown in Figure 5.10.Thechiparea excluding the test pads is 490 x 355 µm2for LNA1 and 330 x 310 µm2for LNA2. Note that the proposed technique achieves a 40% of area reduction, and as we will show later, with minor performance degradation over the same circuit implemented with conventional inductors. The S parameters and the noise figure of both circuits were measured using ground-signal-ground microwave probes. Both circuits operate with a supply voltage of 3.3 V and consume 4 mA. Figures 5.11 and 5.12 show the measured gain and noise figure for 50 Ωsource Feedback Wide Band Low Noise Amplifiers 69 Figure 5.10: Chip photograph of (a) LNA1: with conventional spiral inductor and (b) LNA2: with modified miniature 3D inductor Figure 5.11: Simulated and measured gain. 70 Figure 5.12: Simulated and measured noise figure. and load impedance. Both amplifiers provide a gain which varies from 14 dB to 7 dB in the band between 3.1 GHz and 10.6 GHz, being greater than 1 dB from 0.1 GHz to 15 GHz. The gain response is flat, which indicates that no excessive peaking was employed to obtain the desired bandwidth. The low frequency gain of LNA1 is 15 dB and the 3 dB bandwidth is 5.5 GHz. For LNA2, the gain is similar but the bandwidth is higher (6.7 GHz). This is due to the greater LBinductance value obtained with the 3D inductor (6 nH) compared with the conventional spiral inductor (5 nH). Another positive effect associated to the use of a 3D inductor in the feedback path is an improved noise performance. As shown in Figure 5.12,the measured noise figure of LNA1 is 4.2 dB for low frequencies and rises to 5.6 at 10.6 GHz. The noise figure of LNA2 is between 2.9 dB and 4 dB from 3.1 GHz to 10.6 GHz. The noise figure improves at high frequencies due to the added resistance associated to the low Q 3D inductor. Figure 5.13 shows the measured input and output return loss of both amplifiers. S11 and S22 for LNA2 are lower than -9 dB between 3.1 GHz and 10.6 GHz. The two-tone test for third-order intermodulation distortion (IIP3) is shown in Figure 5.14 for LNA1 and LNA2. The test is performed at 5 GHz. Tone spacing is 100 KHz. LNA1 and LNA2 achieve an IIP3 of -3.4 dBm and -4.4 dBm, respectively. The measurement results of the two wide band LNAs and several previously Feedback Wide Band Low Noise Amplifiers 71 Figure 5.13: Measured input and output return loss (S11 and S22). Figure 5.14: Measured two tone test at 5GHz (a) LNA1 (b) LNA2. 72 Ref. S21 NF 3dB BW IIP3 Pdc Active Tech. (dB) (dB) (GHz) (dBm) (mW) Area (mm) [34]9.3 <92-23 -6.7 91.1 0.18µm CMOS [35]21 <4.5 2-10 >-5.5 30 0.55 0.18µm SiGe [36]9.3 <9.2 2.3-9.2 >-6.7 90.66 0.18µm CMOS [37]8.5 <5.3 1.3-10.7 >84.5 10.18µm CMOS [37]8.2 <5.5 1.3-12.3 >84.5 10.18µm CMOS [18]10.6 <5.4 0.01-14 >10 52 1.35 0.18µm CMOS [38]20 <4.5 3-10 >-11.75 42.5 0.18 0.18µm CMOS [39]22 <3.9 3.1-14.5 >-32.5 13.2 0.49 0.18µm SiGe [40]15.3 <2.98 3.1-10.6 >-8.5 90.87 0.25µm SiGe [41]12 <42-10 >1.9 24 0.25 0.13µm CMOS [42]13 <3.3 2-10 >-7.5 9.6 0.88 0.18µm SiGe [42]11.5 <3.5 2-10 >-7.5 7.2 0.88 0.18µm SiGe [43]11.5 4.7 3.1-10.6 -10 10.57 0.665 0.18µm CMOS Std.ind 14 <5.6 0.1-5.5 >-3.4 13.2 0.1 0.35µm SiGe 3D ind. 14 <40.1-6.7 >-4.4 13.2 0.1 0.35µm SiGe Table 5.1: Comparative Results. published results are listed for comparison in Table 5.1. As shown in Table 5.1, the modified 3D inductor active feedback LNA achieves low noise figure, high gain, and high IIP3 while simultaneously occupying the lowest area yet published in a commercial SiGe BiCMOS process. 5.6 Conclusions Design Gain (dB) BW (GHz) NF (dB) P1dB (dBm) Area (mm2) PDC (mW) Standard Inductor 14 5.5 <4-3.4 0.17 13.2 3D inductor 14 6.7 <4-4.4 0.10 13.2 Table 5.2: Wide band feedback amplifiers specifications. In this chapter other alternative to implement wide band low noise amplifiers has been presented. In this case, a feedback low noise amplifier has been presented. In order to reduce the area, a modified 3D inductors have been used. Inductorless Techniques 79 Figure 6.2: Capacitor cross-coupled CG stage. topology is shown in Figure 6.3. The RF signal is fed into two separate input stages, which drive their respective switch quads. Another possibility is to utilize a single input stage, which drives both switch quads, as it is shown in Figure 6.4. Since the transconductor of the mixer, shown in Figure 6.4,drivesbothswitch quads, the conversion gain is 3 dB lower than the basic Gilbert cell mixer of Figure 6.3. In adittion, complete switching requires larger LO amplitude when quadrature switch quads are driven from a single transconductor. 6.3.2 Mixers with Current Boosting The current boosting method [44], [47], [48]isusedinthemixeranditisshownin Figure 6.5. The optimum bias for the input and switching stages can be optimized separately with current boosting. For proper gain and linearity performance, the input transconductance stage should be biased with rather higher current. However, the performance of the switch quad may require quite low current level for optimum operation. The conversion gain increases for two main reasons: the mixer requires a lower LO swing to switch completely and a larger load resistor value can be used to increase the voltage gain. Alternatively, if the load resistor value is kept unchanged, mixer design for lower supply voltages is alleviated with current boosting, since the voltage drop at the resistive load is reduced. 80 Figure 6.3: Two separate Gilbert mixers driven by quadrature LO signals. Figure 6.4: Quadrature mixer with single input stage. Inductorless Techniques 81 Figure 6.5: Current boosting with constant current source. 6.4 Inductorless Operation Figure 6.6 shows a simplified interface between the LNA and mixer. Biasing and AC coupling have been omitted for clarify. In this Figure, M0represents the LNA transconductor, wich is realized as a CG stage. Further, M1represents the RF transconductor of the mixer. The circuit in Figure 6.6a shows the use of conventional inductive peaking to extend the bandwidth at the LNA output (It is really the LNA-mixer interface bandwidth that is being extended.). This bandwidth extension occurs due to the addition of a zero in the transfer function due to the inductor. A zero can also be introduced by capacitive degeneration as shown in Figure 6.6b[49]. In this circuit, the RCcombination of CSand RSprovides a zero that extends the high frequency response. Effectively, capacitive degeneration provides bandwidth extension properties similar to inductive peaking [50]. 6.5 Experimental Results 6.5.1 Frontend I Figure 6.7 shows an RF frontend composed by a differential common-gate shuntpeaking LNA followed by differential double balanced Gilbert mixer. The layout of 82 Figure 6.6: Simplified circuits for (a) inductive peaking and (b) capacitive peaking. the circuit, named as Frontend I, is shown in Figure 6.8.TheFrontendIchiparea, including the test pads, is 1410.63 x 693.39 µm2. Conversion gain and noise figure simulation results are shown in Figure 6.9 and Figure 6.10 respectively, for a 400 MHz channel located at the center of the band. Frontend I has a conversion gain of 12.1 dB at 5.2 GHz and a noise figure of 11.2 dB (IF=200MHz). The two-tone test for third-order intermodulation distortion (IIP3) of Frontend I is shown in Figure 6.11. The test was performed at 5 GHz and an IIP3 of -5.7 dBm was obtained. 6.5.2 Frontend II Figure 6.12 shows an RF frontend composed by a differential common-gate resistive load LNA followed by differential double balanced Gilbert mixer with capacitive degeneration. The layout of the circuit, named as Frontend II, is shown in Figure 6.13. The Frontend II chip area, including the test pads, is 698.89 x 744.76µm2.Due to the non existence of inductors, the occupied area of this design is 54% lower than Frontend I. Conversion gain and noise figure simulation results are shown in Figure 6.14 and Inductorless Techniques 83 Figure 6.7: Frontend I schematic. Figure 6.8: Frontend I layout. 84 Figure 6.9: Frontend I conversion gain simulations results. Figure 6.10: Frontend I noise figure simulations results. Inductorless Techniques 85 Figure 6.11: Frontend I IIP3 simulations results. Figure 6.12: Frontend II schematic. 86 Figure 6.13: Frontend II layout. Figure 6.15 respectively, for a 400 MHz channel located at the center of the band. Frontend II has a conversion gain of 7.2 dB at 5.2 GHz and a noise figure of 13.71 dB (IF=200MHz). The linearity of the Frontend II was evaluated with a two tone test. The result is plotted in Figure 6.16.TheIIP3is-2.1dBm. 6.6 Conclusions Design Frontend I Frontend II NF (dB) 11.2 13.7 Gain (dB) 12.1 7.2 IIP3 (dBm) -5.6 -2.1 Consumption (mW) 16 14 Area (mm2)0.97 0.52 Table 6.1: Frontends performance summary. In this chapter, an inductorless techniques has been explored. The inductorless wide band amplifier can been achieved if the amplifier works in conjunction with a Inductorless Techniques 87 Figure 6.14: Frontend II gain simulation results. Figure 6.15: Frontend II noise figure simulation results. 88 Figure 6.16: Frontend II IIP3 simulation results. Gilbert Cell mixer because the mixer input is part of the low noise amplifier output matching network. For this reason, in this chapter also a Gilbert Cell mixer with current boosting has been designed. In order to validate the area saving without a significant performance degradation, another wide band low noise amplifier with shunt-peaking followed by a Gilbert cell mixer has been designed. Table 6.1 shows the performance comparative of both frontends. Simulations results shows that the proposed topology with the same bandwidth has better linearity, comparable noise figure and uses less power. The silicon area for the inductorless LNA and I/Q mixers 54% less than the traditional inductor based designs showing area savings and improved portability. Resumen en Castellano 95 Figura A.2: Arquitectura de un receptor gen´erico. anteriormente presentados, tiene una estructura muy similar a la mostrada en la Figura A.2.Enestaarquitectura,lase˜nalprocedentedelaantenaesfiltradapor un filtro externo que se encarga de preseleccionar la banda de inter´es para reducir las interferencias de se˜nales fuera de la banda. Una vez preseleccionada la banda, los amplificadores de bajo ruido (LNA) y los mezcladores de cuadratura se encargan de amplificar la se˜nal y trasladarla a baja frecuencia. El filtrado en banda base se encarga de acondicionar la se˜nal deseada. Finalmente se lleva a cabo una digitalizaci´on de la se˜nal por medio de los conversores anal´ogico-digitales (ADC), de manera que la se˜nal ya puede ser procesada digitalmente. En esta arquitectura, uno de los puntos cr´ıticos del dise˜no es el amplificador de bajo ruido (LNA). Este circuito debe presentar ganancia a lo largo de toda la banda de trabajo con una correcta adaptaci´on de impedancia a la entrada y la m´ınima aportaci´on de ruido posible. Debido a estas restricciones en el dise˜no, normalmente los LNAs est´an compuestos por un gran n´umero de bobinas y tienen un alto consumo de potencia. En las aplicaciones m´oviles, el consumo de potencia est´a directamente relacionado con la duraci´on de la carga de la bater´ıa. Por otro lado, el ´area ocupada por los diferentes circuitos es directamente proporcional al coste del mismo. Con el fin de desarrollar circuitos comerciales competitivos es necesario llevar a cabo una implementaci´on con un m´ınimo consumo de ´area y potencia. A.1.1 Objetivos El principal objetivo de este trabajo de investigaci´on es presentar diferentes 96 alternativas para implementar amplificadores de bajo ruido con un bajo consumo de potencia y un uso eficiente del ´area ocupada. Los resultados de este trabajo de investigaci´on est´an integrados dentro de los siguientes proyectos de investigaci´on: •SR2 - Short Range Radio, Ministerio Espa˜nol de Industria, Turismo y Comercio. 2010-2011. •SR2 - Short Range Radio, Ministerio Espa˜nol de Industria, Turismo y Comercio. 2009-2010. •WITNESS - WIreless Technologies for small area Networks with Embedded and Security & Safety. MEDEA+ de la Uni´on Europea - Ministerio Espa˜nol de Industria, Turismo y Comercio. 2005 - 2007. De cara a alcanzar el objetivo de este trabajo se han planteado los siguientes hitos: 1. Obtener las especificaciones de un sistema de referencia basado en las especificaciones impuestas por el est´andar ECMA-368 / ISO/IEC 26907. 2. Explorar diferentes alternativas para la implementaci´on de amplificadores de bajo ruido para sistemas de ultra banda ancha, prestando especial atenci´on en la optimizaci´on de consumo de ´area y potencia. 3. Explorar diferentes estructuras de inductores integrados con el fin de reducir el consumo de ´area de las misma. 4. Explorar nuevas alternativas de desarrollo de amplificadores de bajo ruido para sistemas de ultra banda ancha que eviten el uso de inductores integrados con el fin de reducir el consumo de ´area. A.1.2 Estructura de la memoria El documento principal de este trabajo de investigaci´on esta compuesto por siete cap´ıtulos distribuidos de la siguiente manera. El Cap´ıtulo 1 introduce al lector a las comunicaciones de ultra banda ancha mostrando una visi´on general del estado actual del mercado. Por otro lado, en este cap´ıtulo se plantean los objetivos del trabajo de investigaci´on. Despu´es de esta peque˜na introducci´on, en el Cap´ıtulo 2 se plantean Resumen en Castellano 97 las principales caracter´ısticas de la especificaci´on ECMA-368 / ISO/IEC 26907. A partir de estas especificaciones se lleva a cabo el dise˜no de un sistema de recepci´on a nivel de bloques. A partir de este sistema de referencia se extraen las especificaciones de partida para los diferentes amplificadores de bajo ruido que se ir´an desarrollando en cap´ıtulos posteriores. El Cap´ıtulo 3 se centra en estudiar una de las estructuras m´as cl´asicas en el desarrollo de amplificadores de ultra banda ancha, los amplificadores distribuidos. Con el fin de solucionar algunos de los principales inconvenientes de los amplificadores distribuidos, en el Cap´ıtulo 4, se presentan diferentes alternativas para la implementaci´on de amplificadores de bajo ruido para ultra banda ancha. Con el fin de continuar llevando a cabo una optimizaci´on de consumo de potencia y´area,enelCap´ıtulo 5 se exploran las t´ecnicas de realimentaci´on aplicadas al dise˜no de amplificadores de bajo ruido. El Cap´ıtulo 6 esta centrado en el desarrollo de amplificadores de bajo ruido evitando el uso de inductores integrados, consiguiendo de esta forma una mejora importante en el consumo de ´area total de los LNAs. Finalmente, en el Cap´ıtulo 7 se presentan las principales conclusiones obtenidas del trabajo realizado. Por otro lado, se presentan las posibles l´ıneas de trabajo para continuar avanzando y explorando en el desarrollo de amplificadores de bajo ruido para comunicaciones de ultra banda ancha. En las siguientes secciones, tal y como regula la Universidad de Las Palmas de Gran Canaria en el Reglamento para la elaboraci´on, tribunal, defensa y evaluaci´on de tesis doctorales en el art´ıculo 2, se presentar´a un resumen de cada uno de los cap´ıtulos del trabajo de investigaci´on donde se recoger´an los siguientes aspectos: Objetivos, Planteamiento y metodolog´ıa, Aportaciones originales y Conclusiones obtenidas. A.2 An´alisis del Sistema A.2.1 Objetivos Como punto de partida de la investigaci´on, los principales objetivos de este cap´ıtulo son: llevar a cabo un estudio de la especificaci´on ECMA-368 / ISO/IEC 26907 y obtener un conjunto de especificaciones de referencia para los amplificadores 98 Figura A.3: Distribuci´on espectral de canales. de bajo ruido que se desarrollar´an en los cap´ıtulos posteriores. A.2.2 Planteamiento y metodolog´ıa A.2.2.1 Especificaciones del sistema Para llevar a cabo el dise˜no del sistema de referencia es necesario conocer las principales especificaciones y requerimientos impuestos por el est´andar ECMA-368 / ISO/IEC 26907. A continuaci´on se enumeran las principales especificaciones a nivel f´ısico. Bandas de frecuencia A nivel f´ısico el rango de frecuencias va desde los 3.1 a los 10.6 GHz, dividiendo el espectro en canales de 528 MHz. Tal y como se define en la Figura A.3,elespectro est´a dividido en 6 grupos de banda. Los grupos del 1 al 4 est´an compuestos por cuatro canales, (canales del 1 al 12). El grupo 5 est´a compuesto por los canales 13 y 14. Finalmente, el grupo 6 contiene los canales 9, 10 y 11. En la Tabla A.1 se muestra la distribuci´on de canales. A pesar de existir esta recomendaci´on de frecuencias en algunos pa´ıses se crean especificaciones mucho m´as restrictivas que proh´ıben la utilizaci´on de canales concretos. Sensibilidad del receptor Otro par´ametro fundamental a la hora de dise˜nar el sistema es conocer la sensi- Resumen en Castellano 99 Grupo de Banda Band ID (nb) Frecuencia Inferior (MHz) Frecuencia Central (MHz) Frecuencia Superior (MHz) 1 1 3168 3432 3696 23696 3960 4224 34224 4488 4752 2 4 4752 5016 5280 55280 5544 5808 65808 6072 6336 3 7 6336 6600 6864 86864 7128 7392 97392 7656 7920 410 7920 8184 8448 11 8448 8712 8976 12 8976 9240 9504 513 9504 9768 10032 14 10032 10296 10560 6 9 7392 7656 7920 10 7920 8184 8448 11 8448 8712 8976 Tabla A.1: Dstribuci´on de canales. 100 Tasa de Transferencia (Mb/s) Sensibilidad (dBm) 53.3 -80.8 80 -78.9 106.6 -77.8 160 -75.9 200 -74.5 320 -72.8 400 -71.5 480 -70.4 Tabla A.2: Sensibilidad para las diferentes tasas de transferencia. Figura A.4: Arquitectura de conversi´on directa. bilidad m´ınima a la que debe trabajar. Seg´un las especificaciones se debe conseguir un Error de Transferencia de Paquetes (PER) inferior al 8 % con una carga ´util por paquete de 1024 octetos. Teniendo en cuenta este error de transferencia se puede obtener la sensibilidad m´ınima para cada una de las velocidades de transferencia soportadas por el est´andar tal y como se muestra en la Tabla A. A.2.2.2 Arquitectura del receptor Debido al gran ancho de banda que presentan los canales se ha optado por llevar a cabo la implementaci´on de un sistema de conversi´on directa. La Figura A.4 muestra un diagrama a nivel de bloques de un receptor de conversi´on directa, en este tipo de receptores la frecuencia del oscilador local es igual a la frecuencia de la se˜nal de entrada, de esta forma al llevar la se˜nal a banda base para proceder a la selecci´on del canal es necesario solamente el uso de un filtro paso bajo. La arquitectura de conversi´on directa presenta algunos inconvenientes. En este tipo de arquitectura la se˜nal de banda base llega hasta 0 Hz. En esta situaci´on la Resumen en Castellano 101 aparici´on de se˜nales continuas pueden corromper e incluso saturar a las etapas de procesado en banda base. Asociado a este fen´omeno est´an relacionados los acoplamientos de la se˜nal del oscilador local a trav´es del puerto de RF. Este acoplamiento resulta en una se˜nal continua que puede contribuir a corromper la se˜nal en banda base. Por otro lado, en este tipo de receptores es necesario llevar a cabo el proceso de mezclado en cuadratura, por lo que cualquier desajuste en los desfasadores pueden provocar un empeoramiento de la calidad de la se˜nal. Otro inconveniente de esta arquitectura es que los arm´onicos de tercer orden pueden aparecen dentro de la se˜nal deseada provocando una degradaci´on de la misma. Finalmente, como la se˜nal se lleva directamente a cero el ruido Flicker asociado a los dispositivos puede influir negativamente en la se˜nal deseada. Apesardeestosinconvenientes,lasimplicidaddelosreceptoresdeconversi´on directa presentan dos importantes ventajas. En este tipo de arquitectura no aparece el problema de la frecuencia imagen porque la se˜nal se lleva a banda base en un ´unico paso. Como resultado de esto no es necesario el uso de filtros externos para el rechazo de imagen. Por otro lado, al llevar a cabo todo el proceso de conversi´on en un ´unico paso, esta arquitectura es mucho m´as sencilla de integrar en un ´unico chip con un consumo de potencia significativamente menor que otras arquitecturas de receptores. Una vez definida la arquitectura del sistema teniendo en cuenta las diferentes especificaciones establecidas por el est´andar ECMA-368 / ISO/IEC 26907, se puede proceder a obtener las especificaciones a nivel de bloques del sistema. En este aspecto inicialmente se obtiene la figura de ruido total a partir de las especificaciones de sensibilidad, ancho de banda del canal y tasa de transferencia en el canal. Una vez definida la figura de ruido total del sistema, se procede a calcular las especificaciones del filtrado de banda base as´ı como las especificaciones de los conversores anal´ogico digital necesarios para transformar la se˜nal al dominio digital para su posterior proceso digital. Con la especificaci´on de los conversores anal´ogico digitales se puede obtener la ganancia general que necesita el sistema. Una vez determinada la ganancia m´axima y m´ınima que debe tener el sistema se determina si es necesario el uso de un control autom´atico de ganancia para asegurar que la ganancia est´a siempre entre los valores m´aximos y m´ınimos determinados. Finalmente, para terminar de llevar a cabo el dise˜no del sistema es necesario 102 Figura A.5: Esquem´atico de simulaci´on del sistema. Par´ametro Especificaci´on Simulaci´on Sensibilidad (dBm) -80.8 -85 Figura de ruido (dB) 7.32 7.27 Ganancia (dB) 48.81 50.9 Maximum input level (dBm) -41 -35 IIP3 (dBm) -8.65 -8.15 Tabla A.3: Resultados de simulaci´on del sistema. determinar los requerimientos de linealidad del mismo, teniendo en cuenta el peor escenario de interferencias al que se puede ver sometido el sistema. Llegados a este punto ya se dispone de todo el sistema dise˜nado y es el momento de validar el dise˜no por medio de simulaciones. Para llevar a cabo estas simulaciones se ha usado el simulador comercial ADS. La simulaci´on realizada al sistema se centra en determinar las especificaciones de cada uno de los bloques del sistema para que en su conjunto se consiga que el sistema completo cumpla las especificaciones calculadas inicialmente. En este proceso de simulaci´on, como punto de partida, a cada bloque se le asigna un conjunto de especificaciones que han sido establecidas teniendo en cuenta la experiencia de trabajo del grupo en circuitos previos y el estado del arte. L´ogicamente, el ajuste final de las especificaciones de cada bloque ser´an determinadas por medio de la simulaci´on. La Figura A.5 muestra el esquem´atico de simulaci´on empleado para determinar las especificaciones de cada uno de los bloques que constituye el sistema. Despu´es de llevar a cabo el proceso de simulaci´on y ajustadas las especificaciones de cada bloque, en la Tabla A.3 se muestra la comparativa entre las especificaciones calculadas inicialmente y las obtenidas finalmente a trav´es de simulaci´on, como Resumen en Castellano 103 Figura A.6: Simulaci´on de la SNR del sistema. Figura A.7: Simulaci´on de ganancia del sistema. puede observarse los valores son muy pr´oximos. La Figura A.6 muestra la variaci´on de la relaci´on se˜nal a ruido (SNR) a lo largo de toda la cadena de recepci´on. L´ogicamente la mayor SNR se encuentra en la entrada del receptor. A medida que la se˜nal va pasando a trav´es del receptor la SNR va disminuyendo porque la se˜nal se va viendo corrompida por el ruido. La diferencia entre los valores de la SNR a la entrada y a la salida constituyen la figura de ruido de la cadena de recepci´on. En este caso el valor de la figura de ruido est´a en torno a los 7.2 dB. La Figura A.7 muestra la contribuci´on a la ganancia de cada uno de los bloques que constituye la cadena de recepci´on. La ganancia total del sistema est´a dividida 104 Figura A.8: Simulaci´on de figura de ruido del sistema. Figura A.9: Simulaci´on de linealidad del sistema. equitativamente entre el LNA los mezcladores y los amplificadores de banda base. Esta situaci´on proporciona un escenario relajado para los dise˜nadores de los diferentes bloques porque si un bloque no llega a alcanzar la ganancia propuesta, se puede intentar solucionar el problema aumentando la ganancia de los bloques posteriores. Por otro lado, tal y como se muestra en la Figura A.8, la contribuci´on de ruido depende mayoritariamente del LNA y los mezcladores. Debido a esta condici´on el dise˜no del LNA y de los mezcladores deber´a realizarse teniendo en cuenta intentar cumplir al m´aximo posible la especificaci´on de ruido. Finalmente, en la Figura A.9 se muestra la contribuci´on a la linealidad de cada uno de los bloques. En este caso la mayor contribuci´on la lleva a cabo los amplifica- Resumen en Castellano 111 Figura A.13: Comparativa inductor convencional frente a inductor multinivel. una frecuencia de 5 GHz. Como ya se hab´ıa adelantado anteriormente puede observarse como el rendimiento de los inductores multinivel es inferior al de los inductores convencionales. Esto es debido a las capacidades asociadas a los metales inferiores que influyen negativamente en el rendimiento del inductor. Gracias a la correcta compactaci´on del dise˜no como al uso de los inductores multinivel se ha conseguido una reducci´on de ´area importante. El dise˜no inicial (DA1) ocupa un ´area total de 0.74 mm2, incluyendo los pads de medida. Por el contrario, el dise˜no compactado (DA2) presenta un ´area total de 0.61 mm2lo que implica una reducci´on de ´area del 17 % con respecto al dise˜no inicial. Finalmente, el dise˜no con inductores multinivel (DA3) ocupa un ´area total de 0.47 mm2,loque implica una reducci´on de ´area de un 36 % con respecto al dise˜no inicial. Despu´es de la medida de m´ultiples muestras, la respuesta en frecuencia se muestra en la Figura A.14. La ganancia de la versi´on DA1 es de 6 dB con una planitud de ganancia de unos 0.6 dB desde 1 GHz hasta 5 GHz y con una ganancia unitaria alrededor de los 8.6 GHz. Por otro lado, el circuito presenta una figura de ruido por debajo de los 5 dB desde 1 GHz hasta los 6.5 GHz. El incremento de ganancia en banda base es debido a la alta impedancia de los condensadores de bloqueo de 112 Figura A.14: Medida del S21 y la figura de ruido. continua a baja frecuencia. La adaptaci´on tanto de entrada como de salida es mejor de -10 dB en todo el ancho de banda. La respuesta en frecuencia de la versi´on DA2 es aproximadamente la misma que la versi´on DA1, excepto en la mejora que aparece en la figura de ruido. Esta mejora es debido a una reducci´on de los par´asitos asociados al reducir la longitud de muchas l´ıneas de interconexi´on. Finalmente, con respecto a la versi´on DA3 y a pesar de que el rendimiento de los inductores multinivel es peor que el de los inductores convencionales, la respuesta de DA3 es muy similar a la obtenida con las versiones DA1 y DA2. La figura de ruido en este caso es un poco superior debido a la resistencia serie asociada a los inductores multinivel que es un poco superior a la resistencia serie de los inductores convencionales. Hay que mencionar que todas las medidas se hicieron bajo las mismas condiciones de polarizaci´on y que las tres versiones tienen un consumo de potencia de 90 mW. A.3.3 Aportaciones originales La principal aportaci´on de este cap´ıtulo es la implementaci´on de diferentes t´ecnicas para la reducci´on de ´area en los amplificadores distribuidos. Como se ha podido comprobar, se ha pasado de un ´area total ocupada de 0.7 mm2a un ´area total de 0.4 mm2gracias a las t´ecnicas de compactaci´on empleadas y al uso de inductores Resumen en Castellano 113 Circuito Ganan. (dB) BW (GHz) NF (dB) P1dB (dBm) Area (mm2) PDC (mW) DA1 7 6.5 512.3 0.74 90 DA2 7 6.5 4.5 12.4 0.61 90 DA3 5.5 6.5 611.2 0.47 90 Tabla A.6: Especificaciones de los amplificadores distribuidos. multinivel. A.3.4 Conclusiones Con la implementaci´on de los amplificadores distribuidos se ha tomado contacto con el dise˜no de amplificadores de bajo ruido para sistemas de ultra banda ancha. Como se ha podido comprobar, los amplificadores distribuidos presentan un gran ancho de banda aunque con relativamente poca ganancia. El principal problema de esta estructura radica en el alto consumo de potencia que presenta as´ı como el ´area ocupada. Para conseguir reducir el ´area ocupada se han presentado dos soluciones diferentes. Primeramente se ha llevado a cabo una recolocaci´on de los inductores en el circuito intentando minimizar la influencia del acoplamiento m´utuo entre ´estas. Por otro lado, se han introducido los inductores multinivel que a pesar de tener unas especificaciones peores que los inductores convencionales, el ´area ocupada es mucho menor. A pesar de tener peores especificaciones los inductores multinivel provocaron una influencia m´ınima en el rendimiento de los amplificadores distribuidos. Usando estas t´ecnicas se dise˜naron tres versiones de amplificadores distribuidos para poder llevar a cabo comparaciones entre ellos y se obtuvieron resultados satisfactorios en cuanto a la reducci´on de ´area. En la Tabla A.6 se muestra un resumen de las especificaciones de los amplificadores distribuidos desarrollados. A.4 Amplificadores de banda ancha A.4.1 Objetivos Los amplificadores distribuidos presentan un elevado consumo de potencia y ocupan un ´area elevada. De cara a optimizar el consumo de potencia y el ´area ocupada, el principal objetivo de este cap´ıtulo es la exploraci´on de diferentes arquitecturas de amplificadores para sistemas de comunicaci´on de ultra banda ancha intentando 114 Figura A.15: Esquema simplificado de un LNA con degeneraci´on inductiva. optimizar el consumo de potencia y el ´area consumida por los mismos. A.4.2 Planteamiento y metodolog´ıa A.4.2.1 Amplificador de banda ancha Para llevar a cabo la implementaci´on del amplificador de banda ancha se toma como partida la estructura de un amplificador cascodo de banda estrecha como el mostrado en la Figura A.15. Para conseguir transformar este amplificador de banda estrecha en un amplificador de banda ancha se lleva a cabo una modificaci´on de la red de adaptaci´on de entrada. En la estructura mostrada en la Figura A.16 puede observarse como la etapa de entrada puede considerarse compuesta por un filtro paso banda de cuarto orden. Este filtro de cuarto orden a su vez se puede dividir en dos etapas de segundo orden. Estos filtros de segundo orden est´an compuestos por una secci´on paso bajo y otra secci´on paso alto. La secci´on paso alto del filtro est´a compuesto por LByCπ. La relaci´on existente entre los componentes y la frecuencia de corte es la siguiente: high −pass �LB=R ωL ;Cπ=1 ωLR(A.9) Por otro lado, la secci´on paso bajo del filtro esta constituida por LEyporCB.En Resumen en Castellano 115 Figura A.16: Esquema simplificado LNA con adaptaci´on de banda ancha. este caso, la relaci´on entre los componentes y la frecuencia de corte es la siguiente: low −pass �LE=R ωU ;CB=1 ωUR(A.10) Las dos etapas de filtrado proporcionan una impedancia igual a R en la banda de paso entre ωUyωL. De cara a conseguir una operaci´on en banda ancha, una opci´on puede ser sustituir la carga resonante del circuito por una simple resistencia. Esta soluci´on presenta un problema importante porque el polo par´asito generado por la resistencia de salida y la capacidad par´asita del nodo de salida provoca una ca´ıda a alta frecuencia. Una t´ecnica t´ıpica para solucionar este problema es cambiar la resistencia por una carga shunt-peaking [8] compuesta por un inductancia colocada en serie a la carga de salida. Esta inductancia en serie provoca un aumento de la frecuencia de corte debido a que la inductancia introduce un cero que elimina la influencia del polo formado por la resistencia de carga y la capacidad par´asita asociada al nodo de salida. Con esta configuraci´on la carga inductiva ecualiza la ganancia a un valor constante a lo largo de la banda de paso. El problema es que la combinaci´on entre la carga inductiva y Cout introduce una resonancia que debe mantenerse siempre fuera de la banda. Como Cout representa la capacidad total en el nodo de salida incluyen- 116 Figura A.17: Fotograf´ıa del amplificador de banda ancha. do capacidades par´asitas asociadas a las conexiones y a las propias capacidades del transistor, es necesario minimizar siempre ese efecto para asegurar que la resonancia entre la carga inductiva y Cout se produzca por encima de ωU. En la Figura A.17 se muestra una fotograf´ıa del LNA desarrollado. El ´area total del chip incluyendo los pads de medida es de 665x665 µm2. El amplificador consume 5.3 mA de una fuente de alimentaci´on de 3.3 V. En la Figura A.18 se muestra una comparativa entre la medida y la simulaci´on del amplificador de banda ancha desarrollado y puede observarse como los resultados de las medidas son bastante similares a los obtenidos en simulaci´on. La ganancia m´axima est´a alrededor de 12.5 dB a una frecuencia de 3.4 GHz y el ancho de banda a 3 dB va desde 1.7 a 5.3 GHz. La ganancia unitaria del circuito es de 9.4 GHz. La medida de las p´erdidas de retorno en la entrada (S11) es inferior a -5 dB en toda la banda de trabajo. Por otro lado, las p´erdidas de retorno a la salida (S22) se encuentran tambi´en por debajo de los -4 dB en toda la banda. En la Figura A.19 se muestra la comparativa entre la simulaci´on y la medida de la figura de ruido. La figura de ruido var´ıa desde los 4.3 dB a 3.9 GHz hasta los 5.2 dB a 5.3 GHz, observ´andose como hay una similitud entre los valores de figura de ruido medidos y simulados. Finalmente, el punto de intercepci´on de tercer orden del circuito se encuentra en -4 dBm. A.4.2.2 Amplificador Shunt-peaking modificado Uno de los principales problemas del amplificador de banda ancha es que no Resumen en Castellano 117 Figura A.18: Comparativa de simulaci´on y medida de los par´ametros S. 118 Figura A.19: Comparativa de simulaci´on y medida de la figura de ruido. Resumen en Castellano 119 Figura A.20: Esquem´atico del LNA banda ancha con transistores MOSFET. mantiene la ganancia constante a lo largo de toda la banda, esta falta de planitud en la ganancia est´a directamente relacionado con la carga de salida empleada. En la Figura A.20 se muestra una versi´on con transistores MOSFET del amplificador de banda ancha. Este circuito esta compuesto por una etapa de ganancia con degeneraci´on inductiva (LgyLs) y una carga de salida de banda ancha. Con el fin de adaptar la se˜nal de salida a 50 Ωse ha a˜nadido un seguidor de emisor en la salida (M3). Al igual que en el caso anterior, la impedancia de entrada esta formada por la combinaci´on de dos filtros paso bajo y paso alto. La ganancia de esta estructura la proporciona una estructura cascodo que mejora el aislamiento en inversa y disminuya el efecto de la capacidad Miller sobre la respuesta en frecuencia del circuito. El dimensionado de los transistores ha sido determinado para obtener un bajo ruido y un bajo consumo de potencia. Como se muestra en la Figura A.21, y al igual que en el caso anterior, para conseguir una operaci´on de banda ancha se ha cambiado la red resonadora por una red shuntpeaking. Con esta estructura, la ganancia dentro de la banda deber´ıa ser plana y el valor de esta ganancia es proporcional a la tranconductancia del par cascodo y a la impedancia de salida de la estructura shunt-peaking que viene dada por la siguiente 120 Figura A.21: (a) shunt-peaking convencional (b) shunt-peaking modificado. expresi´on: ZL(jω)= RL+ωLL 1−ω2LLCout +jωCoutRL (A.11) donde Cout representa la capacidad equivalente en el nodo de salida del circuito incluyendo las capacidades par´asitas de los transistores y todas las capacidades asociadas al interconexionado. Como se puede observar, la expresi´on anterior contiene dos polos y un cero. La existencia de estos polos y ceros provoca la aparici´on de un pico en la respuesta en frecuencia del circuito, degradando la planitud de la ganancia. Una posible soluci´on a este problema es mantener ambas resonancias fuera de la banda usando un valor bajo para LL, pero esa soluci´on implica una baja ganancia del circuito. Con el fin de mantener una alta ganancia se debe elegir un valor de RLsuficientemente alto para mejorar la ganancia a baja frecuencia. Sin embargo, el rango din´amico del circuito impone una limitaci´on en cuanto al valor resistivo de RL.Para intentar solucionar estos inconvenientes se propone una modificaci´on de la estructura shunt-peaking. La modificaci´on de la estructura shunt-peaking tal y como se ve en la Figura A.21 esta basada en una estructura convencional shunt-peaking que actua de manera desacoplada de la etapa cascodo a trav´es del condensador CC. Para polarizar la etapa activa se ha colocado el inductor LCentre VDD yeldrenadordeltransistorM2.En consecuencia, la impedancia de esta nueva etapa viene dada por: Z(jω)= jωLCRL�jωLL RL+1 � 1−jω3LCLLCout −ω2LCRLCout +jω(LC+LL)(A.12) Resumen en Castellano 127 Dise˜no. Ganancia (dB) BW (GHz) NF (dB) IIP3 (dBm) Area (mm2) PDC (mW) Banda ancha 12.5 5.3 4.3 -4 0.13 32 Shunt-peaking modificado 11.2 555.1 0.29 56.1 Cascodo doblado 8.24 2.96 3-4 0.13 18.93 Tabla A.8: Especificaciones de los amplificadores desarrollados. trabajado tambi´en en la optimizaci´on de ´area de los mismos utilizando inductores multinivel cuando ha sido posible. A.4.4 Conclusiones A lo largo de este cap´ıtulo se han presentado tres diferentes alternativas para la implementaci´on de LNAs para comunicaciones de ultra banda ancha con unas especificaciones superiores a las obtenidas con los amplificadores distribuidos. La primera alternativa presentada fue el amplificador de banda ancha que tiene una buena respuesta en frecuencia pero presenta algunos problemas para mantener la planitud de la ganancia. Para solucionar este problema se desarroll´o el circuito con una estructura shunt-peaking modificada. Finalmente, se desarroll´o una estructura cascodo doblado que puede trabajar con bajos niveles de tensi´on, presentando una linealidad superior a la obtenida con las otras estructuras. A modo resumen, en la Tabla A.8 se recogen las especificaciones de los circuitos desarrollados. A.5 Amplificadores realimentados A.5.1 Objetivos En general, las t´ecnicas de realimentaci´on ayudan a mejorar el rendimiento en amplificadores. El bucle de realimentaci´on ayuda a incrementar el ancho de banda y la ganancia y en algunos casos, incluso colabora a conseguir una reducci´on de la figura de ruido y el consumo de potencia. Es por estos motivos por los que es interesante estudiar la posibilidad de aplicar t´ecnicas de realimentaci´on al dise˜no de 128 Figura A.31: Esquem´atico LNA realimentado. amplificadores de bajo ruido para sistemas de ultra banda ancha. A.5.2 Planteamiento y metodolog´ıa A.5.2.1 Aproximaci´on t´eorica La Figura A.31 muestra el esquem´atico de un amplificador emisor com´un realimentado. Ignorando algunos problemas asociados a las capacidades par´asitas del transistor, la ganancia de tensi´on viene dada por la siguiente expresi´on: AV=vo vi = RL RF−gmRL 1+RL RF≈−gmRL 1+RL RF (A.13) donde gmes la transconductancia del transistor Q1. Esto significa que la ganancia sin la realimentaci´on (-gmRL)esreducidaporla presencia del bucle de realimentaci´on. La impedancia de entrada tambi´en cambia con respecto al amplificador en bucle abierto. Ignorando los efectos de capacidades par´asitas la impedancia de entrada queda acorde a la siguiente expresi´on: Zin =RF+RL (1 + gmRL)≈RF+RL gmRL (A.14) Resumen en Castellano 129 En este caso concreto, la realimentaci´on colabora a mejorar la linealidad del circuito. En cambio, a pesar de mejorar la linealidad se produce un empeoramiento en el factor de ruido debido a la influencia de un nuevo inductor en la entrada del circuito. Llevando a cabo un an´alisis de ruido, se puede obtener que el factor de ruido sigue la siguiente expresi´on: F=1+rb+re RS +1 2gmRS +gmRs 2β+gmRS 2β2+1 2gm RS RF 2+RS RF (A.15) donde rbyreson las resistencias par´asitas de base y emisor y βes la ganancia en corriente de peque˜na se˜nal. Tal y como se hab´ıa comentado del an´alisis de ruido se extrae que la resistencia de realimentaci´on RFinfluye negativamente en el ruido del circuito. Esto es debido a que la resistencia RFtiene una magnitud similar a la resistencia de base RS. La relaci´on existente entre la linealidad del circuito y los par´ametros del mismo es la siguiente: IIP3LNA ∝gm 2∝Ibias 2(A.16) Intuitivamente, un valor grande de gmmejorar´a la linealidad del circuito. Una mayor gmimplica un mayor consumo de corriente. Sin embargo, cuando se trabaja en alta frecuencia es necesario inyectar m´as corriente para minimizar el efecto de los par´asitos y obtener ganancia. El hecho de tener que inyectar m´as corriente proporciona cierta flexibilidad a la hora de obtener el valor de gm. La ganancia de tensi´on dada por la Ecuaci´on A.13 proporciona una relaci´on entre RLyRFpara una gmdada. Como resultado de esto, el factor de ruido y la impedancia de entrada est´an acoplados porque tal y como se muestra en las ecuaciones A.13 y A.15 ambos elementos dependen de los valores de RLyRF.Debidoaestarelaci´onpuede ser complicado llegar a conseguir un compromiso entre ambos valores para un bajo factor de ruido y una adaptaci´on de entrada de 50 Ω. Para resolver este inconveniente, puede ser ´util reemplazar el bucle de realimentaci´on pasivo por un bucle activo compuesto por un seguidor de emisor tal y como se muestra en la Figura A.32.Enestecaso,laimpedanciadelcircuitovienedada por la siguiente expresi´on: Zin =1+gm2RF gm2(1 + gm1RL)≈RF gm1RL (A.17) 130 Figura A.32: Esquem´atico LNA realimentado con bucle activo. donde gm2es la transconductancia del transistor Q2. Para una impedancia de entrada de 50 Ωy para la misma ganancia de tensi´on el valor de RFmejora en este caso con respecto al caso anterior. Otra ventaja de esta alternativa es que gracias al uso de RF,RByQ2,latensi´ondecolectordeQ1puede ser modificada tal y como se muestra en la siguiente expresi´on: VCE1≈VBE2+VBE1·�RF RB +1 �(A.18) Como resultado, se puede aumentar la linealidad total del circuito. Finalmente, en el dise˜no propuesto de cara a mejorar el ancho de banda se ha reemplazado la carga de salida por una carga shunt-peaking tal y como se ha hecho en otros circuitos. A.5.2.2 Resultado Experimentales De cara a reducir el ´area total del circuito, se ha optado por utilizar inductores multinivel modificados tal y como se muestra en la Figura A.33. Como puede observarse, el inductor va desde el nivel m´as alto de metalizaci´on al m´as bajo y luego Resumen en Castellano 131 Figura A.33: Estructura de inductor 3D. Figura A.34: Layout y medida del inductor 3D modificado. 132 Figura A.35: Fotograf´ıa de los LNAs: (a) versi´on inductores convencionales, (b) versi´on inductor 3D modificado. vuelve a subir. En la Figura A.34 se puede ver el layout y resultados de simulaci´on del inductor. Como se puede observar, presenta un factor de calidad relativamente bajo. Este factor de calidad tan bajo es debido al incremento de los par´asitos con respecto al sustrato al bajar a trav´es de los diferentes niveles de metalizaci´on. Para comprobar el correcto funcionamiento del circuito con la bobina 3D modificada, se han desarrollado dos versiones del circuito. En la primera versi´on se han empleado inductores convencionales y en la segunda versi´on se ha usado el inductor modificado 3D. En la Figura A.35 se muestra una fotograf´ıa de ambos circuitos. las dimensiones del ´area activa de ambos circuitos es de 490x355 µm2para el LNA1 y de 330x310 µm2para el LNA2. Utilizando los inductores 3D modificados, se ha conseguido un ahorro de ´area de un 40 % con una influencia m´ınima en las especificaciones del circuito. En la Figura A.36 y en la Figura A.37 se muestra la simulaci´on de ganancia del circuito y de la figura de ruido. Ambos amplificadores tienen una ganancia que var´ıa desde los 14 dB hasta los 7 dB en la banda que va desde los 3.1 GHz hasta los 10.6 GHz. La figura de ruido para el LNA1 va desde los 4.2 dB hasta los 5.6 dB a 10.6 GHz. En el caso del LNA2 la figura de ruido pasa desde los 2.9 a 4 dB en el rango de 3.1 a 10.6 GHz. Ambos circuitos presentan una correcta adaptaci´on de entrada y salida en el rango de 3.1 GHz a 10.6 GHz. Finalmente, en la Figura A.38 se muestra la simulaci´on de linealidad de ambos Resumen en Castellano 133 Figura A.36: Simulaci´on y medida de ganancia. Figura A.37: Simulaci´on y medida de figura de ruido. 134 Figura A.38: Medida linealidad (a) LNA1 (b) LNA2. circuitos. Como puede observarse, el LNA1 tiene un IIP3 de -3.4 dBm y el LNA2 presenta un IIP3 de -4.4 dBm. A.5.3 Aportaciones originales En este cap´ıtulo se ha hecho uso de las t´ecnicas de realimentaci´on y se ha podido obtener un LNA con unas especificaciones superiores a cualquiera de los desarrollados en cap´ıtulos anteriores. El uso de inductores multinivel 3D ha posibilitado reducir el ´area del circuito en un 40 % con una m´ınima influencia en las especificaciones del circuito. A.5.4 Conclusiones El uso de las t´ecnias de realimentaci´on ha permitido mejorar las prestaciones del LNA desarrollado, provocando una mejora considerable con respecto a los circuitos desarrollados en cap´ıtulos anteriores. Por otro lado, el uso de inductores 3D modificados ha posibilitado una reducci´on de ´area considerable en comparaci´on a circuitos desarrollados con inductores convencionales. En la Tabla A.9 se muestra un resumen de las especificaciones de los circuitos Resumen en Castellano 135 Ref. Ganancia (dB) BW (GHz) NF (dB) P1dB (dBm) Area (mm2) PDC (mW) Inductor est´andar 14 5.5 <4-3.4 0.17 13.2 Inductor 3D 14 6.7 <4-4.4 0.10 13.2 Tabla A.9: Especificaciones de los amplificadores. desarrollados en este cap´ıtulo. A.6 T´ecnicas sin inductores A.6.1 Objetivos A lo largo de todo el trabajo se ha podido comprobar que la mayor parte del ´area esta ocupada por los inductores integrados. De cara a reducir el ´area, en este cap´ıtulo se explorar´a el desarrollo de una estructura sin inductores. A.6.2 Planteamiento y metodolog´ıa A.6.2.1 Aproximaci´on te´orica Para el desarrollo del LNA sin inductores se ha optado por desarrollar un LNA puerta com´un. La estructura en puerta com´un no sufre del efecto Miller, de hecho la red de adaptaci´on de entrada y la red de salida pueden ser dise˜nadas de forma independiente. La estructura m´as b´asica de amplificador puerta com´un es la mostrada en la Figura A.39 (a). Para que el circuito funcione correctamente es necesario que haya una gran impedancia desde el nodo de entrada a tierra, la opci´on m´as sencilla es colocar una fuente de corriente, pero esa fuente de corriente har´a empeorar las especificaciones de ruido del circuito. Una soluci´on a este problema puede ser la soluci´on mostrada en la Figura A.39 (b) donde se sit´ua un inductor en serie que forma un resonador con la capacidad par´asita asociada Cpar.Estasituaci´onpuede darse en casos en los que no sea necesaria conexi´on externa. Cuando es necesaria una conexi´on externa aparece el caso mostrado en la Figura A.39 (c) donde aparece un inductor en serie (asociado al conexionado) as´ı como una capacidad de entrada. En esta estructura concreta se puede conseguir una adaptaci´on de entrada a 50 Ω utilizando capacidades. La Figura A.40 muestra de manera resumida la interfaz de uni´on entre el LNA y 136 Figura A.39: Etapas de entrada LNA puerta com´un: a) fuente de corriente, b) resonador paralelo c) resonadores en serie y paralelo. Figura A.40: Conexionado simplificado de (a) shunt-peaking y (b) degeneraci´on capacitiva.