Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography

Doctoral Thesis Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography Author: Franco Nahuel Bandi Advisors: Ricardo Carmona Galán Ángel Rodríguez Vázquez Sevilla 2020 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography By: Franco Nahuel Bandi PROPUESTA DE TESIS DOCTORAL PARA LA OBTENCIÓN DEL GRADO DE DOCTOR EN CIENCIAS Y TECNOLOGÍAS FÍSICAS Advisors: Ricardo Carmona Galán Ángel Rodríguez Vázquez Seville, 2020 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography Doctoral Thesis Universidad de Sevilla Franco Nahuel Bandi Master in Microelectronics Advisor: Ricardo Carmona Galán Tenured Scientist Instituto de Microelectronica de Sevilla Consejo Superior de Investigaciones Advisor: Ángel Rodríguez Vázquez Full Professor Electronics and Electromagnetism Department Universidad de Sevilla Universidad de Sevilla Consejo Superior de Investigaciones Científicas Centro Nacional de Microelectrónica Instituto de Microelectrónica de Sevilla Calle Américo Vespucio, 28. Parque Científico y Tecnológico Cartuja. 41092 Sevilla Author e-mail: [email protected] This work is licensed under a Creative Commons Attribution-Non Commercial- No Derivatives 4.0 International License. Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Acknowledgements Será imposible hacer justicia en estas líneas y agradecer a toda la gente que me apoyó y, de alguna forma u otra, hizo posible este desenlace, por lo que tal vez debería empezar pidiendo disculpas por el olvido y la brevedad. No creo que haya un solo evento, uno discreto e independiente, que haya desembocado en la realización esta tesis. Más bien, esto probablemente sea consecuencia de una integración de circunstancias, pequeñas, ingravidas y sutiles. ¡Gracias totales! I would like to thank my advisor Dr Ricardo Carmona Galán for his mentoring and support over these years. His experience and knowledge in electronics and image sensor design was fundamental at each stage of the thesis. My gratitude must be extended to my co-advisor Dr Ángel Rodríguez Vázquez, who provided very valuable advice during the analysis and design of circuits. Their support and passion for this subtle art allowed me to grow as a designer, but more important, as a person. También tengo que agradecer al Ministerio de Economía y Competitividad por proporcionar la financiación de mi contrato FPI (BES-2016-076255) que me permitió realizar mi tesis. I would like to thank Dr Rafael Ballabriga Sune and Dr Michael Campbell for giving me the opportunity of doing a four-months research stay at CERN, where I learned a lot about time-to-digital converter design, fast timing applications and X-ray detectors. Also, I would like to thank Iraklis, Samuele, Cienti, Sara M. V., Jerome and Wojciech for all their invaluable help and patience during the whole stay. Specially, I am very grateful to Jose and Nuria not only for sharing their expertise in fast timing, but also for our non-technical discussions. Quiero agradecer a Ion por sus discusiones de carácter técnico, su ayuda a la hora de dilucidar los entresijos del funcionamiento de algunos circuitos y su soporte durante la caracterización del chip. Tampoco puedo olvidar la ayuda recibida de Joaquín, Antonio R., Antonio L., Cristina y Luis durante los test en el laboratorio. No puedo dejar pasar la ocasión sin agradecer a mis compañeros Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be iv del grupo, Jorge, Juan Antonio, James, Raffaela y Marco, con los tuve la suerte de coincidir. Asimismo, me gustaría dar las gracias a todo el personal del IMSE, área técnica, informática, administración y mantenimiento, por su ayuda y por crear un espacio de trabajo acogedor. A todos ustedes ¡Gracias! With a special mention to all the members, past and future, of the 34: José Luis, Alfredo, Andrés, Héctor, Beti, Luca, Giuseppe, Norber, Pablo, Antonio, Valentín, Juan, David, Virginia, Rubén e Isma. For those all good and bad moments that you where there, giving me advice and being patient. It was an honor to share the space with all of you during these last years. Me gustaría aprovechar estas líneas para agradecer a todos mis profesores y maestros. En particular, a aquellos que dedicaron su tiempo y paciencia en hacerme crecer como persona y me enseñaron que la vida es el camino, no los hitos. ¡Grego, Sebastian, Jaume, Rodrigo y Eugenio muchas gracias! Finalment, no puc deixar d’agrair als meus amics Cristian, Sergio, José, Joan, Miquel, Roberto, Naza, Inés i Juan que m’han donat el seu suport al llarg de tot aquest camí i, sempre que ho vaig necessitar, em varen donar un lloc tranquil on descansar. Gràcies a tots vosaltres per omplir la meva memòria de bons records, els meus ulls de la verdor de la muntanya i els meus pulmons de la frescor de la mar! Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be CONTENTS Contents v List of Figures ix List of Tables xv Acronyms xvii Abstract xxi 1 Introduction to SiPM Sensors for Medical Applications 1 1.1 Electronics and Medical Imaging: a Brief History . . . . . . . . . . 2 1.2 Positron Emission Tomography . . . . . . . . . . . . . . . . . . . . 4 1.3 Scintillation Phenomena and Light Propagation . . . . . . . . . . 6 1.4 Photodetector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 Case Study and Desired Features (Thesis Goals) . . . . . . . . . . 14 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 SPAD and Front-End Electronics in CMOS Technologies 17 2.1 SPAD Working Principle . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 SPAD Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 Photon Detection Probability . . . . . . . . . . . . . . . . . 24 2.2.3 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.4 Premature Edge Breakdown . . . . . . . . . . . . . . . . . . 25 2.3 Implemented SPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 Quenching and Recharge Circuit . . . . . . . . . . . . . . . . . . . 27 2.4.1 Passive Quenching and Recharge Circuit . . . . . . . . . . 28 2.4.2 Active Quenching and Recharge Circuit . . . . . . . . . . . 30 2.4.3 Passive Quenching Active Recharge Circuit . . . . . . . . . 31 2.5 Proposed Active Quenching and Recharge Circuit . . . . . . . . . 32 2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 Time-to-Digital Converter Design 35 3.1 TDC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 v Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be xii List of Figures 4.3 SPAD size, x , as a function of number of sub-pixels per pixel and number of SPADs per micro-cell. . . . . . . . . . . . . . . . . . . . . . 73 4.4 Sensitivity as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for optimized size. . . . . . . . . . . . . . 74 4.5 Counted photons as a functions of incident photons with 1 SPAD per micro-cell for optimized size. The dashed line represents the detected photons (ideal sensor response), the triangle is pointing the maximum number of incident photons in Tclk . . . . . . . . . . . . . . 75 4.6 Graphic definition of non-linearity. . . . . . . . . . . . . . . . . . . . . 75 4.7 Pixel non-linearity for optimized size SPAD. . . . . . . . . . . . . . . . 76 4.8 Signal to noise ratio as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for optimized size. . . . . . . . . 77 4.9 Data path from sub-pixel output to finite state machine (FSM) input. 78 4.10 Sensitivity as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for constant SPAD size. . . . . . . . . . . 79 4.11 Counted photons as a functions of incident photons with 16 SPADs per micro-cell for constant SPAD size. The dashed line represents the detected photons (ideal sensor response), the triangle is pointing the maximum number of incident photons in Tclk . . . . . . . . . . . . 80 4.12 Pixel non-linearity for constant SPAD size. . . . . . . . . . . . . . . . . 80 4.13 Signal to noise ratio as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for constant SPAD size. . . . . . 81 4.14 Proposed digital SiPM architecture with an adder tree of 5 levels and the SPADs are clustered into 32 sub-pixels. . . . . . . . . . . . . . . . . 82 4.15 (a) Sub-pixel architecture, (b) block diagram of counter block working interleaved. Dotted arrows represent the data flow when clk =0. 84 4.16 Pixel micro-photography. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.1 Inverse current as a function of cathode-anode voltage for SPADs with different sizes and shapes at room temperature: (a) PP/NW3V3 diodes with premature edge breakdown (PEB) and (b) PW3V3/DNW diodes without PEB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 Histogram of break down voltage of the PW3V3/DNW devices at room temperature. The mean is 18.01V and the total number of samples is N=400 from 4 different chips. . . . . . . . . . . . . . . . . 89 5.3 Break down voltage for a PW3V3/DNW SPAD as a function of temperature. Linear fit shows a slope of 14 mV/K. . . . . . . . . . . . . . . 90 5.4 Breakdown resistance as a function of the inverse of the SPAD active area at room temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5 (a) Avalanche photo-emission of PP/NW1V2 SPAD with premature edge breakdown and ISPAD =10mA (b) avalanche photo-emission of PW3V3/DNW SPAD without premature edge breakdown and ISPAD = 19mA. Turned-off SPADs are shown for comparison purposes. . . . . 91 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be List of Figures xiii 5.6 (a) Desired PP/NW3V3 SPAD structure (b) implemented PP/NW3V3 SPAD structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7 Dark count rate (DCR) map for PW3V3/DNW devices with Vex =2V and td=5µs . White areas stand for non-working quenching ( ISPAD > 1mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.8 DCR map for PW3V3/DNW devices with Vex =3V and td=5µs . White areas stand for non-working quenching (ISPAD >1mA). . . . . 94 5.9 Cumulative DCR population for 2432 PW3V3/DNW SPADs at room temperature. SPAD active area is 200µm2 and median DCR 0.4Hz/µm2 . 95 5.10 DCR as a function of temperature for PW3V3/DNW SPAD. EA1 slope is associated to thermal trap assisted Shockley-Read-Hall generation and EA2slope is associated to band-to-band tunneling. . . . . . . . . 96 5.11 (a) Color micro photography of a SPAD micro-cell and (b) avalanche photo-emission of two SPADs with out proper quenching ( Vex =1V and ISPAD =1mA), the other SPADs are turned-off. . . . . . . . . . . . 96 5.12 Photon detection probability as a function ofwavelengthwith PW3V3/DNW SPADs for Vex =0.5V and td=5µs. . . . . . . . . . . . . . . . . . . . . 97 5.13 Photon detection probability as a function of excess voltage for PW3V3/DNW SPADs at λ=420nm (circle) and λ=470nm (cross). . 98 5.14 Counted photons as a functions of incident photons for the implemented pixel at λ=420nm and Vex =3.0V . The dashed line represents the detected photons (ideal sensor response), star marker represents the estimated detected photons and square marker represents the simulated detected photons. . . . . . . . . . . . . . . . . . . 98 5.15 TDC resolution as a function of bias voltage. Solid lines represents post-layout simulation results and dashed line stand for experimental data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.16 Differential non-linearity and integral non-linearity of the TDC of the first 512 codes ( ∼50ns ). The periodicity at the integral non-linearity could be attributed to coupling between the ring oscillator and the ripple counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be LIST OF TABLES 1.1 Properties of common scintillator crystal used in medical and high energy physic applications [2, 3, 4]. . . . . . . . . . . . . . . . . . . . . 9 1.2 State of the art of Silicon Photomultiplier (SiPM). . . . . . . . . . . . . 14 2.1 Usual magnitudes for the SPAD circuit model of figure 2.8. . . . . . . 28 2.2 Transistor sizes for circuit of figure 2.12. . . . . . . . . . . . . . . . . . 33 3.1 Transistor nominal sizes and load capacitor. . . . . . . . . . . . . . . . 48 3.2 Phases of a ring oscillator with 4 stages. . . . . . . . . . . . . . . . . . 61 3.3 Post-layout simulation results. . . . . . . . . . . . . . . . . . . . . . . . 62 4.1 Parameter values used for the architectural exploration. These values are obtained from our own library blocks, simulations and measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2 Set-up and hold-on conditions for Nµc=1. . . . . . . . . . . . . . . . 77 4.3 Set-up and hold-on conditions for constant SPAD size and Nµc=16. 81 4.4 Expected performance of the proposed SiPM architecture. . . . . . . 85 xv Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be ACRONYMS a-SiPM Analog Silicon Photomultiplier ADC Analog to Digital Converter ADPLL All-Digital Phase Locked Loop AQRC Active Quenching and Recharge Circuit BGO Bismuth Germanate CAD Computer-Aided Design CIS CMOS Image Sensor CsI Cesium Iodide CT Computed Tomography CTR Coincidence Time Resolution DNL Differential Non-Linearity d-SiPM Digital Silicon Photomultiplier DCR Dark Count Rate DOI Depth Of Interaction ENOB Effective Number Of Bits FF Fill Factor FLIM Fluorescence-Lifetime Imaging Microscopy FOM Figure Of Merit FOV Field Of View FPGA Field-Programmable Gate Array xvii Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be xviii ACRONYMS FSM Finite State Machine HEP High Energy Physics INL Integral Non-Linearity LiDAR Light Detection and Ranging LOR Line Of Response LSB Less Significant Bit LSO Lutetium Oxyorthosilicate LYSO Lutetium Yttrium Orthosilicate MRI Magnetic Resonance Imaging NaI Sodium Iodide PDE Photon Detection Efficiency PDP Photon Detection Probability PEB Premature Edge Breakdown PET Positron Emission Tomography PLL Phase Locked Loop PMT Photomultiplier Tube PQARC Passive Quenching and Active Recharge Circuit PQRC Passive Quenching and Recharge Circuit PVT Process, Voltage and Temperature PWO Lead Tungsate QE Quantum Efficiency QRC Quenching and Recharge Circuit SiPM Silicon Photomultiplier SNR Signal to Noise Ratio SPAD Single-Photon Avalanche Diode Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be ACRONYMS xix SRAM Static Random Access Memory SRH Shockley-Read-Hall STI Shallow Trench Isolation TCAD Technology Computer-Aided Design TDC Time to Digital Converter ToF Time of Flight VCRO Voltage Controlled Ring Oscillator VLSI Very Large-Scale Integration XCI Cross-Coupled Inverters XCP Cross-Coupled PMOS ZnS Zinc Sulfide Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be ABSTRACT This thesis presents a contribution to the design of single-photon detectors for medical imaging. Specifically, the focus has been on the development of a pixel capable of single-photon counting in CMOS technology, and the associated sensor thereof. These sensors can work under low light conditions and provide timing information to determine the time-stamp of the incoming photons. For instance, this is particularly attractive for applications that rely either on time-of-flight measurements or on exponential decay determination of the light source, like positron emission tomography or fluorescence-lifetime imaging, respectively. This thesis proposes the study of the pixel architecture to optimize its performance in terms of sensitivity, linearity and signal to noise ratio. The design of the pixel has followed a bottom-up approach, taking care of the smallest building block and studying how the different architecture choices affect performance. Among the various building blocks needed, special emphasis has been placed on the following: • the Single-Photon Avalanche Diode (SPAD), a photodiode able to detect photons one by one; • the front-end circuitry of this diode, commonly called quenching and recharge circuit; • the Time-to-Digital Converter (TDC), which determines the timing performance of the pixel. The proposed architectural exploration provides a comprehensive insight into the design space of the pixel, allowing to determine the optimum design points in terms of sensor sensitivity, linearity or signal to noise ratio, thus helping designers to navigate through non-straightforward trade-offs. The proposed TDC is based on a voltage-controlled ring oscillator, since this architecture provides moderate time resolutions while keeping the footprint, the power, and conversion time relatively small. Two pseudo-differential delay stages have been studied, one with cross-coupled PMOS transistors and the other with cross-coupled inverters. Analytical studies and simulations have shown that cross-coupled inverters are the most appropriate to implement the TDC because they achieve better time resolution with smaller energy per conversion than cross-coupled PMOS transistor stages. xxi Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1. INTRODUCTION TO SIPM SENSORS FOR MEDICAL APPLICATIONS LOR e--e+ annihilation Scintillator Detector Uniform distribution 511 keV 511 keV Conventional PET TOF PET Gaussian distribution LOR e--e+ annihilation Scintillator Detector 511 keV 511 keV TOF1TOF2 Figure 1.2: Positron emission tomography (PET) working principle: (a) conventional scanner and (b) time of flight (TOF) scanner. the improvements in image quality and acquisition time, this is prohibitive on many occasions due to the high cost of the components, mainly scintillator crystals [ 17 ]. Secondly, gamma photons can also suffer several scattering along their trajectory. As figure 1.3-(b,c) represents, this can happen inside the patient’s body or the scintillator. This kind of interaction between gamma photons and matter, changes the direction and reduces the energy of the gamma photon. Generally, in order to reduce the impact of this non-ideality, only events with an energy close to 511keV are considered during the image reconstruction, the others are discarded. Also, to reduce the probability that the gamma photons escapes from scintillator, high density crystal, like lutetium oxyorthosilicate (LSO), bismuth germanate (BGO) or lead tungsate (PWO), are preferred over others less dense, like cesium iodide (CsI) or sodium iodide (NaI). 1.3 Scintillation Phenomena and Light Propagation Since the discovery of the scintillation phenomena of zinc sulfide (ZnS) in 1903 by W. Crookes [ 18 ], a lot of effort has been done by the community to understand the physics behind and to develop new compounds [ 2 ]. It is indispensable for the electronic designer to understand the most basic physical phenomena occurring during a scintillation, like the transformation of gamma photons into optical photons, light propagation and extraction from the scintillator to the sensor. This is important because the scintillator is a key part of the sensor interface, since it transforms the ionizing energy of the gamma photons into 6 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1.3. Scintillation Phenomena and Light Propagation LOR e--e+ annihilation Scattered coincidence (a) (b) LOR e--e+ annihilation Random coincidence LOR Comptom scatter without photoelectric e--e+ annihilation (c) Figure 1.3: PET non-idealities: (a) random coincidence, (b) scatter coincidence and (c) Compton scatter without photoelectric absorption. Conduction band Valence band Band gap Activator excited state Activator ground state ... Scintillation photons Figure 1.4: Band diagram of a scintillator crystal. visible photons that can be detected by silicon photodiodes. To properly design the sensor, it is important to understand the way this transformation is done, its magnitude, dynamics and spatial distribution. It is also necessary to be aware of secondary phenomena that may have the key for producing prompt photons which will bring a CTR improvement in a near future, like ˇ Cerenkov radiation or hot intraband luminescence [19]. For PET scanners, inorganic scintillators have been used because of their larger light yield ( photons/MeV ), radiation hardness and fast response, compared to organic or plastic scintillators. From the point of view of light generation, these crystals can be classified into few categories, depending on which type of recombination center is present in their crystalline lattice: doping impurity or activator, like cerium/calcium doping in LSO and lutetium yttrium orthosilicate (LYSO); self-trapped excitons, like CsI; luminescence ion, like Bi +3 in BGO; and may others [2, 20]. The emission of optical photons in an inorganic scintillator can be explained 7 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1. INTRODUCTION TO SIPM SENSORS FOR MEDICAL APPLICATIONS with its band diagram, as the one shown in figure 1.4. Scintillator crystals can be considered as insulators, since its band gap is high enough to prevent free electrons in the conduction band at room temperature, in the order of 5eV [ 21 ]. This means that the electrons in the valence band are bound to the crystal lattice, while the conduction band is empty. In scintillators with doping impurities as recombination centers, like Ce +3 , Eu +2 or Tl + [ 2 ], the impurities add several discrete energy levels in the band gap, without changing the valence or the conduction band. In these recombination centers, the excited electron can be here recombined with an hole emitting a large number of photons in the visible spectrum [ 20 , 21 ]. On the contrary, some scintillators, like BGO, does not need a doping impurity, because its crystal lattice include a luminescence ion intrinsically. In the case of BGO, the Bi +3 ion is the recombination center of the crystal lattice where electrons returns to their ground state [20]. All in all, a scintillation event can be summarized as follows: an ionizing particle, like a gamma photon, provides enough energy to an electron in the valence band and generates a free electron-hole charge. The hole travels to a recombination center, since the ionization energy of crystal lattice is higher than the ionization energy of recombination center. The electron also travels to find the ionized recombination center. At this point, the recombination center becomes neutral and the electron starts its de-excitation, emitting thousands of photons in the ultraviolet and visible spectrum [ 20 ]. This emission is isotropic, that is, in any direction, and its dynamics can be described with one or several exponential decays [18]: N=Aexpµ−t τf¶+Bexpµ−t τs¶(1.4) where N is the total number of emitted photons at time t , τf is the fast time constant, τs is the slow time constant, A and B are relative magnitudes of light yield that depends on the scintillator. LSO and LYSO are commonly modeled with one time constant of 40ns , while PWO is modeled with two time constant: τf=10ns and τs=30ns [ 22 ]. A summary of some scintillator properties is given in table 1.1. In spite of the above, several interactions may occur between a gamma photon and the crystal electrons. Mostly, these interactions can be divided into Compton scattering and photoelectric absorption [ 23 ]. In a photoelectric absorption, the whole energy of the gamma photon is transfer to the electron. While, in a Compton scattering, the gamma photon transfer a fraction of its energy to the electron, generating a free electron-hole pair. The new trajectory of the gamma photon changes an angle proportional to the amount of transferred energy [ 24 ]. Since the gamma photon can suffer several Compton scatters before undergo in photoelectric interaction, the event energy is distributed across the crystal. When this happens, it is very difficult to estimate the entrance point of the gamma photon and, therefore, to reconstruct the LOR, as figure 1.3-(c) illustrates. To overcome this limitation, new architectures of scanners are being proposed. For instance, in [ 23 ], the LOR is reconstructed 8 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1.3. Scintillation Phenomena and Light Propagation Table 1.1: Properties of common scintillator crystal used in medical and high energy physic applications [2, 3, 4]. NaI:Tl CsI:Tl BGO PWO LSO:Ce Density (g/cm3) 3.67 4.51 7.13 8.3 7.4 Light yield (photons/MeV) 38000 68000 8200 300 27000 Energy resolution (%) 7.4 7.9 10.8 75 9.1 Time constant (ns) 245 1220 300 10 40 30 Emission peak (nm) 410 550 480 420 420 Refractive index (-) 1.85 1.79 2.15 2.2 1.82 Photodetector Optical grease Scintillator Absortive coating n2 n1 n1>n2 h r Absorption Reflection Cone cross-section r Ain DOI Figure 1.5: Photoelectric event and light propagation phenomena in a detector block composed of a scintillator crystal, an absorptive coating, an optical coupling medium and a photodetector. If n1>n2 , total internal reflection occurs and the light profile over the sensor can be simplified to a cone shape with radius rand height h. taking into account also the information from Compton interactions, thanks to a multi-layer structure. Once the optical photons have been created inside the crystal, the transmission, refraction and reflection become the most important phenomena for the designer, since they shape the light distribution over the photodetector. Monolithic crystal are preferred over pixelated crystals for several reasons. First of all, as figure 1.5 illustrates, with monolithic crystals, the spatial distribution of light during the absorption of the gamma photon can be sampled and studied. This allows to reconstruct and estimate the position where optical photons have been generated [ 25 , 26 ]. Generally, this is done by calculating depth of interaction (DOI). In order to increase the light extraction, the crystals usually have a large surface coupled to the photodetector and small thickness, i.e., 10×50×50mm3[27]. Additionally, it is evident that the number of reflections and absorptions inside the crystal must be minimized to maintain the spatial distribution of light. Otherwise, the information contained in the light distribution is loose. 9 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1. INTRODUCTION TO SIPM SENSORS FOR MEDICAL APPLICATIONS In this sense, scintillators are transparent, with transmission coefficient close to 80% [ 22 ], respect to their emission spectrum. However, this may not be the case for ˇ Cerenkov photons whose spectrum is close to the ultraviolet. For these wavelengths the transmission coefficient is small and ˇ Cerenkov photons are mostly absorbed by the crystal. As figure 1.5 represents, the interface between the crystal and the photodetector is composed of optical coupling, generally optical grease. If the refractive index of the scintillator is higher than the refractive index of the optical coupling, total internal reflection occurs. This phenomena imposes a critical angle, from which each incident photon is reflected. This critical angle is given by the Snell’s law: θc=arcsinµn1 n2¶(1.5) where θc is the critical angle, n1 is the refractive index of the scintillator and n2 is the refractive index of the optical coupling. This angle limits the amount of photons reaching the sensor surface. For example, the refractive index of LSO is 1.82 and, typically, optical grease has a refractive index of 1.5 , this leads to a critical angle of 56.44° . In order to improve light extraction, some methods proposed the use of photonic crystals at the surface of the crystal. They act as a matching impedance between the scintillator and the coupling medium [ 28 , 29 , 30 ]. The critical angle provides useful information about the light shape over the sensor and its magnitude. In a conventional set-up, like the one of figure 1.5, the amount of optical photons hitting the photodetector can be estimated. The worst case scenario is given by photoelectric events close to the detector surface, because it brightness can saturate the photodetector if it is not properly designed. Considering that photoemission is isotropic, the solid angle associated to the critical angle from (1.5) is: Ω=4πsin2µθc 2¶(1.6) where Ω is the solid angle of the cone with its apex angle of 2 θc and its basis at the detector surface, see figure 1.5. The amount of photons leaving the crystal, without considering black reflections, can be estimated by the fraction of the generated photons during the scintillation and the solid angle from (1.6): Pout =Ptotal Ω 4π=LY E sin2µθc 2¶(1.7) where Pout is the number of photons leaving the crystal, Ptotal corresponds to the total number of photons generated during the scintillation, Ω is the solid angle between the scintillator and the optical coupling, 4 π is the total number of steradians of a sphere, LY is the light yield of the scintillator, E is the energy of the gamma photon. From expression (1.7) , if the thickness of the optical grease is neglected, the maximum density of optical photons per area can be calculated as: 10 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1.4. Photodetector Hq=Pout Ain =LY E π·sin(θc/2) tan(θc)h¸2 (1.8) where Hq is the cumulative optical photons per area, Ain is the incidence area of the sensor, h is the distance between the recombination center and the crystal surface. Considering an interface between LSO crystal ( LY =27000photons/MeV and n= 1 . 82) and optical grease ( n= 1 . 5); a photoelectric interaction of 511keV with a distance h=1mm , the critical angle is θc=56.44° and the maximum density of optical photons per area is: Hq=27000·0.511 π·sin(56.44/2) tan(56.44)¸2 ≈450photons/mm2(1.9) This upper bound value of Hq=450photons/mm2 only takes into account the forward emission. However, it provides an idea of the maximum magnitude of input light and shows that the sensor will work in single-photon regime, even when the gamma photon deposits all its energy close to the sensor. 1.4 Photodetector Once the optical photons have left the crystal, they must be detected and translated into electrical signals that can be processed. To do so, the first PET scanners rely on photomultiplier tube (PMT)s as a photodetectors. The PMT have their origin in the vacuum tubes developed by H. Iams and B. Salzberg in 1935 [ 31 ]. The figure 1.6 represents the working principle of conventional PMT. An incident photon with enough energy hit the photocathode and, thanks to the photoelectric effect, a free electron is produced. Next, this electron is accelerated toward the first dynode, due to the high electric field between the photocathode and the dynode. Then, the collision with the first dynode generates more electrons, that at the same time are attracted to the second dynodes. This multiplication process finishes at the anode where the signal is sampled by the front-end electronics. Thanks to their high gain, linearity, robustness, radiation hardness, fast response and low noise, these devices were the best option for a broad range of applications, not only single-photon detection, since their adoption in the early 1940 s. Usually, the main drawbacks of these devices are associated with their high bias voltage, power consumption and non-compatibility with magnetic fields. During the last decades, the silicon photomultiplier (SiPM) has rose as a solid state alternative to substitute PMTs in many applications. As figure 1.7 represents, SiPM are composed of an array of SPADs with quenching circuitry connected in parallel and biased on the Geiger mode, i.e., reversed biased above the breakdown voltage. Broadly speaking, the working principle of these devices can be summarize as follows: an incident photon with enough energy is absorbed at the diode depletion region and, thanks to the photoelectric effect, 11 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1. INTRODUCTION TO SIPM SENSORS FOR MEDICAL APPLICATIONS R RR R R R R R R RL Photocathode Scintillator Anode Dynodes e- -Bias voltage Vout Figure 1.6: Photomultiplier tube working principle. The photoelectric effect generates a electron at the photocathode. The electrons are drifted by the electric field the the dynodes, where more electrons are emitted. a free electron-hole pair is produced. These free charge carriers are accelerated by the high electric field in the depletion region. The collisions of these charge carriers with the crystal lattice release more electron-hole pairs in a process called impact ionization [ 32 , 33 ]. This sharp current rise, also called avalanche, is detected by the front-end electronics. Another function of the front-end electronics is to limit the amount of current flowing through the SPAD, quench it and reset the device to its original bias condition, ready for another detection. Compared to PMT, the SiPM has a smaller power consumption, bias voltage and it is compatible with magnetic fields and more compact, allowing higher spatial resolution. The main drawbacks of these devices are their high noise and low radiation hardness. In figure 1.7-(a) the schematic of an analog SiPM is shown, each one of the micro-cells of this device is composed of a SPAD and a passive quenching resistor. The output of an analog SiPM provides a current proportional to the number of detected photons. In order to optimize the quantum efficiency (QE), reduce noise and increase fill factor, analog SiPMs are usually fabricated into custom process. On the contrary, digital SiPMs are fabricated with CMOS or CMOS image sensor (CIS) technologies. As figure 1.7-(b) represents, the main advantage of this approach is the flexibility that the designer have to implement processing logic close to the focal plane of the SiPM, i.e. to determine the photons arrival time with a TDC. This flexibility comes at the expense of a degradation of QE, noise and fill factor. Before evaluating and comparing the performance of the state of the art, several parameters and figure of merit (FOM) must be defined briefly: • Photon detection probability (PDP) is the ratio between the detected photons and the incident photons without considering losses due to dead area. It depends on the technology, incident wavelength, the SPAD structure and the bias voltage. 12 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1.4. Photodetector (a) (b) QRC SPAD Bias voltage ... OR Read out Rquench SPAD Bias voltage Vout RL Figure 1.7: (a) Analog silicon photomultiplier (SiPM) and (b) digital SiPM with common read out. • Fill factor (FF) is the ratio between the photo-sensitive area and the dead area of the device, micro-cell, pixel or chip. The device fill factor is limited by the technology, since every SPAD requires a surrounding structure, guard ring, to confine the high electric fields. Without a proper guard ring the functionality of the SPADs is not guaranteed. • Dark count rate (DCR) is the number of avalanches counted when the device is in complete darkness. This source of noise is uncorrelated with other sources and it is function of temperature and bias voltage. • Cross-talk is the probability that one SPAD provokes avalanches in neighboring SPADs. A cross-talk event can be trigger by diffused charge carriers or photon generated by avalanche photo-emission. • After-pulsing is the probability that a secondary avalanche is triggered due to the delayed release of charge carriers from deep level traps, like impurities and defects in the silicon lattice. These deep level traps are filled during a previous avalanches, and released sometime after that. • Coincidence time resolution (CTR) is the time accuracy of two detectors working in coincidence. In a PET scanner, it takes into account the contribution of all the sources of uncertainty or jitter. From the system clock jitter to the SPAD and TDC jitter. The state of the art of SiPMs for ToF-PET is summarized in table 1.2. It can be observed that custom technologies provide better performance in terms of PDP and DCR. However, they require additional circuit to estimate the photons arrival time. Despite having worst performance, digital technologies allow the 13 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1. INTRODUCTION TO SIPM SENSORS FOR MEDICAL APPLICATIONS Table 1.2: State of the art of Silicon Photomultiplier (SiPM). [37] [38, 39] [40, 41] [42, 43] [44] [45, 46] Architecture Analog Analog Analog Digital Digital Digital Technology (nm) Custom Custom Custom 180 Custom 130 CIS 350 HV SiPM pitch (mm) 3 3 4 4 0.59 0.8 SPAD size (µm2) 2500 1225 2500 3780 210 1200 SPAD/SiPM 3531 5676 6400 3200 720 416 PDP (%) 68 51 76 54 45 32 FF (%) 74 75 42 74 43 57 DCR (Hz/µm2) - 0.05 0.2 0.15 65 50 Cross-talk (%) 7 8 - 7 2 1.8 After-pulsing (%) - 0.25 - 0.1 0 - CTR (ps) 180* 220* 200* 325** 400* 400* * Laboratory set-up; ** PET-TOF scanner. integration of on-chip processing logic, like event detection, TDC and communication logic. Nevertheless, the area occupied by these logic has a negative impact on the FF. Also, the DCR of a digital SiPM is two order of magnitude higher than that of their analog counterpart. Apart from ToF-PET, some other applications, like fluorescence-lifetime imaging microscopy (FLIM) [ 34 ] and light detection and ranging (LiDAR) [ 35 ], also benefit from on chip processing logic. However, it seems evident that the current trend is to implement the designs into 3D-stacked technologies [ 35 , 36 ]. Unfortunately, nowadays this kind of processes are not widely available. To the best of the author knowledge, the honors of bringing together the best of analog and digital SiPMs is not yet claimed. 1.5 Case Study and Desired Features (Thesis Goals) As it has been shown in previous sections, PET scanners can improve their image quality via SNR improvement applying ToF. The technology scaling that has been pushing the microelectronics industry to its limits year after year has improved the working frequency, power consumption and occupation area of consumer electronics. Almost every circuits in a digital SiPM benefits from this trend, specially the TDC in terms of temporal resolution. However, technology scaling does not always improves SiPM performance. The SPADs are the most affected devices when they are implemented in small technology nodes. This is because they suffer from low yield, due to the high doping concentration and non-spatial uniformity of the doping layers used to implement the device. To slightly alleviate this, CIS technologies are good alternatives. Although they have not been completely optimized for SPADs, these technologies contain less impurities and defects than standard CMOS. Also, they offer some properties attractive for SiPMs, like anti-reflective coating. With this in mind, a 110nm CIS 14 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 1.6. Thesis Organization technology has been chosen to design the digital SiPM for ToF-PET. 3D-stacked technologies have not been tested because of their high cost and because there is still room at the bottom to exploit the performance of SiPM in CMOS and CIS technologies. The main goal of this thesis is to design a digital SiPM able to perform three main functions: to detect and count photons, to measure their arrival time and to process the scintillation event. Single-photon detection can be performed in CIS technologies with SPADs. However, the integration of such full custom devices is not trivial, because it requires a careful design and a deep knowledge of the process. The technology also allows the integration of active quenching and recharge circuit (AQRC) and digital logic to count the pulses generated by the avalanches. Moreover, time measurements can be done with a TDC. Since time resolution depend on the TDC architecture, it is necessary to study which architecture fits better this application. Specifically, a small area footprint is required to reduce dead area and increase fill factor. Also, a small conversion time is preferable to reduce temporal blind spots. Furthermore, power consumption should be also low to reduce the variations associated to thermal gradients. Additionally, time resolution should be small enough for not to be the dominant source of uncertainty. Also, an event processing finite state machine (FSM) must be flexible enough to study different trigger logic and threshold alternatives. For the proposed prototype, such flexibility can be achieved by reconfigurable logic, preferably a field-programmable gate array (FPGA). Once the three main blocks and the rest of auxiliary logic are designed, the next step is to start the architectural exploration of the SiPM. This optimization process relies on the fact that each photon carries valuable information about its origin, therefore, photon detection and counting must be maximize. The architectural exploration provides an insight into the design space of these sensors, and helps to identify optimum points. This information helps the designer to justify their election and make the design more straightforward. The final step consist in the experimental characterization of the designed blocks and verification of the design approach. 1.6 Thesis Organization Chapter 2 explains the design steps of two full custom SPADs and its AQRC in a CIS technology. In chapter 3, some TDC architectures are discussed and the design of a TDC based on VCRO is described. The architectural exploration of the SiPM is carried out in chapter 4 based on analytical methods. In chapter 5, the characterization of the SiPM is carried out. Chapter 6 discuss the main results and limitations of the design. Based on the experience gained during the design and characterization of the first prototype, the future work is described. Finally, chapter 7 provides the conclusions of this thesis. 15 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2. SPAD AND FRONT-END ELECTRONICS IN CMOS TECHNOLOGIES POLY STI n+ nw3v3 pw3v3 p+ SiO2 Retrograde deep nw Depletion region POLY STI n+ N-well P-well P-sub p+ diffusion Anode Deep N-well Depletion region Cathode GR POLY STI n+ nw3v3 pw3v3 p+ SiO2 Retrograde deep nw Depletion region POLY STI p+ P-well N-well P-sub n+ diffusion Cathode Deep N-well Depletion region Anode GR (a) (b) Figure 2.4: SPAD cross-section with deep junction: (a) red-sensitive structure and (b) near infrared sensitive structure. tion of layers, the designers choose the SPAD structure that provides the best performance for their applications. A common way to classify these structures is using the junction depth, because a large number of SPAD parameters depends on it, directly or indirectly. For example, as in any other photodiode, the junction depth affects the wavelength at which the peak of sensitivity is found. In the following subsections, the benefits and drawbacks of SPADs implemented with superficial junctions [ 48 , 54 , 55 , 56 ] (see figure 2.3) and deep junctions [48, 49, 54] (see figure 2.4) are discussed. 2.2.1 Noise Noise in SPADs consists of spurious avalanches produced by charge carriers whose origin is different from photoelectric effect. Noise sources can be divided into uncorrelated and correlated. The dark count rate (DCR) groups together all uncorrelated noise sources. They are manly the result of thermal trap assisted carriers generated, by SRH, and carriers jumping from valence to conduction band, i.e. band-to-band tunneling. These phenomena are represented in figure 2.5 [ 57 ]. Although purely thermal carriers (no trap is involved) can also be generated by SRH, this noise source is less common in indirect band gap semiconductors, like silicon [ 46 ]. Generally, superficial p-n junction are composed of diffusion and well layers as indicated in figure 2.3. Since these structures have higher doping concentration, they are expected to suffer more DCR than 22 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2.2. SPAD Structures Depletion RegionP N EC EV - + Trap + Thermal After-pulsing - + (a) (b) (c) (d) (e) Depletion RegionP N EC EV - + - + Hole Band-to-band Electron Figure 2.5: SPAD noise sources: (a) thermal trap assisted Shockley-Read-Hall generation, (b) thermal Shockley-Read-Hall generation, (c) carrier release from trap (afterpulsing), (d) band-to-band tunneling and (e) trap assisted band-to-band tunneling. the deeper junctions composed of less doped layers, like those represented in figure 2.4. The main cause for this is the rise of band-to-band tunneling contribution due to a thinner depletion region [57]. On the other hand, correlated noise sources produce secondary avalanches after a primary avalanche has occurred. They can be classified in after-pulsing and cross-talk. An after-pulse is produced when a free charge carrier is captured by a deep-level trap during an avalanche and it is released some time later, see figure 2.5. These traps are impurities or defects in the silicon lattice. The after-pulsing probability can be calculated as [46]: Pap (t)=PtPav exp(−t/τt) τt (2.4) where Pap ( t ) is the after-pulsing probability at time t after the primary avalanche; Pt is the trap capture probability, it depends on the density of impurities in the lattice and the current flux during avalanche; Pav is the probability that a free charge carrier triggers an avalanche; and τt is the trap lifetime [ 46 ]. From the designer point of view, there are several ways to reduce after-pulsing. The first step is to choose a clean technology in order to reduce the number of impurities and defects that act as traps. Next, some SPAD structures suffer from more after-pulsing than others. For example, when shallow trench isolation (STI) are used as a guard ring, the interface states at silicon-SiO 2 boundary, act as traps [ 58 , 59 , 60 ]. Also, the maximum current during the avalanche can be limited to reduce the amount of trapped charges. Finally, the dead time of the SPAD can be adjusted to be larger than the trap lifetime. Doing so, a significant fraction of traps are discharged before the SPAD becomes sensitive again. Cross-talk is the probability that one SPAD provokes avalanches in any of the neighboring SPADs as figure 2.6 illustrates. A cross-talk event can be 23 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2. SPAD AND FRONT-END ELECTRONICS IN CMOS TECHNOLOGIES POLY STI n+ nw3v3 pw3v3 p+ SiO2 Retrograde deep nw Depletion region Photon - + - + - + - + + Optical cross-talk Electric cross-talk - + - + + Figure 2.6: SPAD electrical and optical cross-talk. initiated by diffused charge carriers or photons generated by avalanche photoemission [ 52 , 61 ] traveling through the silicon bulk to the active area of a different SPAD [ 47 , 46 ]. For these reasons, opaque and isolating guard rings are required. Unfortunately, sometimes this means to increase the guard ring area and, hence, to reduce the fill factor. The junction depth is especially relevant in this aspect, because superficial junctions are better confined by their guard rings, which are more effective as a physical barrier to surround the active area and to prevent particles generated during the avalanche to travel to other SPAD’s active area. As reported in [ 54 ], SPADs with deep junction are less isolated between each other, because charge carriers are not so well confined. 2.2.2 Photon Detection Probability The photon detection probability (PDP) is the ratio between the detected and incident photons for a normalized area. PDP can be calculated as: PDP =QE (λ)·Pav (Vex)(2.5) where QE ( λ ) is the quantum efficiency, i.e. the probability that a photon of a given wavelength, λ , generates a free electron-hole pair; and Pav (Vex) is the probability that a free charge carrier triggers an avalanche, which is a function of the excess voltage (Vex ) . Practically, this means that deeper junctions are more sensitive to longer wavelength, because the charge carriers generated by them are closer to the active area. This allows the designers to choose the structure that provides the PDP peak closer to the applications needs, selecting the more appropriate junction depth. This metric is more useful than photon detection efficiency (PDE) at this level, because it focuses on the performance of the technology and junction, not in the fill factor of the diode and the diode array. As it is expected, SPADs with superficial junctions, like the ones of figure 2.3- (b,c), are preferred in applications where higher sensitivity to blue is needed [ 43 , 62 ]. On contrary, the junctions represented in figure 2.4 are a common choice when high sensitivity to red or near-infrared is required [49, 62]. 2.2.3 Jitter Jitter in SPADs is related with the seeding point of the avalanche, its horizontal propagation and the active area of the device. As it was described in sec- 24 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2.3. Implemented SPAD tion 2.1, the seeding point is the place where the incident photon creates the first electron-hole pair that initiates the avalanche. After that, the avalanche begins to spread to the rest of the active area and the current rises [ 50 , 52 ]. Since the avalanche current depends directly on the avalanche propagation, its rise time is also affected by the stochastic nature of these processes. Therefore, if the avalanche is detected by the rising edge of the avalanche current, the jitter can be defined as the standard deviation, or FWHM, of the avalanche propagation time. It is important to notice that the size of the depletion region, both the total active area and the width of the depletion region itself (measured in a direction that is perpendicular to the junction), has an impact in the jitter. This is because the avalanche propagation time depends on the size of the depletion region. Statistical variations appear in the number of the emitted photons, so they have an impact in the jitter [ 52 ]. As of today, the smallest jitter reported corresponds to shallow diffusion/well junctions and small SPAD areas [48, 63, 56]. 2.2.4 Premature Edge Breakdown Premature edge breakdown (PEB) occurs in areas where the electric field is locally higher than in the rest of the junction. This high electric field entails a lower breakdown voltage than in the active area, because the breakdown condition represented in (2.1) is meet before in these regions. The areas more prone to this kind of failure are located where the doping profile has strong variations, like the periphery of diffusion, see figure 2.3-(a), or the corners of a square-shape SPAD [ 48 ]. As a result, the avalanches are triggered at the edges, rather than at the active area. This leads to a SPAD that is insensitive to incident light, since the active area never reaches a proper bias. PEB can be avoided with a properly designed guard ring. Guard rings are implemented with layers that are less doped than the ones of the active area, surrounding it, in order to confine its high electric field. Generally, the used layers are P-wells or retrograde Deep N-wells, see figure 2.3 and 2.4. Although STI are effective to avoid PEB, the direct contact between active area and STI leads to a noisy device, due to the interface states at silicon-SiO 2 boundary [ 59 ]. PEB also affects diodes with sharp corners, for that reason, designers prefer circular shapes, or at least squared with round corners, rather than squared [ 48 ]. 2.3 Implemented SPAD In orderto experimentally validate the technology, two differentSPAD structures have been designed: a P-well/Deep N-well diode and P+/N-well diode. From now on PW3V3/DNW and PP/NW3V3, respectively. As figure 2.7-(a,b) illustrates, both structures share some common features. The deep N-well cathode can be shared among the neighboring SPADs to increase the fill factor. The poly-silicon layer is employed to form the P-substrate guard ring above the retrograde deep 25 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2. SPAD AND FRONT-END ELECTRONICS IN CMOS TECHNOLOGIES Cathode n+ Anode p+ r x GR (c) POLY A' A O b POLY STI n+ nw3v3 p+ SiO2 Depletion region STI n+ N-well 3V3 P-well 3V3 P-Sub p+ diffusion Anode Retrograde Deep NW Cathode GR + r (a) A' O Depletion Region x 2 POLY POLY STI n+ nw3v3 p+ SiO2 Depletion region STI n+ N-well 3V3 N-well 3V3 P-Sub p+ diffusion Anode Deep N-well Cathode (b) A' O Depletion region POLY p+ mask Figure 2.7: (a) PW3V3/DNW SPAD cross-section (b) PP/NW3V3 SPAD cross-section and (c) SPAD front view. Where r =5µm , x =5µm , GR =1µm , b =21.2µm , active area =200µm2. N-well. Moreover, poly-silicon is used to prevent the formation of STI close to the depletion region. The technology provides both 1.2V and 3.3V wells, but it is expected that 3.3V wells have lower and uniform doping than 1.2V , because of technological scaling [ 64 ]. The effects of doping non-uniformity also affect superficial junction composed highly doped layers, like p+/n+ diffusion. It is worth mentioning that the PP/NW3V3 structure implemented will suffer from PEB. As seen in figure 2.7-(b), the p+ diffusion mask was extended to enclose the N-well as figure 2.3-(c) shows. However, this extended diffusion below the poly-silicon is not fabricated as in CMOS processes the gate self-aligns [ 33 ], therefore the poly-silicon acts as a stopping layer that prevents the formation of diffusion below it beyond a small overlapping. The effect of this error will be discussed in chapter 5. It is expected then that PW3V3/DNW diode performs better in terms of DCR and PDP at long wavelength than PP/NW3V3. On the contrary, PP/NW3V3 structure may have smaller jitter, cross-talk and more PDP at short wavelength than PW3V3/DNW [ 60 , 54 , 48 ]. Comparing PW3V3/DNW against PP/NW3V3 structure, the main advantages should be less noise, more uniformity among devices and, therefore, higher yield. Figure 2.7-(c) represents the layout of a SPAD parametric cell. A squared shape with round corners has higher fill factor than the circle-shaped and lower noise than square-shaped SPADs with straight corners. As for the dimensions, a small footprint will keep the DCR small, while the SPAD FF is close to 40 %: 26 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2.4. Quenching and Recharge Circuit K A RBD CKA CKB K A VBD CAB Event Figure 2.8: SPAD circuit model. FFspad =Aaspad Aspad =x2+4·r·x+r2π b2(2.6) where Aaspad is the active area of the SPAD, Aspad is the total area of the SPAD, x is the size of the straight segment of the SPAD size, r is the corner radius, b=x+ 2( GR +r+b0 ) is the side of the complete structure and b0 is the minimum size of n+ diffusion given by design rules of the technology, that in the example is b0=2.1µm . Following the guidelines reported in [ 48 , 54 ], these parameters can take values like r=5µm and GR =1µm . Expression (2.6) can be solved for a SPAD fill factor around 40% rendering x≈5µm. 2.4 Quenching and Recharge Circuit Once the SPAD structure is selected and the dimensions defined, the next step is the design of the electronic front-end for the diode. The main component is the quenching and recharge circuit (QRC). The assembly of a SPAD and its QRC is usually known as a micro-cell. As it will be seen in chapter 5, the design of this circuit is critical, because the performance of the whole system depends on the work done at this stage. A bad design can mean anything from erratic operation and excessive power consumption to irrecoverable device damage. For this reason, it is very important to have a basic understanding of the SPAD working principle and to have an accurate model to perform simulations. It is relatively easy to find examples of both passive [ 65 , 40 , 66 ] and active [ 67 , 68 , 69 , 70 , 71 ] quenching and recharge circuit sizing. The first step, before starting the design of the QRC, is the characterization of the SPAD and the extraction of its parameters. The basic model represented in figure 2.8 is enough to study the dynamic behavior of a SPADs, a more complex and realistic model can be find in [ 72 ]. This basic model emulates the onset of 27 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2. SPAD AND FRONT-END ELECTRONICS IN CMOS TECHNOLOGIES Table 2.1: Usual magnitudes for the SPAD circuit model of figure 2.8. Parameter Value Unit VBD 10–40 V RBD 100–1000 Ω CK A 100–1000 fF CAB 1–10 fF CK B 1–2 pF the avalanche with closing of the switch labeled as “Event”. At that moment, the current starts flowing from cathode (K) to anode (A), discharging CK A , until the voltage across the diode terminals reaches the breakdown voltage, VBD . With the avalanche quenched, the circuit starts the recharge until the bias voltage is reached. As it is evident, the circuit parameter values are very important, since they determine, along with the QRC, the time constant of the avalanche quenching and of the diode recharge, and the current magnitude of the avalanche. In the best case scenario, the designers have experimental data from which they can obtain all the required values. However, sometimes this ideal case may not be true. Without experimental measurements, designers can make use of the library cells provided by the foundry. In the worst case scenario, designers must use the reported values by other groups in order to have a SPAD model whose parameter values are in the proper order of magnitude. The common values of these parameters in CMOS technologies are summarized in table 2.1 [ 65 , 73 ]. From now on, the following values are used: VBD =18V , RBD =300Ω , CK A = 200fF , CAB =10fF and CK B =1pF . Some of these values have been extracted from the models provided by the foundry, while others have been obtained from the bibliography. 2.4.1 Passive Quenching and Recharge Circuit The design of a PQRC consist in determining the size of the quenching resistor. Firstly, the value of the resistance is chosen to guarantee that the steady-state current flowing through the SPAD is below the self-quenching value, Iquench . Below this quenching current, the avalanche is not longer self-sustained and, eventually, it will be quenched, see figure 2.9. Although the value of this current depends on the technology and the junction, reported values area around 10 – 100µA [ 65 , 68 , 53 ]. Even though the steady-state current through the SPAD is below the self-quenching value, the current peak associated to the discharge of CK A through RBD could be order of magnitude higher. As it is shown in figure 2.9-(a), if RQÀRBD and the switch is closed, the current flowing through RQ in steady-state is given by (2.7) . This approach is equivalent to find the operating point of any circuit. Hence, RQ should has a value around 60 – 600kΩ 28 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2.4. Quenching and Recharge Circuit RBD CKA CKB Event SPAD VBD CAB VK =VBD+Vex RQ VA ISPAD (a) (b) VA τQ (CKB + CKA)RBD τR (CKB + CKA)RQ VK-VA<VBD t ISPAD Iquench t Vex /RQ < Iquench Vex /RQ > Iquench Figure 2.9: SPAD with passive quenching and recharge circuit (PQRC): (a) circuit schematic and (b) dynamic response, not into scale. for Vex =6V. ISPAD ≈Vex RQ (2.7) Secondly, it is important to estimate the quenching and recharge times of the SPAD. Analyzing the circuit in figure 2.9-(a), when the switch is closed and RQÀRBD, the quenching time constant is [65]: τQ=(CK A +CAB )RQRBD RQ+RBD ≈(CK A +CAB )RBD (2.8) Finally, when the switch is open again, the recharge time constant can be calculated as: τR=(CK A +CAB )RQ(2.9) From (2.8) and (2.9) it can be observed that the recharge time is much longer than the quenching time. Furthermore, the bandwidth of the circuit, i.e. maximum number of avalanches per unit of time that can be triggered without saturating the SPAD output, is function of RQ , as expression (2.10) shows. At first glance, this could be compensated reducing Vex , however, this has a negative impact on the PDP and jitter. BW ∝1 τR+τQ≈1 (CK A +CK B )RQ=ISPAD (CK A +CK B )Vex (2.10) 29 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2. SPAD AND FRONT-END ELECTRONICS IN CMOS TECHNOLOGIES VBD+Vex Vdd td VA MNQ MPQ MNR - - - Vth VQ VR t VA PQRC VK-VA<VBD AQRC td Vdd (a) (b) Figure 2.10: SPAD with active quenching and recharge circuit (AQRC): (a) circuit schematic and (b) dynamic response. 2.4.2 Active Quenching and Recharge Circuit The working principle of an active quenching and recharge circuit is relatively simple as figure 2.10 illustrates. When the avalanche is triggered, the anode voltage ( VA ) rises above the threshold voltage ( Vth ). Then, transistor MNQ is turned off and MPQ is turned on, pulling-up the anode voltage to Vdd and, hence, forcing a voltage across SPAD terminals smaller than the breakdown. Next, after delay ( td ), the transistor NR is turned on, pulling the anode voltage down to ground. This resets the device to its initial operation point, waiting for another avalanche. As figure 2.10-(b) represents, the principal benefit of AQRC over PQRC is the control of the recharge time. This allows to increase the bandwidth without having a negative impact on the quenching of the avalanche. Furthermore, since the device spends more time out of Geiger mode and the deep leveltraps have more time to be discharged, the probability of after-pulsing is reduced. The comparator and the delay element can be implemented in different ways depending on the specifications, from a few inverters as in [ 74 , 75 ] to an operational amplifier [ 65 , 76 ]. Nowadays, research in this field is very active and mainly focused on the reduction of the footprint to increase fill factor. For this reason, the following analysis will be qualitative and oriented to the design of essential transistors, MNQ ,MPQ and MNR. Different design approaches, sometimes diametrically opposed, can be found in the bibliography. For example, in the sizing of the quenching transistor. For example, in [ 67 ], transistor MNQ is sized to provide a high output resistance of 1.2MΩ . On the contrary, other authors employ much more conductive transistors to better detect the avalanche current peaks [ 77 ]. This approach implies that the avalanche can only be quenched after the output of the comparator goes to zero and transistor MNQ is switched off. Using this method, considering 30 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 2.4. Quenching and Recharge Circuit ISPAD =0.5 – 1mA [ 77 ] and Vex =Vdd =3.3V , the size of MNQ can be estimated with a quadratic model: Vex ISPAD =1 RQ=1 W L µnCox 2(Vdd −Vthn)2λ⇒ W=2ISPAD L µnCoxVex(Vdd −Vthn)2λ (2.11) where RQ is the output resistance of NNQ transistor, µn=0.03695m2s/V , Vthn= 0.5V , λ=0.02V−1 and Cox =10×10−3F/m2 . If the minimum length is used ( Lmin =0.36µm ), the transistor width is W=1.5 – 3µm . On the contrary, the approach presented in [ 67 , 70 ] would yield a completely different result, that is, a transistor longer than wider. Considering (2.11) , ISPAD =10 – 200µA and Wmin =0.6µm , the transistor length is L=0.6 – 5.7µm . As it will be seen in chapter 5, the selection of the first method can explain the excessive power consumption and system instability. Another point where special care must be taken is during the design of MNR and MPQ , to avoid instabilities related to a positive feedback, like oscillations or VA stuck at Vdd . If the gate of MPQ is simply driven by the comparator, MNR must be more conductive than MPQ , to pull-down the anode voltage to ground. To avoid any short circuit current between Vdd and ground when both transistors are active, the straightforward solution is to add a second PMOS transistor in series with MPQ and connect its gate to VR . However, this last solution may not be attractive for arrayed devices, because it reduces the fill factor by increasing the occupation area. 2.4.3 Passive Quenching Active Recharge Circuit In the bibliography, some alternatives halfway between AQRC and PQRC are proposed to provide the simplicity of a passive quenching and the bandwidth of an active recharge [ 53 ]. Moreover, while the excess voltage is limited to Vdd in an AQRC architecture, the excess voltage in a passive quenching and active recharge circuit (PQARC) is limited by the transistor maximum operation voltages. For example, the PQARC architecture shown in figure 2.11-(a) is able to work with an excess voltage above Vdd . Thanks to the cascode transistor MNC that reduces the voltage across the quenching transistor to less than the maximum VGS and VDS allowed by the technology [ 78 ]. However, the maximum excess voltage is limited by the breakdown of the drain-bulk junction of MNC . The operation principle of this topology is shown in figure 2.11-(b) and it can be divided into tree main parts: quenching, dead time and recharge. Once the avalanche is triggered, the current rises until it reaches the value set by the current mirror and the anode voltage reaches a value close to the excess voltage. This quenches the avalanche. Next, the anode voltage starts discharging 31 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN (a) (b) td D Q Q0 td D Q Q1 td D Q Q2 td D Q QN-1 Tstart Tstop 1 1 1 0 td D Q Q0 td D Q Q1 td D Q Q2 Counter Tstart Tstop QN-1 Q3 ... Figure 3.2: Simplified block diagram of digital TDC architectures: (a) delay line, (b) VCRO. D Q Q0D Q Q1D Q Q2D Q QN-1 Tstart Tstop 1 1 1 0 Figure 3.3: Simplified block diagram of Vernier delay line TDC. D Q Q0 0 1tdr 2 1 2 tdr 1tdf 2 tdf 1D Q Q1 1 1 1 2 D Q QN-1 N-1 1 Ts 1 1 0 Figure 3.4: Simplified block diagram of pulse shrinking TDC. agated through a delay stage its width is reduced a value equal to the time resolution [82]: Tshr res =(tdr 2−td f 2)−(tdr 1−td f 1) (3.3) where Tshr res is the resolution time, tdr 2 is the rising edge delay of stage 2, td f 2 38 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.1. TDC Architectures Ts N-bit Bus QLSB N-bit memory ... N-1 ... 1 ... 0... O0O1ON-1 QMSB Counter Vdd Ts ON-1 ON-4 ON-6 ON-2 Ts (a) (b) Figure 3.5: (a) Simplified block diagram of multi-path TDC and (b) schematic of delay stage. Ts Tout td -td C C C C gm gm gm gm td td Tstart Tstop TsTout (a) (b) Figure 3.6: (a) Simplified block diagram of time amplification TDC and (b) transfer characteristic of time amplification. is the falling edge delay of stage 2, tdr 1 is the rising edge delay of stage 1 and td f 1 is the falling edge delay of stage 1. The conversion finishes when the pulse vanishes in the delay path, because the signal is below the noise margin of the inverters. This makes the architecture sensitive to PVT variations [82]. Multi-path gated ring oscillator architecture is shown in figure 3.5-(a). Multipath architectures are implemented with delay stages with multiple inputs, each one connected to different delayed phases, see figure 3.5-(b). With this, a reduction of the propagation delay per stage is achieved [ 83 ]. However, the design of such oscillators is not trivial, since several oscillation frequencies, phase shifts and phase noises are possible because of the existence of different oscillation modes [ 84 ]. A careful design must be carried out to avoid unwanted oscillation modes. As the ring oscillator architecture shown before, this structure also uses the oscillator phases and a counter to obtain the fine and the coarse conversion, respectively. In time amplification architectures, the width of narrow pulses is increased thanks to the metastability of positive feedback comparators, see figure 3.6-(a). 39 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN (a) (b) + - + - V-1 V-2 V-3 V-in V-out V+1 V+2 V+3 V+in V+out V-1 tdV-out V-in V-1 V-2 V-3 t V Figure 3.7: (a) Delay stage of local passive interpolation TDC and (b) interpolated signals between input and output edges. The small-signal time amplification is given by [85]: AT=2C gmtd (3.4) where C is the load capacitance of NAND gates, gm is the small-signal transconductance of NAND gates during metastability and td is the delay time that extends the metastability input range. Because of the non-monotonic response of the transfer characteristic, see figure 3.6-(b), the input range must be between ±td . The main drawback of this technique is its limited measuring range and linearity. Consequently, this architecture is commonly used as a part of pipeline or fine-coarse converters [85, 86]. In addition to all these architectures, local passive interpolation architectures are also part of the sub gate-delay family, without having some of their drawbacks like long conversion times or unwanted oscillation modes [ 87 ]. Local passive interpolation architectures are equivalent to delay lines, but each delay stage has a voltage divider between input and output, as figure 3.7-(a) illustrates. This voltage divider creates a copy of the input signal in their internal nodes as figure 3.7-(b) shows. As a result, the voltage interpolation increases the number of signal phases and, hence, the resolution. One of the main drawbacks of this architecture is the power consumption because of the cross current at the delay stage during interpolation [87]. 3.2 Proposed Architecture As it was discussed in the previous section, for a given technology, the selection of the architecture determines the compromise between time resolution, area and power consumption. The TDCs based on VCROs are generally chosen for in-pixel implementation because of several reasons. First of all, as the oscillation frequency is a function of the delay of individual stages of the oscillator, 40 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.3. Study of Delay Stages Encoder Ripple counter Coarse output Fine output Ring oscillator 1 2 N 2N log2(N) Controller ... ... Tstart Tstop Ts VBias Figure 3.8: Simplified block diagram of a voltage controlled ring oscillator (VCRO) time to digital converter (TDC). the time resolution can be controlled by controlling the stage delay, Td . That can be done through, for instance current-starved stages or voltage-controlled transmission gates. The main advantage of voltage-controlled transmission gates is the possibility to adjust the oscillation frequency linearly to a reference value through a control loop, which reduces the effects of PVT variations [ 88 ]. On second place, the small area footprint of this architecture makes it possible to integrate the TDC within a pitch size as small as 50µm×50µm [ 89 ]. Finally, its conversion time is small enough to allow sampling frequencies in the order of tens of megahertz [ 90 ]. These are the main reasons why the VCRO architecture is chosen. Figure 3.8 displays a simplified block diagram of the proposed VCRO TDC. The time interval to be sampled, Ts , is determined by the difference between the rising edges of the start and stop signals, Tstar t and Tstop , respectively. The controller block prevents that any spurious pulse re-triggers the oscillator. The voltage VBias modifies the resolution of the converter by controlling the stage delay. Once the VCRO is stopped, the ripple counter retains the number of oscillations done by the VCRO, constituting the coarse conversion of the sampled time interval. Simultaneously with the rising edge of the stop signal, the internal phases of the VCRO are encoded into additional bits, that provide the fine conversion. Notice that, unlike a single-ended ring oscillator where there must be an odd number of stages, in differential and pseudo-differential ring oscillators, the number of stages can be even. In order to fulfill Barkhausen criteria, however, a wire inversion has to be placed [91]. 3.3 Study of Delay Stages Nowadays, VCROs can be found in a wide range of applications, like ADPLLs for communications [90]; direct ToF estimation for telemetry [92, 93] and high energy physics (HEP) [ 94 ]; and bio-medicine, including FLIM [ 95 ] and PET [ 44 ]. In particular, flash 3D imaging based on direct ToF estimation relies on inpixel TDCs. They need to be compact and power efficient to fit into a small 41 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN pixel pitch. TDC architectures employing pseudo-differential VCROs as time interpolators fulfill these requirements. At this point, the design of the VCRO becomes central. In the following sections, an effective analysis is proposed to optimize the design parameters of the pseudo-differential VCRO to maximize the overall performance of in-pixel TDCs. The main building block of VCROs is the delay cell whichcan be single ended, differential or pseudo-differential. Unlike differential delay cells, single ended and pseudo-differential delay cells achieve rail-to-rail outputs, because they lack the biasing current source. This rail-to-rail output swing features lower jitter due to smaller thermal noise associated with larger slew rates [ 91 , 96 ]. Besides, they do not require any static power which makes them more power efficient. Differential stages with non-saturated outputs provide excellent common mode rejection [ 91 ]. However, they need a bias current to keep the operating point in a linear region, this implies higher power consumption. Pseudo-differential delay cells have worse rejection to supply and ground noise than differential rings, but better than single ended delay cells. Finally, differential and pseudo-differential rings can be built with even or odd number of stages, even rings are useful in clock recovery or phase locked loops when quadrature outputs are needed [ 97 ]. For these reasons, most of the implementations in the literature are based on differential [89] and pseudo-differential rings [98, 99]. Since differential rings with non-saturated outputs work in the linear region, it is almost straightforward to make an estimation of the oscillation frequency based on the transfer function of the oscillator using small-signal analysis. Instead, pseudo-differential oscillators are more difficult to predict because of their strongly non-linear behavior. Despite these non-linearities, it is possible to make a first order approximation and calculate the pole frequency of the stage by a small-signal approach [ 100 ]. This approximation only remains valid while the non-linearities of the output signal are small. This can be achieved choosing the proper number of delay stages, for instance, in a ring with a large number of delay stages, the output is hard saturated (or hard clipped), because it spends a large fraction of the period in the supply rails. However, in a ring with small number of delay stages, the output is soft saturated, since it spends a smaller fraction of the period in the supply rails. In order to avoid the non-linearities and high harmonics inherent to hard saturation, simulations are done with a 3-stage ring oscillator. Otherwise, one should work with tricky expressions, not very suitable to highlight the trade-off between stages. Figure 3.9-(a) shows the pseudo-differential stage with cross coupled PMOS (XCP) transistors, while the pseudo-differential stage with cross-coupled inverters (XCI) is shown in figure 3.9-(b). These two pseudo-differential stages are widely used in the literature: XCP stages can be found in [ 89 , 101 , 102 , 103 ]; while XCI stages can be found in [ 98 , 99 , 104 , 105 ]. The main difference between them is that CL is charged by cross-coupled element in the XCP stage, while CL is charged by delay elements in the XCI stage. In other words, in the XCP stage, PMOS transistors have two roles: charging CL and providing positive-feedback. 42 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.3. Study of Delay Stages E VBias E Vdd E E E MN MP VO 'VO (c) (a) (b) P0P1 N0N1Vi+ Vi- CL Vd d CL VO- 'VOVO+ ' VO+ Vi+ Vi- Iz Iz Ix Ix CL CL VOVO+ ' VO- ' VO+ VBias E V Bias E V Bias E V Bias E Figure 3.9: (a) Pseudo-differential stage with cross-coupled PMOS (XCP), (b) pseudodifferential stage with cross-coupled inverters (XCI) and (c) tunable resistor. CL is the capacitive load, VBi as is the tuning voltage, V0 o and Vo are the terminals of the tunable resistor, Eand Eis the enable and its complementary, respectively. β X(s) = 0 A(s) F0(s)F1(s)FN-1(s) Y(s) Figure 3.10: Simplified block diagram of N-stages ring oscillator. While in XCI, these tasks are done by delayinverters and cross-coupled inverters, respectively. The frequency tuning of these rings is achieved by means of a voltage controlled resistor between each delay stage [ 99 ]. The schematic of the tunable resistor is shown in figure 3.9-(c). The tuning voltage, VBias , changes the conductance of MP transistor, while the voltage gate of MN is kept constant. This means that, for a value of VBias =Vdd , MP is in cut-off, while MN is still active, and oscillations are possible. The main advantage of this method is to control the oscillation frequency almost linearly with the tuning voltage as will be shown in the following sections. 3.3.1 Oscillation Frequency Single-ended, differential with clipped outputs and pseudo-differential ring topologies are highly non-linear systems, due to the fact that the transistor do not operate around the same operation point, e.g., saturation, linear or cut-off, but rather, it fluctuates from one region to the other during its operation. For 43 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN that reason, the study and analysis of these ring oscillators is not trivial. To circumvent this issue, the feedback loop can be divided into its linear time invariant and non-linear time invariant components. Doing so, the oscillation frequency can be estimated by means of frequency domain linear analysis, whereas the non-linear component determines the output swing [ 100 ]. This assumption is valid as long as the amount of time that the output remain hard saturated is negligible. In other words, the output signal is more sinusoidal than squared and it has less harmonics. Therefore, in this section a smallsignal analysis is performed to estimate the oscillation frequency of the ring. In figure 3.10, the simplified block diagram of a ring oscillator with N stages is shown. The closed loop transfer function, H ( s ), of the whole system has the following form: H(s)=Y(s) X(s)=A(s) 1+A(s)β(3.5) Barkhausen criteria is a necessary condition for steady state oscillation but not sufficient for starting-up oscillations. To fulfill Barkhausen criteria at the angular oscillation frequency, ω0 , the characteristic equation of (3.5) becomes: 1+A(s)β=0⇒A(jω0)β=−1 (3.6) where A ( jω0 ) is the transfer function of N stages and β is the feedback transfer function, the time invariant non-linear component, that is considered equal to 1 during this step of the analysis. Therefore, the oscillation condition can be rewritten as: |A(jω0)|∠φ=¯¯F(jω0)¯¯ N ∠π=1∠π(3.7) for simplicity, the transfer function of each delay stage, F ( jω0 ), has a single dominant pole at ωp: F(jω0)=A0 1+jω0 ωp (3.8) applying (3.8) into (3.7), the following equations are obtained:      A0 r1+³ω0 ωp´2      N =1 φ=Narctanµω0 ωp¶=π (3.9) 44 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.3. Study of Delay Stages rox CL roz 1/GT vo+ 'vo+ gmn+gmp zvigmn+gmp xvo- () () ro CL 1/GT vo+ vo+ ' gmpvogmnvi- (a) (b) Figure 3.11: (a) Small-signal model of the half pseudo-differential XCP stage and (b) small-signal model of the half pseudo-differential XCI stage. solving the expression (3.9) for the oscillation frequency, f0: f0=ω0 2π=ωp 2πtan³π N´(3.10) Expression (3.10) illustrates that the oscillation frequency in the small-signal model, f0 , is function of two parameters: the pole frequency, ωp ; and the number of stages, N . Consequently, it is fundamental to study the small-signal model of each stage to find which of them provides the highest oscillation frequency. Pseudo-Differential Stage with Cross-Coupled PMOS Figure 3.11-(a) represents the small-signal model of the XCP stage. The transfer function of this stage is: FXCP (s)=− gmn gmp−go−sCL¡1+RTgo¢(3.11a) ωp=go−gmp CL(1+RTgo)(3.11b) where FXCP ( s ) is the transferfunction of the pseudo-differential stage with crosscoupled PMOS, go is the output conductance of the combination of MP0 and MN0 transistors, gmp is is the transconductance of MP0 which is in parallel to the output conductance go , RT is the resistance of the tunable resistor described by (3.13), and the capacitor CLcan be approximated as: CL=(Cg s +Cgb +Cgd )n+(Cg s +Cgb +2Cgd )p+(Cg s +Csb)MN+(Cds +Cdb)MP (3.12) where the subindex MN and MP stand for the NMOS and PMOS of the tuning resistor, see figure 3.9-(c). GT can be approximated as the conductances of the tunable resistor in linear region: GT=1 RT=βMN¡Vdd −Vo−Vthn¢+βMP³V0 o−VBias −|Vthp|´(3.13) 45 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN where β=µCox W L , Vth is the threshold voltage, Vo is the output voltage of the delay stage and input of the tunable resistor, V0 o is the voltage at the other terminal of the tunable resistor, and VBias is the tuning voltage. Expression (3.13) is valid while V0 o<Vdd −Vthn and Vo>VBias +|Vthp| [ 99 ]. Also, the output conductance of this stage, go, in saturation is: go=gdsn+gdsp(3.14) where gdsn and gdsp are the small-signal common-source output conductances of MP0 and MN0 transistor, respectively. Finally, substituting (3.14) and ωp from (3.11b) into (3.10), the oscillation frequency can be defined as: f0=GT(gdsn+gdsp−gmp) 2π³GT+gdsn+gdsp´CL tan³π N´(3.15) As it was shown in the previous section, the main function of PMOS transistors is to charge CL up to Vdd through the conductance gdsp . Furthermore, as expression (3.15) shows, an increase of the PMOS strength not only increases gdsp but also gmp , this could lead to a reduction of f0 . Moreover, if it is considered that GT¿gdsn+gdsp , the oscillation frequency can be simplified to a linear function of VBi as, if expression (3.13) remains valid. Pseudo-Differential Stage with Cross-Coupled Inverters figure 3.11-(b) represents the small-signal model of pseudo-differential stage with cross-coupled inverters. The transfer function of this stage is: FXC I (s)=− (gmn+gmp)z (gmx−gox −sCL)¡1+RTgoz¢−goz (3.16a) ωp=GTgoz+(GT+goz)(gox−gmx) (GT+goz)CL (3.16b) where the subindex z and x stand for the delay inverters, Iz , and the crosscoupled inverters, Ix , respectively. FXC I ( s ) is the transferfunction of the pseudodifferential stage with cross-coupled inverters, goz is the output conductance of the delay inverters, gox is the output conductance of the cross-coupled inverters, gmx= ( gmn+gmp ) x is transconductance of the cross-coupled pair, RT is the resistance of the tunable resistor described by (3.13) , and the capacitor CL in saturation can be approximated as: CL=(Cg s +Cgb +Cgd )nz +(Cg s +Cgb +Cg d )pz +(Cg s +Cgb +2Cg d )nx +(Cg s +Cgb +2Cgd )px +(Cg s +Csb)MN+(Cds +Cdb)MP (3.17) 46 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.3. Study of Delay Stages And the output resistances of this stage in saturation are, roz =1 (gdsn+gdsp)z rox =1 (gdsn+gdsp)x (3.18) Finally, substituting (3.18) and ωp from (3.16b) into (3.10) the oscillation frequency can be expressed as: f0= GT(gdsn+gdsp)z GT+(gdsn+gdsp)z+(gdsn+gdsp)x−(gmn+gmp)x 2πCL tan³π N´(3.19) From expression (3.19) it can be observed that the contribution of delay inverters is independent of the negative resistance of the cross-coupled pair. Thus, it is possible to increase the strength of delay inverters respect to cross-coupled inverters without increasing the positive feedback term. This guarantees faster charges and discharges of CL . In comparison with (3.15) , expression (3.19) shows that this stage have one degree of freedom more because of its larger number of transistors. As an example, if delay inverters are sized to make ( gdsn+gdsp ) z of (3.19) equal to gdsn+gdsp of (3.15) and CL is imposed equal in both expression, then gmp in (3.15) is always higher than ( gmp+gmn ) x in (3.19) , because cross-coupled inverters can be implemented with minimum size transistors. As a result, this suggests that a ring implemented with this stage has higher oscillation frequency. Simulation Results In order to validate the prediction on the oscillation frequency, two VCROs with 3 stages have been designed and simulated in 110nm CIS technology. To make a fair comparison, both rings have been sized to have similar CL at nominal size and VBias =0V (see table 3.1). The data used to verify the accuracy of the models is obtained from fitting DC operating point simulation results to simulated oscillation frequency, unless otherwise indicated. The delay stages were connected as unity gain amplifiers. The input and the output of the tunable resistor were connected between Vdd and ground, respectively, for the DC operating point calculation. Simulated oscillation frequency, power consumption and phase noise are obtained with periodic steady-state analysis. figure 3.12 shows the oscillation frequency ofa ring with 3 pseudo-differential XCP stages as a function of bias voltage, VBias . Solid line represents the simulated oscillation frequency, while dashed line represents the frequency applying (3.15) . At VBias = 0V and nominal sizes, this stage have gdsn+gdsp=180µS , GT=160µS and the transconductance of PMOS transistors is set as gmp=38µS 47 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN 0 0.5 1 1.5 2 2.5 −158 −156 −154 −152 −150 −148 −146 −144 −142 −140 Wp/Wn(−) FOMosc (dBc/Hz) FOMosc (Wn=2.6μm) FOMosc (Wn= 3.1μm) FOMosc (Wn= 3.6μm) Figure 3.18: FOM osc of a ring with 3 XCP stages as a function of Wp / Wn with VBi as =0V . 3.3.3 Application Despite the fact that both stages are used indiscriminately for the same applications in the literature, the analysis done so far shows that the XCP stage has lower phase noise and the XCI stage has higher oscillation frequency. Hence, it is mandatory to study the FOM of each stage for each application. For example, the principal FOM of oscillators is defined by [99], FOMosc =L−20log10 µf0 fo f f ¶+10log10 µP 1mW¶(3.28) where L is the single side band phase noise power spectral density, f0 is the oscillation frequency, fo f f is the offset frequency at which the phase noise is measured, and P is the power consumption in milliwatts. In figure 3.18, it is shown that the FOM osc of the XCP stage does not depend on the size of NMOS transistor. Moreover, a minimum is reached at the ratio Wp/Wn=0.5. On the contrary, the FOM osc of the XCI stage does not have any minimum, and its magnitude depends on the size of Wnz , showing the same behavior as the oscillation frequency. Also, the smallest value of FOM osc in this oscillator is similar to the obtained with the XCP stage, however, this can only be achieve increasing Wnz . This results suggest that XCP stages are more robust, despite having lower oscillation frequency. VCRO are commonly used in many TDCs architectures. The basic FOM for TDCs represents the amount of energy consumed during a conversion [114], FOMTDC =P 2ENOB fs (3.29) 54 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.3. Study of Delay Stages 0 0.2 0.4 0.6 0.8 1 −157 −156 −155 −154 −153 −152 −151 −150 −149 Wx/Wz(−) FOMosc (dBc/Hz) FOMosc (Wnz =0.8μm) FOMosc (Wnz = 1.1μm) FOMosc (Wnz = 1.6μm) Figure 3.19: FOM osc of a ring with 3 XCI stages as a function of Wx / Wz with VBi as =0V and Wpz =3.6µm. where P is the power consumption, fs is the sampling frequency of the converter, and effective number of bits (ENOB) is the effective number of bits. The ENOB can be approximated as (3.30) if the effect of systematic deviations are negligible, and only random contributions are consider [115], ENOB =log2ÃTf s σT0p12!(3.30) where Tf s = 1/ fs is the full-scale time of the converter, fixed to 20ns for every converter. On the other hand, the period jitter, σT0 , can be obtained from the phase noise [109], σT0=fo f f f0sL f0(3.31) where fo f f is the offset frequency at which the phase noise is measured, f0 is the oscillation frequency, and L is the single side band phase noise power spectral density. figure 3.20 and 3.21 illustrate the amount of energy consumed in a conversion (FOM TDC ) as a function of the transistor ratios for the XCP and XCI stages. It can be observed that the FOM TDC of both stages is reduced as the positive feed-back term is reduced. While the XCP stage shows a drastic reduction from 3pJ per conversion down to 0.5pJ per conversion, the XCI stage provides the lowest values ( 0.3pJ per conversion). As a result, the XCI stage provides more efficient conversions than the XCP stage. 55 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3 3.5 Wp/Wn(−) FOMTDC (pJ/conv.) FOMTDC (Wn=2.6μm) FOMTDC (Wn= 3.1μm) FOMTDC (Wn= 3.6μm) Figure 3.20: FOMTDC of a ring with 3 XCP stages as a function of Wp / Wn with VBi as = 0V. 0 0.2 0.4 0.6 0.8 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Wx/W z(−) FOMTDC (pJ/conv.) FOMTDC (Wnz =0.8μm) FOMTDC (Wnz = 1.1μm) FOMTDC (Wnz = 1.6μm) Figure 3.21: FOMTDC of a ring with 3 XCI stages as a function of Wx / Wz with VBi as =0V and Wpz =3.6µm. 3.3.4 Evaluation of Results The previous sections concentrates on the modeling and design optimization of two representative VCROs based on pseudo-differential delay cells. Although the outputs of this kind of oscillators are switching from rail-to-rail, small-signal analysis remains a simple and quite accurate tool to compute a first order approximation of the oscillation frequency and noise. This is useful to obtain a fast optimization of the design parameters. The small-signal model provides good accuracy when the number of stages 56 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.4. Time-to-Digital Converter Implementation Controller Start Stop Reset Latches Encoder Ripple counter 8b 3b Coarse output Fine output Ring oscillator Vbias (a) TDC1 11b 11b 11b clk 0 1 3b 3b clk 0 1 TDC0 To Memory Start Stop Reset (b) Sampling Reading Figure 3.22: (a) Block diagram of TDC based on VCRO with 4 delay stages and (b) two TDC working interleaved. is small, if the time spent with saturated outputs is minimum. Additionally, this model highlights very well the contribution of each transistor to the oscillation frequency, making the comparison between stages quite straightforward and helping the designer to identify the principal trade-offs. However, this model can not predict the oscillation frequency when the positive feedback term is big or the number of stages is large. Analytical expressions agree with simulation results, showing that a ring oscillator made of pseudo-differential stage with cross-coupled inverters have higher oscillation frequency. At the same time, analytical expressions predict smaller phase noise in ring oscillators composed of pseudo-differential stage with cross-coupled PMOS and simulation results confirm it. Finally, FOMs were used to study the best application for each stage. Both stages show similar performance as oscillator, since they seem to have the same phase noise figure at the best design choice. On the other hand, XCI stage is better suited for TDCs, when power consumption is considered. 3.4 Time-to-Digital Converter Implementation The study of delay stages has provided an insight into the relations of time resolution and phase noise with the basic design parameters. This approximation allows to find the design point at which the oscillation frequency is maximum, while keeping a reasonable value of power consumption, without having to deal 57 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN Start Stop Reset Run Write Zero S RQ (a) Time Start Stop Reset Run Write Zero Ignored triggerFirst trigger Sampling Reading (b) Figure 3.23: (a) block diagram and (b) time diagram of controller. with cumbersome expressions. Figure 3.22-(a) illustrates a simplified block diagram of a TDC based on VCRO. The building blocks that compose the converter are responsible to start and stop the oscillations, sample the oscillator phases, encode the pseudo-thermometric code 1 of the oscillator phases into binary and count the number of cycles that the ring has done during oscillation. In the following sections these circuits will be presented and described, putting emphasis on its practical implementation. One of the peculiarities of TDC designed for PET is that the trigger signal is completely asynchronous, since the arrival time of gamma photons is unknown. This means that the TDC must cover the whole temporal window. Therefore, architectures with low conversion time are preferred, since the number of TDCs working interleaved is reduced and, hence, the occupation area. The VCRO architecture have a very small conversion time, allowing to cover the whole clock cycle with only 2 interleaved TDCs. Ideally, this implies that while a TDC is sampling, the other is being read, see figure 3.22-(b). Nevertheless, there is always a small misalignment of clock signals that leads to a dead time in the transition between sampling and reading. 3.4.1 Control Logic As figure 3.22 illustrates, the control block is responsible for generating the signals that allow the normal operation of the converter from the input signals start, stop and reset. The output signals of this block must put the oscillator phases to a known value, generate the turn on signal to start the oscillations with the first trigger and generate the signal to read the oscillator phases: • Run: the ring oscillates while this signal is active, this means, that the 1 In a thermometric code, the number “N” is encoded as a string of “N” ‘1’s. Thus, the information is encoded at the transition between ‘1’s and ‘0’s, e.g. the numbers 5 and 6 are { 11111000 } and { 11111100 } , respectively. On the contrary, in the pseudo-thermometric of this ring oscillator, ‘1’s and ‘0’s are alternated and the information is encoded with a string ‘11’ or ‘00’, e.g. the numbers 5 and 6 are {10101101} and {10101001}, respectively. 58 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.4. Time-to-Digital Converter Implementation pulse width, Tsample , is given by the rising edge of the start and stop signal. To guarantee that the measured interval correspond to the arrival time of the first photon, the circuit must only respond to the first start pulse. • Write: when this signal is active, the latches sample the oscillator phases that provide the LSB of the conversion. This signal is generated once the oscillations are stopped. Since the registers are active by level, this signal must have the proper width in all corners. • Zero: this signal is needed to set to a know value the latches, the ripple counter and internal phases of the ring. Doing so, the oscillations start always from the same point. Despite this alternative is the simplest, there are circuits in the literature that implements first order noise shaping by using the stopping point of the previous conversion as the starting point of the new conversion [83]. The circuit of figure 3.23-(a) implements the previous specifications, as the time diagram of figure 3.23-(b) shows, the inputs of the RS bistable is never at the high level at the same time during the normal operation, because the demuxiplier of figure 3.22-(b) prevents against it. Also, some transmission gates have been added to compensate the delays of the start and stop signals. 3.4.2 Ring Oscillator As it was proved previously, the TDC designed with XCI delay stages perform better than the XCP counterpart. In order to have a design as compact as possible, a ring with 4 delay stages is the common choice among designer [ 89 , 116 , 105 ]. This means that the number of phases at which the oscillator can be stopped is 8. As it is expected, these phases can be encoded in 3bit s. In this topology, the phase noise and occupied area of the ring are affected by the number of delay stages in the ring, but the temporal resolution is not modified, because the stage delay is kept constant. Keeping that in mind, if it were necessary to reduce the converter power consumption and the occupied area is not a restriction, a ring with 8 delay stages could be an alternative. Since the oscillation frequency is halved, the power consumption of the ripple counter is reduced considerably. Figure 3.24 presents a ring oscillator composed of 4 delaystages with tunable resistors, reset switches and output inverters. The input of the latches are connected to f1 - f4 and f1 - f4 , while the input of the ripple counter is connected to f4and f4. For that reason, these inverters do not have an enable input, since they must let pass the value of f4 and f4 during oscillations. The main purpose of the other inverters is to make the load capacitance of each stage equal, this is a common practice to reduce non-linearities between stages. 59 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN Vbias Run Write f1 Write f1 Zero Zero Vbias Run Write f2 Write f2 Zero Zero Vbias Run Write f3 Write f3 Zero Zero Vbias Run f4 f4 Zero Zero Figure 3.24: Voltage-controlled ring oscillator with 4 delay stages. (a) Zero f4 f4 TQ r Zero TQ r Zero TQ r Zero TQ r Zero TQ r Zero T3T4T5T10 (b) Clk Clk r r rr Q (c) W W W W W W W W f f Q Q Figure 3.25: (a) Ripple counter based on toggle flip-flops, (b) toggle flip-flop implemented with NAND gates and (c) cross-coupled latch. 3.4.3 Read-out Logic The main function of these blocks is to provide the corresponding binary value associated to the number of oscillations and the stopped phase. The first functionality can be implemented with a ripple counter connected to the last oscillator phase ( f4 ). Hence, when f4 has a falling transition, the counter increases its value. In practice, this kind of implementations are prone to suffer from glitches when the oscillator is stopped during a transition of f4 . This entails the formation of a non-monotonicity in the static transfer function of the converter. The main reasons why these glitches appear are the metastability of delay stages, because of its positive feed-back, and the non-symmetric switch-off of the tun- 60 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.4. Time-to-Digital Converter Implementation Table 3.2: Phases of a ring oscillator with 4 stages. f1f2f3f4T2T1T0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 able resistor. The reader may have noticed that, as figure 3.9-(c) shows, during the switching off transition, the NMOS transistor is disabled before the PMOS transistor. In order to reduce the impact of these glitches and to assure that the oscillation count is increased when a real transition occurs, two flip-flops sample the phases f4and f4and their outputs are compared with an AND gate, as figure 3.25-(a) illustrates. Doing so, the LSB of the counter is only increased when the transition of the two signals happens. The principal drawback of this solution is the power consumption increment, due to the additional flip-flop working at the oscillation frequency. Analytically, the power consumption of the ripple counter can be approximated as, Pc=Ps+Pd Ps=Vdd Ileak Pd≈foscCeqV2 dd Ã2+ n=10 X i=3 1 2i−2!(3.32) where Pc is the total power consumption of the ripple counter, Ps is the static power consumption due to leakage, Pd is the dynamic power consumption, Vdd is the voltage supply, Ileak is the current leakage, fosc is the oscillation frequency, Ceq is the equivalent input capacitance and i is the bit index. The factor 2 inside the braces represents the two flip-flops. As it is expected, the topology of the flip-flop will determine the power consumption by means of Ceq . figure 3.25-(b) represents the schematic of a NAND flip-flop, this topology has been chosen because of two reason: it is a static memory, therefore, the stored value is not lost and no minimum sampling frequency is required, fs ; and its maximum operation frequency is high enough to deal with the output of the oscillator. The main drawback of this topology is its large area occupation compared to other alternatives. Regarding the phase sampling, two circuits are needed: regenerative latches like the one shown in figure 3.25-(c) and an encoder to translate the pseudo- 61 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3. TIME-TO-DIGITAL CONVERTER DESIGN Table 3.3: Post-layout simulation results. Parameter Value Units Area 2925 µm2 Ring oscillator power 0.8 mW Ripple counter power 0.6 mW Total power 1.4 mW Maximum range 185 ns Maximum fs50 MHz Minimum resolution 90 ps thermometric code of the phases into binary. To find the encoder expression, the different phase permutations during oscillations must be studied. The truth table 3.2 represents all possible permutations of the phases and their encoded value. It can be observed that between consecutive permutations, only one bit is changed, similar to what happens in Gray code. Using the truth table, the expressions for the of the converter output can be easily obtained, as (3.33) represents. T0=f1f2f3f4+f1f2f3f4+f1f2f3f4+f1f2f3f4(3.33a) T1=f1f2f4+f1f2f4(3.33b) T2=f4(3.33c) The simplicity of these expressions allows to implement them with CMOS, transmission gate or pseudo-NMOS logic, to name a few. These expressions were implemented with pseudo-NMOS logic, because of its small footprint. 3.4.4 Physical Design and Simulation Results Post-layout simulation results are summarized in table 3.3, it can be see that the occupation area is bigger than in [ 89 ], mainly because of the empty space and the large area of the ripple counter. Moreover, the power consumption is over 1mW , while the ring is oscillating at maximum frequency. Also, the minimum time resolution is below 100ps . However, the final accuracy of the converter will be worse, because there is no phase locked loop (PLL) to compensate PVT variations. Future designs will address this issue. All in all, it is expected a degradation of these parameters during the chip measurements. Figure 3.26 illustrates the layout of the designed converter. It can be see that the ripple counter is the biggest block followed by the ring oscillator. Although the blocks themselves are compact, the floorplan shows that there is still room for future improvements in terms of area occupation. 62 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 3.4. Time-to-Digital Converter Implementation Ripple Counter Ring Oscillator Controller Latches Encoder Figure 3.26: TDC layout. 63 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4. ARCHITECTURAL EXPLORATION Mspl , and the number of SPADs per micro-cell, Nµc . Thus, the number of SPADs per pixel can be calculated as the fraction between the pixel area not occupied by logic and the area occupied by one SPAD and its logic: Nspad ¡Mspl ,Nµc¢=Ì Ì Ì Ê Apxl −(Atdc +Af sm +Acnt Mspl ) Aspad +Aaqrc +Adcmm Nµc Í Í Í Ë(4.2) where Aspad =b2=£x+2¡GR +r+b0¢¤2 is the SPAD area, see figure 4.2-(a); Apxl is the total pixel area; Atdc is the TDC area; Af sm is the FSM area; Acnt is the area occupied by sub-pixel logic, like counters and multiplexers; Aaqrc is the area of the AQRC; and Adcmm is the SPADs shared dead area, like monostable, reset circuits. Note that the parametric cell of the SPAD generates an square active area with rounded corners if x> 0. As it was explained in chapter 2, rounded corner are preferred over right corners, because they are associated with lower electric fields at the edges and, consequently, lower DCR due to premature breakdown [48]. The next step is to obtain the PDE of the pixel: PDE ¡Mspl ,Nµc¢=Aaspad Nspad Apxl PDP (4.3) where Aaspad =x2+ 4 r x +r2π is the SPAD active area. As it was commented previously, an ideal SiPM has an output proportional to the number of incident photons. Nevertheless, since the number of micro-cells is limited in a real SiPM, its output experiments a saturation when the incident number of photons is high enough, in the order of Nµc∼NphPDE as expression (4.1) states. This, however, is only the first of the non-idealities that a digital SiPM has. The studied architecture presents some other limitations whose influence must be estimated. In [ 81 ], the probability of losing photons, pile-up, due to spatial and temporal compression is calculated with a Poisson distribution. The spatial compression is obtained when the monostable and reset logic is shared among different SPAD cells, see figure 4.2-(b). This means that only one photon can be counted by each SPADs micro-cell after an avalanche, because the dead time is shared among all the SPADs of the micro-cell. Here, to simplify the analysis, the SPAD dead time is set equal to the clock period, Tclk . The main advantage of this approach is the increase of fill factor, as a result of the fact that the area of common logic is shared among different SPADs. Hence, the probability of losing photons due to spatial compression ( Psp ), i.e. two or more photons arrive at different SPADs from the same micro-cell during the scintillation build-up, from t=0 to t=Tclk, can be expressed with a Poisson distribution [81]: Psp (µsp;k>1) =1−Psp(µsp;k=0) =1−µk sp k!exp¡−µsp ¢(4.4) 70 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4.2. Figure of Merit Definition and Optimization where k is the number of times the event occurs, that is, photon losses or pile-up per micro-cell; and µsp is the average number of events per sampling interval, i.e, the number of detected photons per micro-cell, from t= 0 to t=Tclk . As it was discussed in expression 1.4, the emission dynamics of a scintillation event are modeled by exponential decays. In the particular case of LSO and LYSO scintillators the emission is usually simplified with one time constant. The number of detected optical photons at a pixel per unity of area, OPd , during the scintillation build-up, from t= 0 to t=Tclk can be obtained by integrating the instantaneous photoemission described by expression (1.4) in chapter 1: OPd=PDE ·Hq··1−expµ−Tclk τLSO ¶¸ (4.5) where Hq is the maximum incident photons per unit of area per event calculated in expression (1.9) and τLSO is the scintillator time constant, in this case LSO. Finally, combining (4.4) and (4.5) , the probability of losing photons due to spatial compression is: Psp (µsp;k>1) =1−exp¡−NµcAaspadOPd¢(4.6) From this expression it can also be derived that SiPMs composed of smaller SPADs have smaller losses due to spatial compression, i.e. larger linearity, because the active area of the micro-cell ¡NµcAaspad ¢is reduced. On the other hand, temporal compression is obtained when the monostable shrink the SPAD output pulses, making possible the counting of more pulses during the same readout interval. As there is not arbitration method to access the pull-up OR, the loss of information is expected due to pulse overlapping, see figure 4.2-(b). The probability of losing photons due to temporal compression, i.e. two or more monostable pulses are so close that the counter is unable to distinguish them, can be expressed with a Poisson distribution [81]: Ptp (µt p ;k>1) =1−Ptp(µtp ;k=0) =1− µk tp k!e−µtp =1−exp·−Nspad AaspadOPdTpul se Tclk Mspl ¸ (4.7) where k is the number of times the event occurs, that is, monostable pulses overlaps; and µtp is the average number of events per sampling interval, from t= 0 to t=Tclk . It is commonly attributed to the Tpulse to be the driving parameter of these losses, unfortunately its minimum value is limited by the resistive and capacitive parasitics of the trigger path. On the contrary, the fraction Nspad / Mspl is easier to modify, because it is independent of parasitics. Other approaches, like the presented in [ 121 , 122 ], substitute the monostable and OR tree by a toggle registerper micro-cell and a XOR tree. This way temporal compression is eliminated because the photons are encoded into the edges 71 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4. ARCHITECTURAL EXPLORATION of the XOR output and the dynamic range is accordingly increased. The main drawback of this approach is the larger occupation area of toggle registers per micro-cell and the XOR tree. Furthermore, the XOR tree is unable to preserve the arrival time of the first photon as OR tree does [ 122 ]. Finally, the sensitivity of the sensor, i.e. photon counting probability, can be calculated with (4.3) , (4.6) and (4.7) as, S(Mspl ,Nµc)=PDE(1−Psp )(1−Ptp) =Aaspad Nspad PDP Apxl exp³−A2 aspad Nspad α´(4.8) where αis independent of the SPAD area: α=PDP Apxl Hq·1−expµ−Tclk τLSO ¶¸µNµc+Nspad Tpulse Mspl Tclk ¶(4.9) Expression (4.9) is function of Nµc , Mspl and the SPAD size. Also, at its rightmost parenthesis, the contribution of spatial and temporal compression is shown. The term Nµc determines the spatial compression, while the factor Nspad Tpulse / Mspl sets the temporal compression. It can be see that that large values of the two components reduces the overall sensitivity. Also, the influence of temporal compression respect to spatial compression can be reduced if Nspad Tpulse / Mspl ¿Tclk . Therefore, since Tclk is determined by the TDC conversion time and Tpulse is limited by parasitics, the SPAD size, Nµc and Mspl are the only free variable. In the following, the SPAD size, x , that provides the maximum sensitivity for each combination of Mspl and Nµc must be calculated from dS/dx =0. The analytical expression for dS/dx is: dS dx =PDP Apxl    d(Aaspad Nspad ) dx exp³−A2 aspad Nspad α´ +Aaspad Nspad dhexp³−A2 aspad Nspad α´i dx    (4.10) The last step is to set equal to zero expression (4.10) . However, since (4.10) is a transcendental equation, the close-form expression to solve dS / dx = 0 may not exist. For this reason, numerical methods must be used to obtain the value of x that provides the best sensitivity for each combination of Mspl and Nµc . Figure 4.3 illustrates the optimum SPAD size in terms of sensitivity as a function of Mspl and Nµc . These pitches are similar to those offered by commercial products [38, 37, 42]. Finally, the SNR can be used to study the trade off between Mspl and Nµc . It can be approximated as follows if DCR (in Hz/mm2 ) is considered to be proportional to the SPAD active area: 72 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4.2. Figure of Merit Definition and Optimization 0 5 10 15 SPADs per micro-cell (Nμc) 0 20 40 60 80 100 120 Sub-pixels per pixel (Mspl) Nμc: 1 Mspl: 128 x: 53.1 Nμc: 1 Mspl: 32 x: 48.2 Nμc: 4 Mspl: 32 x: 26.4 Nμc: 16 Mspl: 32 x: 14.0 50 40 30 20 10 SPAD size (μm) Figure 4.3: SPAD size, x , as a function of number of sub-pixels per pixel and number of SPADs per micro-cell. SNR(Mspl ,Nµc)=µSi gnal Noi se ¶2 =µOPdApxl S Tclk Nspad Aaspad DCR ¶2 =  Hqh1−exp³−Tclk τLSO ´iApxl S Tclk Nspad Aaspad DCR   2 =  HqPDP h1−exp³−Tclk τLSO ´i Tclk DCR   2 exp³−2A2 aspad Nspad α´ (4.11) As figure 4.4 represents, the sensitivity has the lowest values when Mspl < 16, because the photon losses due to temporal compression are larger. However, when this number is above 16, the sensitivity reaches a plateau with the highest value at Mspl ={ 32 , 64 } and Nµc= 1. These results show that architectures with shared monostables ( Nµc> 1) have slightly lower sensitivity, because the sensor saturation is achieved earlier since the dead time is common among the SPADs connected to the same monostable. The figure 4.5 illustrates the counted photons as a function of incident photons for a pixel with Nµc= 1. The dashed line represents the ideal response of a sensor (considering only the PDE), while solid lines show the response of 73 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4. ARCHITECTURAL EXPLORATION 0 5 10 15 SPADs per micro-cell (Nμc) 0 20 40 60 80 100 120 Sub-pixels per pixel (Mspl) Sensitivity (%) 7 8 9 10 11 12 13 14 15 Nμc: 1 Mspl: 32 S: 15.7 Nμc: 1 Mspl: 128 S: 14.0 Nμc: 16 Mspl: 32 S: 11.3 Nμc: 4 Mspl: 32 S: 14.3 Figure 4.4: Sensitivity as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for optimized size. the sensor considering photon losses due to compression. In figure 4.6, the definition for the sensor non-linearity is provided. From this data, the nonlinearity of the sensor can be calculated, as figure 4.7 summarizes. The lowest values of non-linearity can only be achieved if the parallelism of the pixel is maximum, i.e. SPADs do not share monostable and the number of sub-pixels is large. Figure 4.8 illustrates the SNR as a function of Nµc and Mspl . Although it may seem counter intuitive, the SNR does not have any maximum as the sensitivity does around Nµc= 1 and Mspl ={32,64} . This is because the number of SPADs is smaller at the SNR maximum than at the sensitivity maximum (around 125 fewer SPADs). As a result, the small maximum is masked by noise reduction. It has to be noted that the DCR in this expression is not realistically modeled, since large SPADs have not only larger noise but their yield is worst (higher number of very noisy devices). Furthermore, in figure 4.8, it can be observed that the SNR is more or less constant, with less than 1dB of variation, in the whole range of Nµc . The SNR is also quite constant respect to the Mspl when Mspl >16. At this point, the feasibility of these optimum architectures has to be verified with post-layout simulations, because the resistive and capacitive parasitics determine the violation of hold-on and set-up times at register-transfer level. Ideally, this should be done with digital synthesis tools. However, since all the cell where designed in the analog domain, an analytical approximation is 74 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4.2. Figure of Merit Definition and Optimization 0 100 200 300 400 500 0 20 40 60 Incident photons Counted phtons 80 Detected Ph. max Msbpxl = 1 Msbpxl = 8 Msbpxl = 32 Msbpxl = 64 Msbpxl = 128 Figure 4.5: Counted photons as a functions of incident photons with 1 SPAD per microcell for optimized size. The dashed line represents the detected photons (ideal sensor response), the triangle is pointing the maximum number of incident photons in Tclk . In Out Diffmax InFull Scale nonLin Diffmax InFull Scale Figure 4.6: Graphic definition of non-linearity. presented. In figure 4.9, the data propagation flow is shown. The number of accumulated photons at each sub-pixel must be sent through the adder tree to the FSM input. In order to avoid set-up and hold-on violations, the time needed for this data to be propagated, Tlogic , determines the maximum and minimum number of sub-pixels for a given Tclk , respectively. This is because the number of sub-pixels determines the number of adders between the sub-pixels and the FSM. To avoid set-up violations, the data at the FSM input must be valid a time Tset−up before the clock edge. Thus, set-up condition is met if expression (4.12) is valid, 75 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4. ARCHITECTURAL EXPLORATION 0 5 10 15 SPADs per micro-cell (Nμc) 0 20 40 60 80 100 120 Sub-pixels per pixel (Mspl) Non-Linearity (%) 3 4 5 6 7 8 9 10 Nμc: 1 Mspl: 32 nL: 3.5 Nμc: 1 Mspl: 128 nL: 2.8 Nμc: 16 Mspl: 32 nL: 6.1 Nμc: 4 Mspl: 32 nL: 4.7 Figure 4.7: Pixel non-linearity for optimized size SPAD. Tclk ⩾Tskew +Tset−up +Tclk→q+Tlogic max Tclk ⩾Tskew +Tset−up +Tclk→q+Tf a ©n+2£log2¡Mspl ¢−1¤ª+Tpath log2¡Mspl ¢ (4.12) where T clk is the clock period, Tskew is the delay in the clock path, Tset−up is the flip-flop set-up time, Tclk→q is the time needed for the flip-flop to show a valid output after the rising edge of the clock, Tlogic max is the maximum delay of the adder tree and it is divided into two component. Tpath is the delay between two adder levels. Tf a £n+2log2¡Mspl ¢¤ determines the longest delay path by determining the maximum number of full adders through which the data is propagated. The number of bits of the sub-pixel counter can be estimated taking into account the number of detected photons per sub-pixel, n=È Ì Ì Ì log2   HqApxl PDE h1−exp³−Tclk τLSO ´i Mspl   É Í Í Í (4.13) The values of these parameters are calculated from our library blocks at the worst corner, resistive and capacitive parasitics are also included. On the other hand, to avoid hold-on violations, the data must not change a time Thold−on after the clock edge. The hold-on condition is met if expression (4.14) is valid, Tclk→q+Tlogic min −Tskew −Thold−on ⩾0 Tclk→q+¡Tf a +Tpath¢log2¡Mspl ¢⩾Tskew +Thold−on (4.14) 76 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4.2. Figure of Merit Definition and Optimization 0 5 10 15 SPADs per micro-cell (Nμc) 0 20 40 60 80 100 120 Sub-pixels per pixel (Mspl) SNR (dB) 71.5 72 72.5 73 73.5 74 Nμc: 1 Mspl: 32 SNR: 73.9 Nμc: 1 Mspl: 128 SNR: 74.2 Nμc: 16 Mspl: 32 SNR: 73 Nμc: 4 Mspl: 32 SNR: 73.5 Figure 4.8: Signal to noise ratio as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for optimized size. where Tlogic min is the minimum delay of the adder tree and it is function of Mspl . Table 4.2 summarizes the pixel configurations that violate hold-on and set-up conditions. Considering that the clock period is fixed at 20ns , due to the TDC conversion time, the number of sub-pixels per pixels must be higher than 4 to avoid hold-on violations. In terms of set-up, the number of sub-pixels could be 64 or 128. However, these results are too close to the clock period and should be taken with caution since they are approximations. Table 4.2: Set-up and hold-on conditions for Nµc=1. Mspl Set-up (ns) Hold-on (ns) 1Tclk ⩾6.5 0.3 2.2 2Tclk ⩾8.5 1.2 2.2 4Tclk ⩾9.8 2.1 2.2 8Tclk ⩾11.1 3.0 ⩾2.2 16 Tclk ⩾13.1 3.9 ⩾2.2 32 Tclk ⩾14.4 4.8 ⩾2.2 64 Tclk ⩾15.7 5.7 ⩾2.2 128 Tclk ⩾17.7 6.6 ⩾2.2 Taking into account all the previous data, the optimum architecture in terms of sensitivity should have Nµc=1 and Mspl =32 . At this point, Nspad ≈390 , Aspad =3800µm2 and Aaspad =3100µm2 . This configuration provides the best 77 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4. ARCHITECTURAL EXPLORATION Sub-pixels Output FSM Input n n n+1 ... ... n n n+log2(Mspl)Reg Clk Tlogic Tskew Tclk q Adder Tree RegMspl Reg2 Reg1 Tfa n+1... ... n+log2(Mspl)-1 n+log2(Mspl)-1 Tpath ... ... Figure 4.9: Data path from sub-pixel output to finite state machine (FSM) input. sensitivity ofall possible, however, its linearity is not optimal. Betterlinearity can be obtained with smaller SPAD, as it will be see in the next section. Moreover, from the yield point of view, Nµc>1 are preferred to keep DCR as a linear function of active area and to reduce the impact of defective SPADs over the fill factor, that is, a small defective SPAD has smaller impact in the fill factor than a big one. As a consequence of the minimal variation of SNR as a function of Mspl , the SNR is not considered during the comparison. 4.2.2 Constant SPAD size Another commonly used approach is to set a constant, and previously tested, SPAD size to find the optimum design point for a given FOM. This provides sub-optimum performance in terms of the FOM. However, the main advantage is that the whole performance can be better estimated if a complete characterization of the SPAD was carried out previously. This is because the size have an impact in the SPAD yield, e.g. bigger SPADs have worst jitter and DCR. Since the size is set constant, the analysis is reduced to study how the FOMs vary as a function of Mspl and Nµc . This simplifies the whole process, because no optimization is required and expressions (4.8) and (4.11) can be used to determine the sensitivity and SNR, respectively. The proposed SPAD dimensions for this analysis were presented in chapter 2: x=5µm , r=5µm , GR =1µm , Aaspad =200µm2 and Aspad =449µm2 . These dimensions are chosen to have a SPAD fill factor close to 40% and keep the impact of noisy devices low. As figure 4.10 represents, the optimum architecture in terms of sensitivity 78 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 4.2. Figure of Merit Definition and Optimization 0 5 10 15 20 25 30 SPADs per micro-cell (Nμc) 0 20 40 60 80 100 120 Sub-pixels per pixel (Mspl) Sensitivity (%) 5.5 6 6.5 7 7.5 8 8.5 9 9.5 Nμc: 4 Mspl: 32 S: 8.7 Nμc: 1 Mspl: 128 S: 5.1 Nμc: 16 Mspl: 32 S: 9.4 Figure 4.10: Sensitivity as a function of number of sub-pixels per pixel and number of SPADs per micro-cell for constant SPAD size. is around Mspl ={ 16 , 32 } and Nµc={ 15 , 24 } . Contrary on what was shown in figure 4.4, there is a sub-optimum point if the SPAD size is constant. This is attributed to the fact that, for the given SPAD size, a slight fill factor increment have more impact in the final sensitivity than a slight decrement of the losses caused by sensor saturation. This is valid until saturation starts to rise for Nµc>24. As it was expected, figure 4.11 shows how a smaller SPAD size produces an increase in the sensor linearity at the price of lower sensitivity compared with the data of figure 4.5. Since the linearity is improved as figure 4.12 represents, the sensor could be useful for higher brightness applications than PET. This results illustrates the trade-offs between sensor linearity and sensitivity. From figure 4.13, it can be observed that the SNR shows a similarbehavior for both design approaches, variable and constant SPAD size. This is a consequence of a lower active area per pixel susceptible of producing dark counts atthe points with the highest Mspl and lowest Nµc . If the DCR were independent of active area, the SNR would be proportional to the sensitivity, as expressions (4.8) and (4.11) show. In this case, the hold-on and set-up conditions are summarized in table 4.3, these results are similar to those obtained in the previous section. Because both hold-on and set-up violations are determined by shortest and longest delay path, respectively, between the sub-pixel output registers and the FSM input registers. The only difference comes from number of bits of the sub-pixel 79 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be CHAPTER 5 DIGITAL SILICON PHOTOMULTIPLIER CHARACTERIZATION As in many other fields of science, in microelectronics, it is common that the characterization of the first prototype is not only carried out to demonstrate its functionality but also to obtain the necessary information to improve future designs. If the initial assumptions were wrong, the root of the mistake is tracked and solutions are proposed, in order to verify them in future designs. Nowadays, the design of integrated circuits generally does not requires several error and trial iterations. Mainly thanks to the large panoply of computer-aided design (CAD) tools, the designers have at their fingertips and to the foundry efforts to provide well modeled, tested and verified devices. Nevertheless, this is not usually the case for SPADs in CMOS technologies, because foundries do not usually provide them as a standard library cells. The lack of a precise device model involves designing front-end on the basis of the acquired knowledge from the bibliography or the experience of previous implementations. Most of the times, this means to explore and to push the limits of the technology. Despite of the effort of the community to characterize these devices and show their functionality, the lack of experience in this field is an entry barrier for all those new designers that look with distrust, not without reason, any full-custom device that must be biased beyond the break down voltage of its p-n junction. The main goal of this chapter is to characterize the implemented d-SiPM under low-light conditions, similar to the working environment in the application scenario. First of all, the I-V diode characterization is carried out in section 5.1 to extract the breakdown voltage and the internal breakdown resistance. In section 5.2, the array noise is obtained to determine the yield of the devices. Next, in section 5.3, the electro-optical characterization is carried out to find 87 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5. DIGITAL SILICON PHOTOMULTIPLIER CHARACTERIZATION the PDP. Finally, simulations results are provided to show the validity of the expressions obtained during the architectural exploration. 5.1 Diode Characterization The first step of SPAD characterization is always to determine the diode breakdown voltage. Therefore, during the characterization of the other parameters, these can be easily expressed as a function of excess voltage. In order to verify the uniformity of the breakdown voltage, 400 devices from 4 different chips were studied. Low variability of breakdown voltage, both device-to-device and chip- to-chip, is required for SPAD structures implemented in arrays, to guarantee uniform biasing in the whole structure. Also, the shape of the I-V characteristic provides some qualitative information about the presence of PEB and the quality of the p-n junction. Firstly, the I-V characteristic with smooth slope, like the shown in figure 5.1-(a) for PP/NW3V3 devices, usually indicates the presence of PEB, because the breakdown resistance in these devices is higher than the breakdown resistance for a p-n junction without PEB. This higher resistance is caused by a smaller area (lateral junction) through which the current flows during the avalanche. Generally, lateral junctions are vertical p-n junctions at the perimeter of the active area, close to the guard ring. As it was explained in the chapter 2, devices with this characteristic are, in practice, insensitive to light, since the active area never reaches a proper breakdown voltage. Secondly, since all the SPADs share the same cathode, the variations in the breakdown voltage means a variation in the excess voltage for each device, leading to variations of PDP and DCR. figure 5.1-(b) represents the I-V characteristic of PW3V3/DNW diodes of different shapes and sizes. In this case, current through the device rise abruptly from 20nA, due to reverse saturation current, to 4mA. This last value is limited by the measurement instrument to avoid device destruction. Also, the current start to saturate around 100µA because of the multiplexing circuitry of the test array. The figure 5.2 illustrates the breakdown voltage of 400 PW3V3/DNW devices from 4 different chips. The breakdown voltage was defined as the voltage where the current increment has its maximum in the I-V characteristics. It can be observed that the breakdown voltage is around 18.0V at room temperature. Moreover, in the worst case scenario, the variation of breakdown voltage is below 0.3V all the SPADs. This entails that in an array of SPADs biased with an excess voltage of 3.0V above the average, the excess voltage difference between the SPADs with highest and lowest breakdown voltage is below 10% . And it is less than 5% if the excess voltage is 6.0V . The uniformity of the biasing helps to keep the uniformity of parameters like PDP and DCR, for this reason high excess voltages are preferred. On the other hand, the figure 5.3 represents the breakdown voltage as a function of the chip temperature, controlled with an air forcing system. The 88 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5.1. Diode Characterization 15 15.5 16 16.5 17 17.5 18 18.5 19 19.5 20 ISPAD (A) 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 VSPAD (V) VSPAD (V) (a) (b) ISPAD (A) 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 17 17.5 18 18.5 19 19.5 20 Figure 5.1: Inverse current as a function of cathode-anode voltage for SPADs with different sizes and shapes at room temperature: (a) PP/NW3V3 diodes with premature edge breakdown (PEB) and (b) PW3V3/DNW diodes without PEB. 17.9 18 18.1 18.2 VBD (V) 0 20 40 60 80 100 120 140 NSPAD VBD Figure 5.2: Histogram of break down voltage of the PW3V3/DNW devices at room temperature. The mean is 18.01V and the total number of samples is N=400 from 4 different chips. temperature coefficient is around 14mV/K for the range of 255 – 365K , this value agrees with the reported results from [ 55 , 56 ]. Qualitatively, this can be explained because charge carriers with higher temperature lose a fraction of their energy to optical phonons via scattering. These collisions cause a reduction of the ionization ratio of the charge carriers crossing the depletion region [ 33 ]. For this reason, higher electric field and, therefore, voltage is required to ensure the breakdown condition described in chapter 2. This data is necessary to emphasize the importance of a properly sized quenching resistor, since too large or improperly quenched avalanche currents may lead to SPADs self-heating due 89 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5. DIGITAL SILICON PHOTOMULTIPLIER CHARACTERIZATION 260 280 300 320 340 360 Temperature (K) 17.5 18 18.5 19 19.5 VBD (V) VBD experimental VBD = 0.014·T + 14.01 R2 = 0.9885 Figure 5.3: Break down voltage for a PW3V3/DNW SPAD as a function of temperature. Linear fit shows a slope of 14 mV/K. 0 0.02 0.04 0.06 0.08 0 500 1000 1500 2000 2500 RBD (Ω) 1/Area (μm-2) R2 = 0.9927 Rfit = 27440/Area+190 RBD experimental Figure 5.4: Breakdown resistance as a function of the inverse of the SPAD active area at room temperature. to Joule effect. In a compact array, this means the creation of a hot spot able to reduce the excess voltage of its neighbor devices and, therefore, to create variations in the PDP and DCR of the array. Also from the I-V characteristics, the breakdown resistance ( RBD ) can be calculated. Despite only 4 different SPAD sizes were implemented, this data will help to improve the electrical models for future designs. In figure 5.4, 90 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5.1. Diode Characterization Figure 5.5: (a) Avalanche photo-emission of PP/NW1V2 SPAD with premature edge breakdown and ISPAD =10mA (b) avalanche photo-emission of PW3V3/DNW SPAD without premature edge breakdown and ISPAD =19mA . Turned-off SPADs are shown for comparison purposes. the value of the slope ( ∼30kΩ/µm2 ) is high, but it is consistent with the fact that Deep N-well layers have a low doping. The offset of 190Ω is due to the parasitic resistance of the physical set-up and the multiplexing logic. As it was shown in chapter 2, the time constant of the quenching can be approximated to a linear function of the breakdown resistance and the junction capacitance ( τQ≈RBDCK A ). Apart from increasing the quenching time, less doped layers are also associated to devices with larger jitter than devices implemented with more doped layers (less resistive junctions), like the PP/NW3V3. This larger jitter is the result of statistical variation in the number of emitted photons during the avalanche building-up and spreading [52]. A common experiments to test the uniformity of the p-n junction consist of studying the avalanche photoemission, that is, the emission of photons in the visible spectrum due to the impact ionization of electron and holes in the p-n junction [ 47 , 51 , 61 ]. This technique is very useful to identify regions where avalanches are occurring, because these regions are highly illuminated. This helps to study the electric field uniformity across the active area, the effectiveness of guard ring structures or the presence of PEB [47, 123, 124, 125]. To bias the diodes in a self-sustainable avalanche region, low quenching resistors are required, this leads to reverse currents in the order of 1 – 20mA . In figure 5.5-(a), photoemission attributed to PEB and non-uniform doping can be observed at the borders and the center of a PP/NW1V2 diode, respectively. This image was obtained by superimposing an black and white image of the diode with background light over a color image of the same region without any illumination.s Long exposure, around 14 seconds, was required to obtain the picture of photoemission. The current through the device is 10mA . The reason why there is discontinuous glow at the border is because of the lack of electric field uniformity in the PP/NW1V2 depletion region. To avoid the problems arising from superficial highly doped layers, like the previous ones, designers tend to choose low-doped layers, since they have a more uniform doping profile [ 48 ]. In 91 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5. DIGITAL SILICON PHOTOMULTIPLIER CHARACTERIZATION POLY STI n+ nw3v3 p+ SiO2 Depletion region STI n+ N-well 3V3 N-well 3V3 P-Sub p+ diffusion Deep N-well Cathode (b) Depletion region POLY p+ mask POLY STI n+ nw3v3 p+ SiO2 Depletion region STI n+ N-well 3V3 N-well 3V3 P-Sub p+ diffusion Anode Deep N-well Cathode (a) Depletion region POLY p+ mask p+ implant Self-aligned gate ... Figure 5.6: (a) Desired PP/NW3V3 SPAD structure (b) implemented PP/NW3V3 SPAD structure. the case of PW3V3/DNW diodes, photoemission is much more uniform along the borders as figure 5.5-(b) illustrates, even for currents as high as 19mA . Under such bias, a very slight glow can be appreciated at the center of the device. This suggest that a large fraction of the avalanche current is flowing through the guard ring, instead of through the bottom of the device. Qualitatively, these results along with the I-V characteristics indicate that the implemented PP/NW devices are not proper candidates to be part of an array, because of the low electric field uniformity in the p-n junction and the presence of PEB. Nevertheless, devices with equivalent layers are reported in [ 56 ], showing promising results in terms of PDP, DCR, and jitter. As it was discussed in section 2.3, an error during the design of PP/NW3V3 structure leads to PEB. The p+ diffusion mask was extended to enclose the N-well as figure 5.6-(a) illustrates. However, this enclosure was done below the polysilicon, where the poly-silicon acts as a stopping layer, preventing the formation of the diffusion below it as figure 5.6-(b) shows. To overcome this issue in future designs, the poly guard-ring should be reduced or moved away to allow the proper formation of p+ diffusion. On the other hand, the photoemission in the PW3V3/DNW devices seems to be uniform at the borders, but, since low glow is appreciated a the center, a more effective guard ring should be implemented to guarantee that the avalanche is well confined in the active area and no avalanches occurs at the borders. 5.2 Dark Count Rate The DCR characterization of the SiPM provides information about the spatial distribution of noisy diodes and its yield. For obvious reason, this characterization must be carried out SPAD by SPAD under complete darkness with different excess voltages to study the variation of this parameter. Furthermore, the dead time of the devices is set to 5µs , a value high enough to reduce the effect of after-pulsing. Although the magnitude of the dead time is small, the measured DCR must be corrected to estimate the real value of DCR [126]: 92 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5.2. Dark Count Rate 0 20 40 60 Column 10 20 30 40 Row DCR (Hz) 200 400 600 800 1000 Counters Adder tree } Figure 5.7: Dark count rate (DCR) map for PW3V3/DNW devices with Vex =2V and td=5µs. White areas stand for non-working quenching (ISPAD >1mA). DCRr=DCRm 1−DCRmtd (5.1) where DCRr is the estimated real value of DCR, DCRm is the measured DCR and td is the dead time. Since the number of counts is small, the integration time of each sample is 12 seconds. Figure 5.7 represents the DCR for a SiPM with an excess voltage of 2.0V . It can be observed that the DCR is below 200Hz in almost all the SiPM, except for few devices that reach values over 1000Hz . The areas with null data represents the SPADs without proper quench. As a result, these devices are always emitting photons and no counts are registered. At the same time, figure 5.8 represents the DCR for a SiPM with an excess voltage of 3.0V . As it was expected, the current through the SPAD increases at higher excess voltages, consequently, a larger number of quenching circuits are unable to quench the avalanche. Under such bias conditions, the yield degradation can be attributed mainly to the bad design approach used to size the quenching transistor of the AQRC. The design approach followed entails that the avalanche is only quenched after the quenching transistor is switched off, because conductive quenching transistors are used to better detect the avalanche current peaks [ 77 ]. This sets a large avalanche current that modifies the temperature and parameters of the SPAD, the quenching transistor and the comparator. As a result, if the actual excess voltage of the SPADs is reduced, the comparator, in this case implemented with a wide transistor, can not detect the avalanche and switch off the quenching transistor. This leads to a selfsustainable avalanche. While it is true that these DCR maps are indispensable to identify faulty devices that must be turn-off during the SiPM normal operation, it is also true 93 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5. DIGITAL SILICON PHOTOMULTIPLIER CHARACTERIZATION 0 20 40 60 Column 10 20 30 40 Row DCR (Hz) 200 400 600 800 1000 Counters Adder tree } Figure 5.8: DCR map for PW3V3/DNW devices with Vex =3V and td=5µs . White areas stand for non-working quenching (ISPAD >1mA). that it is complicated to study the yield quantitatively. For this reason, DCR is also represented as a cumulative histogram of population. This kind of plots are very useful to interpret which percentage of the total number of SPADs has a DCR equal to or below to a given value. The figure 5.9 shows the cumulative DCR histogram for all the SPADs of a SiPM for different excess voltages and dead time of 5µs , to avoid after-pulsing. The median DCR for the devices biased at 3V is 80Hz , which means a median of 0.4Hz/µm2 . This value is higher than the reported in the state of the art d-SiPM implemented in CMOS technologies [ 56 , 55 ]. With an excess voltage of 2V , the percentage of faulty devices is around 10% , while for excess voltages of 3V , this percentage rises up to 35% . This low yield can be attributed to device self-heating caused by the high currents through the SPADs during avalanche. This, at the same time, means that the number of defective SPADs increases for long integration times, since the selfheating drifts the micro-cell (SPAD and quenching circuit) characteristics over time. In order to validate the previous hypothesis, it is worth studying the effect of temperature on the DCR. To compensate the excess voltage variation with temperature, the data obtained in the previous section was used. The experimental data from figure 5.10 can be fitted to the Arrhenius expression to estimate the activation energy ( EA ) of the charge carriers responsible from triggering the dark counts: DCR =Aexpµ−EA kBT¶(5.2) where A is a constant, EA is the activation energy, kB is the Boltzmann constant and T is the absolute temperature in Kelvin. It can be see that for temperatures 94 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 5.2. Dark Count Rate DCR (Hz) 101 102 103 104 105 Percentage of population (%) 0 10 20 30 40 50 60 70 80 90 100 Vex = 2V; tdead = 5μs Vex = 3V; tdead = 5μs DCRmedian = 80Hz Figure 5.9: Cumulative DCR population for 2432 PW3V3/DNW SPADs at room temperature. SPAD active area is 200µm2and median DCR 0.4Hz/µm2. higher than room temperature, the activation energy is similar to silicon bandgap ( 1.12eV ). Hence, thermal trap assisted Shockley-Read-Hall carriers are responsible of the largest component of DCR [ 127 ]. Moreover, it can be observed that the DCR multiplies it value by ten every 25 – 30K over room temperature. It seems feasible that an increment of p-n junction temperature due to poorly quenched avalanches results in the DCR increment that can be observed in figure 5.9 between 80 – 90% of the the population. On the contrary, when the temperature is below room temperature, the activation energy is smaller and the main component of DCR is band-to-band tunneling [57]. Also, the effects of faulty quenching can be observed with the naked eye because of the photoemission and high current consumption. The figure 5.11-(a) shows a microphotography of a SPAD micro-cell in color. The figure 5.11-(b) shows the same SPAD micro-cell in black and white with a picture of photoemission superimposed. Long exposure, around 14 seconds, was required to obtain the picture of photoemission. The microphotography shows the light produced during continuous avalanches in two SPADs biased with and excess voltage of 1V and a current of 1mA . Such currents are incompatible with SiPM nominal operation, because the number of SPADs per pixel is 2432 . Even with only 10% of active devices, it is experimentally observed that the current consumption is so high that the bias can not be properly supplied because of voltage drop across the entire SiPM. As explained before, this implies that the comparator is unable to detect the avalanche current and to quench it. Once again, this points out that the approach followed to size the quenching transistor is not appropriate for a normal SPAD operation. 95 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be CHAPTER 6 RESULTS AND DISCUSSION This chapter performs a critical assessment of the achievements of this thesis and their connections to the initial global goal. This goal was to design and characterize a functional proof-of-concept SiPM. This global goal called for a detailed architectural study, on the one hand, and for the design of the mixed-signal and logic basic building blocks required for the targeted function, on the other hand. Technology considerations constrained the quest for this goal. First of all, while 3D-stacked, hybrid technologies are a priori better suited for sensory-processing chips, their limited availability and robustness forced using planar technologies. Second, while standard very large-scale integration (VLSI) technologies are advantageous in terms of logic operator density, power and speed, they suffer from having extremely poor SPADs, with DCRs ∼50kHz . These considerations motivated the selection of an 110nm CIS technology which, as shown in this thesis, enables SPADs with ∼50Hz DCR. Still, the characterization data available from the foundry are not complete regarding SPAD behavior. Also, the foundry does not provide technology parameters (such as doping profiles) to perform thorough device engineering using TCAD tools. Some design hypothesis remained hence un-certain until confirmation by measurement form working silicon. Unfortunately, such experimental characterization highlighted a flaw in the theory sustaining AQRC strategies. Basically, resistances were incorrectly estimated based on the foundry data, and this resulted in an incorrect control of positive feedback avalanche phenomena. The re-spinning of the SiPM is hence needed to correct system integration. However, both the architectural studies and the building blocks remain valid assets for such a re-spinning. 103 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 6. RESULTS AND DISCUSSION 6.1 Main achievements Architectural explorations of digital SiPMs have been carried out analytically. To do so, the key functions that a digital SiPM for ToF-PET must perform were identified, namely: to detect and count photons, to measure their arrival time, and to process the scintillation event. Then, optimum points in the design space were encountered. This search has led to the design of a SiPM for ToF-PET in a CIS technology. The complete functionality of the prototype could not be demonstrated under laboratory conditions, due to several flaws in the design of the AQRC. Still, the underlying problems are identified and the thesis contributions have been demonstrated valid. These contributions can be grouped into three different blocks: SPADs, AQRC, and SiPM architectural exploration. 6.1.1 Single Photon Avalanche Diode Two SPAD structures have been implemented in an 110nm CIS technology, whose depletion regions were composed of PP/NW3V3 and PW3V3/DNW layers. The SPADs were designed as parametric cells to simplify the sizing of the active area and the guard ring thickness. This has allowed the implementation of SPADs with different sizes and shapes to study the impact of these parameters in the performance of the device [128]. The characterization of PP/NW3V3 SPADs points out the presence of PEB, as was discussed in chapter 2. On the contrary, the SiPM implemented with PW3V3/DNW SPADs does not suffer from PEB. Characterization shows that the median DCR is around 0.4Hz/µm2 with an excess voltage of 3.0V . Also, the PDP is estimated to be 45% at 470nm with an excess voltage of 3.0V . These are promising results for a wide range of applications, like PET, LiDAR or FLIM to name few. 6.1.2 Active Quenching and Recharge Circuit Despite the promising performance of PW3V3/DNW structure, the quenching circuits implemented in the SiPM are notworking properlybecause of the design approach chosen leads to large avalanche currents, in the order of 1mA , even with excess voltages below 1V . This does not only affect the power consumption, cross-talk, photoemission and after-pulsing, but also the functionality of the digital SiPM itself. For this reason, it is impossible to activate a large number of SPADs at the same time to verify the performance. This flaw is a consequence of the incorrect estimation of the currents and the operation principle of the AQRC circuit. This latter relies on the transition from saturation to cut-offof the quenching transistor used to stop the avalanche. Therefore, if the quenching transistor does not reach the cut-off state, the current through the SPAD can be orders of magnitude higher than the quenching current. Under these circumstances, avalanche photoemission is sustained over 104 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 6.2. Beyond the PhD time. The most straightforward solution is to size a quenching transistor longer than wider. This involves using a transistor with high output impedance in the saturation state to guarantee that the current through the SPAD is always below the quenching current. Similar sizing strategies can be found in [70]. 6.1.3 Architectural Exploration The SiPM architectural exploration has helped to identify the basic functional blocks of a SiPM for a ToF-PET scanner. These blocks support the extraction of information from a scintillation event to enable the reconstructions of the LOR and the annihilation point of the positron. On the one hand, the incident photons must be counted to infer the energy transferred by the gamma photon during its interaction with the crystal. On the other hand, the arrival time of these photons allows to estimate the ToF of gamma photons and, hence, their origin inside the body. Sensitivity is chosen as an optimization figure of merit for architectural exploration. The variables of the optimization are the SPAD size, number of sub-pixels, and the number of SPADs per micro-cell. With the results of the optimization, it is easier for the designer to justify architectural decisions. To the best of the author’s knowledge, the state-of-the-art does not include a similar technique to study the design space of digital SiPM and optimize its performance. However, this technique has some limitations. On the one hand, optimization process relies on the selected figure of merit and the design variables. If the figure of merit does neither have a maximum nor a minimum for the given variables, the optimization is not possible. On the other hand, this approach will be eventually overcome by cost-effective 3D-stacked technologies. In such a scenario, a SPAD custom technology might be used at the top tier, and deep sub-micron technologies might be employed for the front-end and digital processing at the second tier. 6.2 Beyond the PhD 6.2.1 Single Photon Avalanche Diode structure Even though PW3V3/DNW SPADs have a good performance, there is still room for further improvements. Points calling for further analysis include the impact of the guard ring size on the DCR, after-pulsing, jitter, cross-talk, and PEB. Also, the benefits and drawbacks of the biased guard ring structures described in [66, 129] should be studied. On the other hand, the PP/NW3V3 SPADs implemented suffer from PEB which calls for a redesign of the structure. By mistake, the poly layer was extended up to cover the p+ diffusion, which makes the edge of the depletion region to be inside the N-well, leading to PEB. The poly gate acting as a mask for 105 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 6. RESULTS AND DISCUSSION drain-source implants is a common feature call self-aligned gate in silicon-gate technologies. As a consequence, it was impossible to characterize the SiPM implemented with these devices. However, once the origin of the problem is identified, there are still some open questions about the performance of this structure for SiPM. A priori, this structure must have better PDP at shorter wavelengths, and smaller jitter than PW3V3/DNW SPADs, as [56] reports. One of the aspects where more efforts are being made in the design of SiPM for ToF-PET is in the reduction of CTR. In this sense, the contribution of SPAD to the overall CTR is not negligible, in the order of 80–200ps [128]. This means that there is still a lot of work at the circuit level to achieve the time accuracy that satisfies the needs of PET community [19]. 6.2.2 Quenching and Reset Circuit The quenching and reset circuit musthave a fundamental role in the re-spinning. The most promising topologies in terms of power consumption and occupied area are the PQARC, since they control the maximum avalanche current with a current mirror. On the contrary, an AQRC needs larger quenching transistors than PQARC to achieve the same avalanche current. Also, these topologies allow higher excess voltage if cascode transistors are used. This means an improvement in PDP and jitter, at the cost of increasing the DCR. 6.2.3 Time to Digital Converter As for TDC, although the implemented topology has a time resolution smaller than 100ps , the non-idealities found during characterization provide clues for enhancements. The occupied area was reduced to keep the fill factor as high as possible at the expense of increasing substrate and supply noise coupling. The straightforward solution requires properly de-couple the supplies of the ring oscillator and the rest of the logic. Also, the substrate of the ring oscillator can be isolated from the rest of logic with deep n-wells. For the application to benefit from the improvements in ToF, more accurate and precise circuits are required, even more than the implemented topology allows. The industry is pushing towards smaller time resolutions, in the order of tens of picoseconds. This seems to lead to sub-delay line architectures, however, the improvements in time resolution often comes at the expense of long conversion time, high power consumption and occupied area. One of the more attractive alternatives for future designs could be the local passive interpolation [ 87 ]. Nevertheless, power consumption and occupied area must be carefully evaluated. 106 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 6.2. Beyond the PhD 6.2.4 New Silicon Photomultiplier Results of the SiPM characterization have provided a lot of useful information for future designs. The technology seems to have potential to implement future designs based on SPADs, since it performs well in PDP and DCR. Owing to the low DCR, bigger SPADs can be implemented, like the proposed by the optimization process, to increase the fill factor and sensitivity. Experimental characterizations also highlight the shortcoming of the proposed design in terms of testability. In order to reduce these problems, control and test structures must be added in future design. This, along with the previous improvement, will lead to a functional SiPM for ToF-PET. 107 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be CHAPTER 7 CONCLUSIONS This thesis represents a contribution to the design of single-photon detectors for medical applications. The detection of scintillation events, such as those produced inside of a LSO crystal in a ToF-PET scanner, raises two fundamental challenges. On the one hand, sensors must be sensitive enough to work in the single-photon regime. On the other hand, they must measure the arrival time of these photons with resolution in the picosecond range. In this regard, a SiPM architecture has been explored to study analytically the design variables that determine the performance of the sensor. This dissertation addresses different problems related to this architecture and makes the contributions summarized in the bullet points listed below. • Two SPAD structures are selected and implemented to study their performance and assess their suitability for ToF-PET. The PP/NW3V3 structure was expected to have smaller jitter and better PDP for short wavelengths, thus providing better matching to the scintillator spectrum. However, the extension of p+ diffusion beneath the polysilicon guard ring leads to unwanted PEB. As for the PW3V3/DNW structure, the characterization has shown a maximum PDP of 46% and a DCR of 0.4Hz/µm2 with and excess voltage of 3V . All-in-all experimental results indicate that the employed 110nm CIS technology is a convenient choice for further implementations. • Photo-emission characterization has shown that PEB occurs in PP/NW structure with a non-uniform pattern, indicating the presence of nonregular doping. Regarding the PW/DNW structure, it presents a more uniform glow around the whole perimeter, also showing the existence 109 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 7. CONCLUSIONS of PEB but at higher excess voltage. The glow at the border can be a consequence of the small guard ring width of 1µm. • Experimental measurements show that self-sustained avalanches may occur despite the AQRC being sized to stop them based on models and data available from the foundry. Such self-sustained avalanches would result into an experimental power consumption of ∼40W per SiPM, and precluded global characterization. At the conceptual level, the reason for such behavior might be that the AQRC relies on, first, detecting the avalanche and, then, switching off the quenching transistor. Because avalanche currents can grow to milliamperes, delays in performing the quenching action must be very short. To that purpose, the quenching transistor must have a minimum resistance that ensures a passive quenching at any time and PVT variation. • During the design of the TDC based on VCROs, two delay stages were studied: XCP and XCI. The XCI stage provides higher oscillation frequency, while the XCP stage has a lowerphase noise. In terms of TDC performance, XCI stages have a better FOMTDC than XCP stages, with its smallest value at 0.3pJ and 0.5pJ per conversion, respectively. • The results of the TDC characterization agree with post-layout simulations, showing a time resolution below 100ps with a power consumption of 1.1mW . The DNL is ±0.4LSB , while the INL is ±6.1LSB . In terms of TDC performance, there is still room for further improvements. On the one hand, the DNL and INL can be improved by using a PLL to compensate for PVT variations. On the other hand, experimental measurements confirm an expectable trade-off between area occupation and substrate noise coupling. The prototype chip targeted minimum area occupation, thus placing the ring oscillator very close to the rest of the logic. Closer assessment of the trade-off is advisable for smaller coupling between the ring oscillator and the ripple counter. • Architectural studies explored the design space by following a bottomup approach in the quest to determine the dependencies of parameters like sensitivity, SNR, or linearity, on the one hand, and the number of SPADs per micro-cell and the number of sub-pixels per pixel, on the other hand. Besides providing insight into the trade-offs, optimum settings were identified for prototype implementation. 110 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be BIBLIOGRAPHY [1] W. Röntgen and L. Anna Bertha Ludwig; Wellcome Library, Hand Mit Ringen, hand with ring. [Online]. Available: https://wellcomecollection. org/works/wjc8ejn2 [2] S. Derenzo, M. Boswell, M. Weber, and K. Brennan. (2008) Scintillation properties. [Online]. Available: http://scintillator.lbl.gov/ [3] R. Mao, L. Zhang, and R.-Y. Zhu, “Optical and scintillation properties of inorganic scintillators in high energy physics,” Nuclear Science, IEEE Transactions on, vol. 55, no. 4, pp. 2425–2431, Aug 2008. [4] T. Kimble, M. Chou, and B. Chai, “Scintillation properties of LYSO crystals,” in Nuclear Science Symposium Conference Record, 2002 IEEE, vol. 3, Nov 2002, pp. 1434–1437 vol.3. [5] A. M. Thomas and A. K. Banerjee, The History of Radiology. Oxford University Press, 2013. [6] M. Guarnieri, “The age of vacuum tubes: Early devices and the rise of radio communications [historical],” IEEE Industrial Electronics Magazine, vol. 6, no. 1, pp. 41–43, March 2012. [7] S. Siddharth and A. Goyal, “The origin of echocardiography: a tribute to Inge Edler,” Texas Heart Institute journal, vol. 34, no. 4, pp. 431–438, feb 2007. [8] G. Watts, “John Wild,” BMJ, vol. 339, 2009. [Online]. Available: https://www.bmj.com/content/339/bmj.b4428 [9] P. C. Lauterbur, “Image formation by induced local interactions: Examples employing nuclear magnetic resonance,” Nature, vol. 242, no. 5394, pp. 190–191, 1973. [Online]. Available: https://doi.org/10.1038/242190a0 [10] M. M. Ter-Pogossian, M. E. Phelps, E. J. Hoffman, and N. A. Mullani, “A positron-emission transaxial tomograph for nuclear imaging PET,” Radiology, vol. 114, no. 1, pp. 89–98, 1975, pMID: 1208874. [Online]. Available: https://doi.org/10.1148/114.1.89 111 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be BIBLIOGRAPHY [71] G. Boso, M. Buttafava, F. Villa, and A. Tosi, “Low-cost and compact singlephoton counter based on a CMOS SPAD smart pixel,” IEEE Photonics Technology Letters, vol. 27, no. 23, pp. 2504–2507, Dec 2015. [72] F. Zappa, A. Tosi, A. D. Mora, and S. Tisa, “Spice modeling of single photon avalanche diodes,” Sensors and Actuators A: Physical, vol. 153, no. 2, pp. 197–204, 2009. [Online]. Available: http: //www.sciencedirect.com/science/article/pii/S0924424709002581 [73] E. Kamrani, F. Lesage, and M. Sawan, “Efficient premature edge breakdown prevention technique for SiAPD fabrication using standard CMOS process,” IOP International Journal of Semiconductor Science and Technology (JSST), vol. 28, no. 4, p. 045008, 2013. [Online]. Available: http://iopscience.iop.org/0268-1242/28/4/045008 [74] S. Tisa, F. Guerrieri, and F. Zappa, “Variable-load quenching circuit for single-photon avalanche diodes,” Opt. Express, vol. 16, no. 3, pp. 2232–2244, Feb 2008. [Online]. Available: http://www.opticsexpress.org/ abstract.cfm?URI=oe-16-3-2232 [75] M. Gronholm, J. Poikonen, and M. Laiho, “A ring-oscillator-based active quenching and active recharge circuit for single photon avalanche diodes,” in 2009 European Conference on Circuit Theory and Design, Aug 2009, pp. 5–8. [76] A. Rochas, “Single photon avalanche diodes in CMOS technology,” Ph.D. dissertation, PhD thesis, Ecole Polytechnique Federale de Lausanne, 2003. [77] I. Vornicu, R. Carmona-Galán, B. Pérez-Verdú, and A. Rodríguez- Vázquez, “Compact CMOS active quenching/recharge circuit for SPAD arrays,” International Journal of Circuit Theory and Applications, vol. 44, no. 4, pp. 917–928, 2016. [Online]. Available: https: //onlinelibrary.wiley.com/doi/abs/10.1002/cta.2113 [78] S. Lindner, S. Pellegrini, Y. Henrion, B. Rae, M. Wolf, and E. Charbon, “A high-PDE, backside-illuminated SPAD in 65/40nm 3D IC CMOS pixel with cascoded passive quenching and active recharge,” IEEE Electron Device Letters, vol. 38, no. 11, pp. 1547–1550, Nov 2017. [79] I. M. Antolovic, S. Burri, C. Bruschini, R. Hoebe, and E. Charbon, “Nonuniformity analysis of a 65kpixel CMOS SPAD imager,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 57–64, Jan 2016. [80] D. Portaluppi, E. Conca, and F. Villa, “32 x 32 CMOS SPAD imager for gated imaging, photon timing, and photon coincidence,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 24, no. 2, pp. 1–6, March 2018. 118 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Bibliography [81] L. H. C. Braga, L. Pancheri, L. Gasparini, M. Perenzoni, R. Walker, R. K. Henderson, and D. Stoppa, “A CMOS mini-SiPM detector with in-pixel data compression for PET applications,” in 2011 IEEE Nuclear Science Symposium Conference Record, Oct 2011, pp. 548–552. [82] S. Henzler, Time-to-digital Converters. Springer, 2010. [83] M. Z. Straayer and M. H. Perrott, “A multi-path gated ring oscillator TDC with first-order noise shaping,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1089–1098, April 2009. [84] A. A. Hafez and C. K. Yang, “Design and optimization of multipath ring oscillators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 10, pp. 2332–2345, Oct 2011. [85] M. Lee and A. A. Abidi, “A 9b, 1.25ps resolution coarse-fine time-to-digital converter in 90nm CMOS that amplifies a time residue,” in 2007 IEEE Symposium on VLSI Circuits, June 2007, pp. 168–169. [86] J. S. Kim, Y. H. Seo, Y. Suh, H. J. Park, and J. Y. Sim, “A 300MS/s, 1.76ps resolution, 10b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13 µ m CMOS,” IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 516–526, Feb 2013. [87] S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R.Kuenemund, and D. Schmitt- Landsiedel, “A local passive time interpolation concept for variationtolerant high-resolution time-to-digital conversion,” IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1666–1676, July 2008. [88] I. Vornicu, R. Carmona-Galán, and Rodríguez-Vázquez, “In-pixel voltagecontrolled ring-oscillator for phase interpolation in ToF image sensors,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 1906–1909. [89] J. Richardson, R. Walker, L. Grant, D. Stoppa, F. Borghetti, E. Charbon, M. Gersbach, and R. K. Henderson, “A 32x32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging,” in 2009 IEEE Custom Integrated Circuits Conference. IEEE Solid-State Circuits Society, Sept 2009, pp. 77–80. [90] Z. Cheng, X. Zheng, M. J. Deen, and H. Peng, “Recent developments and design challenges of high-performance ring oscillator CMOS time-to- digital converters,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 235–251, Jan 2016. [91] J. A. McNeill and D. Ricketts, The Designer’s Guide to Jitter in Ring Oscillators, 1st ed. Springer Publishing Company, Incorporated, 2009. 119 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be BIBLIOGRAPHY [92] D. Bronzi, F. Villa, S. Tisa, A. Tosi, F. Zappa, D. Durini, S. Weyers, and W. Brockherde, “100 000 Frames/s 64x32 single-photon detector array for 2D imaging and 3D ranging,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 20, no. 6, pp. 354–363, Nov 2014. [93] M. Perenzoni, D. Perenzoni, and D. Stoppa, “A 64 × 64-pixels digital silicon photomultiplier direct TOF sensor with 100-MPhotons/s/pixel background rejection and imaging/altimeter mode with 0 . 14% precision up to 6km for spacecraft navigation and landing,” IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 151–160, Jan 2017. [94] A. Akindinov and et al., “Performance of the ALICE time-of-flight detector at the LHC,” The European Physical Journal Plus, vol. 128, no. 4, p. 44, 2013. [Online]. Available: https://doi.org/10.1140/epjp/i2013-13044-x [95] D. Tyndall, B. R. Rae, D. D. Li, J. Arlt, A. Johnston, J. A. Richardson, and R. K. Henderson, “A high-throughput time-resolved mini-silicon photomultiplier with embedded fluorescence lifetime estimation in 0.13 µ m CMOS,” IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 6, pp. 562–570, Dec 2012. [96] J. Jalil, M. B. I. Reaz, and M. A. M. Ali, “CMOS differential ring oscillators: Review of the performance of CMOS ROs in communication systems,” IEEE Microwave Magazine, vol. 14, no. 5, pp. 97–109, July 2013. [97] B. Razavi, Design of Monolithic Phase Locked Loops and Clock Recovery Circuits: A Tutorial. IEEE, 1996. [Online]. Available: https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5263316 [98] W. Bae, H. Ju, K. Park, S. Y. Cho, and D. K. Jeong, “A 7.6mW, 414fs RMS- jitter 10GHz phase-locked loop for a 40Gb/s serial link transmitter based on a two-stage ring oscillator in 65nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2357–2367, Oct 2016. [99] I. Vornicu, R. Carmona-Galán, and Rodríguez-Vázquez, “Arrayable voltage-controlled ring-oscillator for direct time-of-flight image sensors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. PP, no. 99, pp. 1–14, 2017. [100] H. Chen and R. Geiger, “Transfer characterization of CMOS ring voltage controlled oscillators,” in Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257), vol. 1. IEEE Circuits and Systems Society, 2001, pp. 66–70 vol.1. [101] I. Nissinen, A. Mantyniemi, and J. Kostamovaara, “A CMOS time-to-digital converter based on a ring oscillator for a laser radar,” in ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705). IEEE Solid-State Circuits Society, Sept 2003, pp. 469–472. 120 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Bibliography [102] M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. Henderson, F. Borghetti, D. Stoppa, and E. Charbon, “A parallel 32x32 time-to-digital converter array fabricated in a 130nm imaging CMOS technology,” in 2009 Proceedings of ESSCIRC. ESSCIRC, Sept 2009, pp. 196–199. [103] Z. Cheng, M. J. Deen, and H. Peng, “A low-power gateable vernier ring oscillator time-to-digital converter for biomedical imaging applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 10, no. 2, pp. 445–454, April 2016. [104] C. Veerappan, J. Richardson, R. Walker, D. U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R. K. Henderson, and E. Charbon, “A 160x128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter,” in 2011 IEEE International Solid- State Circuits Conference. IEEE Solid-State Circuits Society, Feb 2011, pp. 312–314. [105] M. Perenzoni, L. Gasparini, and D. Stoppa, “Design and characterization of a 43.2ps and PVT-resilient TDC for single-photon imaging arrays,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 4, pp. 411–415, April 2018. [106] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 331–343, Mar 1996. [107] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb 1998. [108] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 790–804, June 1999. [109] A. A. Abidi, “Phase noise and jitter in CMOS ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1803–1816, Aug 2006. [110] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. Oxford University Press, 3rd Edition, 2011. [111] J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 1965–1971, Nov 1994. [112] D. Xie, M. Cheng, and L. Forbes, “SPICE models for flicker noise in n- MOSFETs from subthreshold to strong inversion,” IEEE Transactions on 121 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be BIBLIOGRAPHY Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp. 1293–1303, Nov 2000. [113] L. K. J. Vandamme and F. N. Hooge, “What do we certainly know about 1 / f noise in mosts?” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3070–3085, Nov 2008. [114] K. Kim, Y. H. Kim, W. Yu, and S. Cho, “A 7bit, 3.75ps resolution two-step time-to-digital converterin 65nm CMOS using pulse-train time amplifier,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 1009–1017, April 2013. [115] P. Napolitano, A. Moschitta, and P. Carbone, “A survey on time interval measurement techniques and testing methods,” in 2010 IEEE Instrumentation Measurement Technology Conference Proceedings. IEEE Instrumentation Measurement Technology Conference Proceedings, May 2010, pp. 181–186. [116] I. Vornicu, R. Carmona-Galán, and Rodríguez-Vázquez, “On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique,” in IEEE International Symposium on Circuits and Systems (ISCAS). IEEE Circuits and Systems Society, May 2015, pp. 1102–1105. [117] N. Zorzi, M. Melchiorri, A. Piazza, C. Piemonte, and A. Tarolli, “Development of large-area silicon photomultiplier detectors for PET applications at FBK,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 636, no. 1, Supplement, pp. S208 – S213, 2011, 7th International Hiroshima Symposium on the Development and Application of Semiconductor Tracking Detectors. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0168900210009654 [118] M. W. Fishburn and E. Charbon, “System tradeoffs in gamma-ray detection utilizing SPAD arrays and scintillators,” IEEE Transactions on Nuclear Science, vol. 57, no. 5, pp. 2549–2557, Oct 2010. [119] M. Tétrault, A. C. Therrien, W. Lemaire, R. Fontaine, and J. Pratte, “TDC array tradeoffs in current and upcoming digital SiPM detectors for Time- of-Flight PET,” IEEE Transactions on Nuclear Science, vol. 64, no. 3, pp. 925–932, March 2017. [120] F. Acerbi, A. Gola, V. Regazzoni, G. Paternoster, G. Borghi, N. Zorzi, and C. Piemonte, “High efficiency, ultra-high-density silicon photomultipliers,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 24, no. 2, pp. 1–8, March 2018. 122 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Bibliography [121] N. A. W. Dutton, S. Gnecchi, L. Parmesan, A. J. Holmes, B. Rae, L. A. Grant, and R. K. Henderson, “11.5 a time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter,” in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, Feb 2015, pp. 1–3. [122] S. Gnecchi, N. A. W. Dutton, L. Parmesan, B. R. Rae, S. Pellegrini, S. J. McLeod, L. A. Grant, and R. K. Henderson, “Digital silicon photomultipliers with OR/XOR pulse combining techniques,” IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1105–1110, March 2016. [123] M. A. Karami, “Deep-submicron CMOS single photon detectors and quantum effects,” Ph.D. dissertation, PhD thesis, Delft University of Technology, 2011. [124] C. Veerappan and E. Charbon, “A low dark count p-i-n diode based SPAD in CMOS technology,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 65–71, Jan 2016. [125] M. Gersbach, J. Richardson, E. Mazaleyrat, S. Hardillier, C. Niclass, R. Henderson, L. Grant, and E. Charbon, “A low-noise single-photon detector implemented in a 130nm CMOS imaging process,” Solid-State Electronics, vol. 53, no. 7, pp. 803–808, 2009. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0038110109000896 [126] F. Villa, D. Bronzi, Y. Zou, C. Scarcella, G. Boso, S. Tisa, A. Tosi, F. Zappa, D. Durini, S. Weyers, U. Paschen, and W. Brockherde, “CMOS SPADs with up to 500 µ m diameter and 55% detection efficiency at 420 nm,” Journal of Modern Optics, Volume 61, Issue 2, 2014, pp.102-115, vol. 61, pp. 102–115, Jan 2014. [Online]. Available: https://ui.adsabs.harvard.edu/abs/2014JMOp...61..102V [127] E. A. G. Webster and R. K. Henderson, “A TCAD and spectroscopy study of dark count mechanisms in single-photon avalanche diodes,” IEEE Transactions on Electron Devices, vol. 60, no. 12, pp. 4014–4019, Dec 2013. [128] I. Vornicu, F. Bandi, R. Carmona-Galán, and Ángel Rodríguez-Vázquez, “Low-noise and high-efficiency near-IR SPADs in 110nm CIS technology,” in 2019 49th European Solid-State Device Research Conference (ESSDERC), Sep. 2019, pp. 250–253. [129] N. D ' Ascenzo and Q. Xie, “Possible layout solutions for the improvement of the dark rate of Geiger mode avalanche structures in the GLOBALFOUNDRIES BCDLITE 0.18 um CMOS technology,” Journal of Instrumentation, vol. 13, no. 04, pp. T04007–T04007, apr 2018. [Online]. Available: https://doi.org/10.1088/1748-0221/13/04/T04007 123 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be SCIENTIFIC PUBLICATIONS In the following, the list of contributions to the scientific bibliography made in this dissertation is provided. Workshops [1] F. N. Bandi, I. Vornicu, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “VCRO-Based TDcs in Submicron CIS Technology,” in 6th Workshop on Architecture of Smart Cameras (WASC), Jun. 5-6, 2017, Córdoba, Spain. [2] F. N. Bandi, I. Vornicu, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “Digital Silicon Photomultiplier Design Flow,” in 7th Workshop on Architecture of Smart Cameras (WASC), Jun. 27-28, 2018, Coimbra, Portugal. Seminars [1] F. N. Bandi, “Single Photon Detection in CMOS technologies,” in 1st Physics Doctoral Meeting of the Colegio Doctoral de Tordesillas, Nov. 11-13, 2017, Granada, Spain. Conferences [1] F. N. Bandi, I. Vornicu, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “Design of a compact and low-power TDC for an array of SiPM’s in 110nm CIS technology,” in 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Jun. 12-15, 2017, Giardini Naxos, Italy, pp. 257-260. [2] I. Vornicu, F. N. Bandi, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology,” in 2019 49th European Solid State Device Research Conference (ESSDERC), Sept. 23-26, 2019, Krakow, Poland, pp. 250-253. 125 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be SCIENTIFIC PUBLICATIONS Journals [1] I. Vornicu, F. N. Bandi, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “A CMOS Digital SiPM With Focal-Plane Light-Spot Statistics for DOI Computation,” in IEEE Sensors Journal, vol. 17, no. 3, pp. 632-643, 1 Feb.1, 2017. Under Review [1] R. Ballabriga, J. Alozy, F. N. Bandi, M. Campbell, N. Egidos, J. M. Fernandez-Tenllado, E.H.M. Heijne, Fellow, IEEE, I. Kremastiotis, X. Llopart, B. J. Madsen, D. Pennicard, V. Sriskaran and L. Tlustos, “Photon Counting Detectors for X-ray Imaging with Emphasis on CT,” in IEEE Transactions on Radiation and Plasma Medical Sciences. [1] I. Vornicu, F. N. Bandi, R. Carmona-Galán, and Ángel Rodríguez- Vázquez, “Compact Macro-Cell with OR Pulse Combining for Low Power Digital-SiPM,” in IEEE Sensors Journal. 126 Código seguro de Verificación : GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be | Puede verificar la integridad de este documento en la siguiente dirección : https://sede.administracionespublicas.gob.es/valida ÁMBITOPREFIJO CSV FECHA Y HORA DEL DOCUMENTO GEISER GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be 31/03/2020 09:53:25 Horario peninsular Nº registro DIRECCIÓN DE VALIDACIÓN O00008744e2000017793 https://sede.administracionespublicas.gob.es/valida GEISER-850a-5af3-75df-4bf9-bd5d-d519-c328-e9be