Integration of nanoscale memristor synapses in neuromorphic computing architectures

Integration of nanoscale memristor synapses in neuromorphic computing architectures Giacomo Indiveria,1, Bernabe Linares-Barrancob, Robert Legensteinc, George Deligeorgisd, and Themistoklis Prodromakise aInstitute of Neuroinformatics, University of Zurich and ETH Zurich, Zurich, Switzerland bInstituto Microelectronica Sevilla (IMSE-CNM-CSIC), Sevilla, Spain cInstitute for Theoretical Computer Science, Graz University of Technology, Graz, Austria dCNRS-LAAS and Univ de Toulouse, 7 avenue du colonel Roche, F-31400 Toulouse, France eCenter for Bio-Inspired Technology, Department of Electrical and Electronic Engineering, Imperial College London, United Kingdom E-mail: 1[email protected] Abstract. Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low-power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic-computing approaches that can best exploit the properties of memristor and-scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault-tolerant by design. arXiv:1302.7007v1 [cs.ET] 27 Feb 2013 Neuromorphic nanoscale memristor synapses 2 1. Introduction The idea of linking the type of information processing that takes place in the brain with theories of computation and computer science (something commonly referred to as neuro-computing) dates back to the origins of computer science itself [1,2]. Neuro-computing has been very popular in the past [3,4], eventually leading to the development of abstract artificial neural networks implemented on digital computers, useful for solving a wide variety of practical problems [5,6,7,8,9]. However, the field of neuromorphic engineering is a much younger one [10]. This field has been mainly concerned with hardware implementations of neural processing and sensorymotor systems built using Very Large Scale Integration (VLSI) electronic circuits that exploit the physics of silicon to reproduce directly the biophysical processes that underlie neural computation in real neural systems. Originally, the term “neuromorphic” (coined by Carver Mead in 1990 [11]) was used to describe systems comprising analog integrated circuits, fabricated using standard Complementary Metal Oxide Semiconductor (CMOS) processes. In recent times, however, the use of this term has been extended to refer to hybrid analog/digital electronic systems, built using different types of technologies. Indeed, both artificial neural networks and neuromorphic computing architectures are now receiving renewed attention thanks to progress in Information and Communication Technologys (ICTs) and to the advent of new promising nanotechnologies. Some of present day neuro-computing approaches attempt to model the fine details of neural computation using standard technologies. For example, the Blue Brain project, launched in 2005, makes use of a 126kW Blue Gene/P IBM supercomputer to run software that simulates with great biological accuracy the operations of neurons and synapses of a rat neocortical column [12]. Similarly, the BrainScaleS EU-FET FP7 project aims to develop a custom neural supercomputer by integrating standard CMOS analog and digital VLSI circuits on full silicon wafers to implement about 262 thousand Integrate-and-Fire (I&F) neurons and 67 million synapses [13]. Although configurable, the neuron and synapse models are hardwired in the silicon wafers, and the hardware operates about 10000 times faster than real biology, with each wafer consuming about 1kW power, excluding all external components. Another large-scale neuro-computing project based on conventional technology is the SpiNNaker project [14]. The SpiN- Naker is a distributed computer, which interconnects conventional multiple integer precision multi ARM core chips via a custom communication framework. Each SpiNNaker package contains a chip with 18 ARM9 Central Processing Units (CPUs) on it, and a memory chip of 128 Mbyte Synchronous Dynamic Random Access Memory (DRAM). Each CPU can simulate different neuron and synapse models. If endowed with simple synapse models, a single SpiNNaker device ARM core can simulate the activity of about 1000 neuron in real time. More complex synapse models (e.g. with learning mechanisms) would use up more resources and decrease the number of neurons that could be simulated in real-time. The latest SpiNNaker board contains 47 of these packages, and the aim is to assemble 1200 of these boards. A full SpiNNaker system of this size Neuromorphic nanoscale memristor synapses 3 would consume about 90 kW. The implementation of custom large-scale spiking neural network hardware simulation engines is being investigated also by industrial research groups. For example, the IBM group led by D.S. Modha recently proposed a digital “neurosynaptic core” chip integrated using a standard 45 nm Silicon on Insulator (SOI) process [15]. The chip comprises 256 digital I&F neurons, with 1024×256 binary valued synapses, configured via a Static Random Access Memory (SRAM) cross-bar array, and uses an asynchronous event-driven design to route spikes from neurons to synapses. The goal is to eventually integrate many of these cores onto a single chip, and to assemble many multi-core chips together, to simulate networks of simplified spiking neurons with human-brain dimensions (i.e. approximately 1010 neurons and 1014 synapses) in realtime. In the mean time, IBM simulated 2.084 billion neurosynaptic cores containing 53 ×1010 neurons and 1.37 ×1014 synapses in software on the Lawrence Livermore National Lab Sequoia supercomputer (96 Blue Gene/Q racks), running 1542×slower than real time [16], and dissipating 7.9 MW. A diametrically opposite approach is represented by the Neurogrid system [17]. This system comprises an array of sixteen 12 ×14 mm2 chips, each integrating mixed analog neuromorphic neuron and synapse circuits with digital asynchronous event routing logic. The chips are assembled on a 16.5×19 cm2 Printed Circuit Board (PCB), and the whole system can model over one million neurons connected by billions of synapses in real-time, and using only about 3 W of power [18]. As opposed to the neuro-computing approaches that are mainly concerned with fast and large simulations of spiking neural networks, the Neurogrid has been designed following the original neuromorphic approach, exploiting the characteristics of CMOS VLSI technology to directly emulate the biophysics and the connectivity of cortical circuits. In particular, the Neurogrid network topology is structured by the data and results obtained from neuro-anatomical studies of the mammalian cortex. While offering less flexibility in terms of connectivity patterns and types of synapse/neuron models that can be implemented, the Neurogrid is much more compact and dissipates orders of magnitude less power than the other neuro-computing approaches described above. All these approaches have in common the goal of attempting to simulate large numbers of neurons, or as in the case of Neurogrid, to physically emulate them with fine detail. Irrespective of the approach followed, nanoscale synapse technologies and devices have the potential to greatly improve circuit integration densities and to substantially reduce power-dissipation in these systems. Indeed, recent trends in nanoelectronics have been investigating emerging low-power nanoscale devices for extending standard CMOS technologies beyond the current state-of-art [19]. In particular, Resistive Random Access Memory (ReRAM) is regarded as a promising technology for establishing nextgeneration non-volatile memory cells [20], due to their infinitesimal dimensions, their capacity to store multiple bits of information per element and the minuscule energy required to write distinct states. The factors driving this growth are attributed to the devices’ simple (two terminals) and infinitesimal structure (state-of-art is down to 10×10 nm2[21]) and ultra-low power consumption (<50 fJ/bit) that so far are unmatched by conventional VLSI circuits. Neuromorphic nanoscale memristor synapses 4 Various proposals have already been made for leveraging basic nanoscale ReRAM attributes in reconfigurable architectures [22], neuro-computing [23] and even artificial synapses [24,25,26,27,28]. However the greatest potential of these nanoscale devices lies in the wide range of interesting physical properties they possess. Neuromorphic systems can harness the interesting physics being discovered in these new nanodevices to emulate the biophysics of real synapses and neurons and reproduce relevant computational primitives, such as state-dependent conductance changes, multi-level stability and stochastic state changes in large-scale artificial neural systems. In this paper we first describe how nanoscale synaptic devices can be integrated into neuro-computing architectures to build large-scale neural networks, and then propose a new hybrid memristor-CMOS neuromorphic circuit that emulates the behavior of real synapses, including their temporal dynamics aspects, for exploring and understanding the principles of neural computation and eventually building brain-inspired computing systems. 2. Solid-state memristors ReRAM cells are nowadays classified as being memory-resistors [29], or memristors for short, that have first been conceptually conceived in 1971 by Leon Chua [30]; with the first biomimetic applications presented at the same time. The functional signature of memristors is a pinched hysteresis loop in the current-voltage (i-v) domain when excited by a bipolar periodic stimulus [31]. Such hysteresis is typically noticed for all kind of devices/materials in support of a discharge phenomenon that possess certain inertia, causing the value of a physical property to lag behind changes in the mechanism causing it, and has been common both to large scale [32] as well as nanoscale dissipative devices [33]. 2.1. Emerging nanodevices as synapse mimetics The analogy of memristors and chemical synapses is made on the basis that synaptic dynamics depend upon the discharge of neurotransmitters within a synaptic cleft (see Fig. 1a), in a similar fashion that “ionic species” can be displaced within any inorganic barrier (see Fig. 1b). TiO2-based memristor models [33,34] hypothesized that solidstate devices comprise a mixture of TiO2phases, a stoichiometric and a reduced one (TiO2−x), that can facilitate distinct resistive states via controlling the displacement of oxygen vacancies and thus the extent of the two phases. More recently however it was demonstrated that substantial resistive switching is only viable through the formation and annihilation of continuous conductive percolation channels [35] that extend across the whole active region of a device, shorting the top and bottom electrodes; no matter what the underlying physical mechanism is. An example of I-V characteristics of TiO2-based memristors is depicted in Fig. 2a. In this example, consecutive positive voltage sweeps cause any of the cross-bar type Neuromorphic nanoscale memristor synapses 5 (a) (b) Figure 1: (a) Cross-section of a chemical synapse, illustrating the discharge of neurotransmitters within a synaptic cleft originating from a pre-synaptic neuron. (b) Schematic representation of solid-state memristors where ionic species can be displaced within a device’s insulating medium, transcribing distinct resistive states, by application of electrical stimuli on the top or bottom electrodes of the device. devices [36] shown in the inset of Fig. 2a to switch from a High-Resistive State (HRS) to Low-Resistive States (LRSs). When the polarity of the voltage sweeps is however inverted, the opposite trend occurs, i.e. the device toggles from LRS to HRS consecutively (as indicated by the corresponding arrows). These measured results are consistent with analogous ones proposed by other research groups [37,38,39] and demonstrate the devices’ capacity for storing a multitude of resistive states per unit cell, with the programming depending on the biasing history. This is further demonstrated in Fig. 2b, by applying individual pulses of -3 V in amplitude and 1 µsec long for programming a single memristor at distinct non-volatile resistive states. In this scenario, the solid-state memristor emulates the behavior of a depressing synapse [40,41]; the inverse, i.e. short-term potentiation is also achievable by alternating the polarity of the employed pulsing scheme. The development of nanoscale dynamic computation elements may notably benefit the establishment of neuromorphic architectures. This technology adds substantially on computation functionality, due to the rate-dependency of the underlying physical switching mechanisms. At the same time it can facilitate unprecedented complexity due to the capacity of storing and processing spiking events locally. Moreover, exploiting the nanoscale dimensions and architecture simplicity of solid-state memristor implementations could substantially augment the number of cells per unit area, effectively enhancing the systems’ redundancy for tolerating issues that could stem from device mismatch and low-yields [42]. Neuromorphic nanoscale memristor synapses 6 (a) (b) Figure 2: Characterization of a TiO2-based solid-state memristor. (a) I-V characteristics for consecutive voltage sweeping. Positive (negative) biasing renders an increase (decrease) in the device’s conductance. Inset of (a) depicts a 25 ×25 array crossbar type memristors comprising of TiO2active areas of 1 ×1µm2. These cells can be programmed at distinct resistive states as shown in (b) by employing -3V and 1µsec wide pulses, while evaluation of the device’s states is performed at 0.9V. 2.2. Memristor scaling Resistive memory scaling has been intensively investigated for realization of nanosized ReRAM [43]. In principle memristors may be scaled aggressively well below conventional RAM cells due to their simplicity: fabrication-wise memristors typically rely on a Metal Insulator Metal (MIM) structure. The memristor action occurs in the insulating material. Scaling down the thickness of such a material will reduce both the required set voltage as well as the read voltage used during operation. In this context, thickness figures of a few nano meters have been demonstrated and operating voltages below 1 V have been shown [44] with a switching energy of a few fJ [45]. Furthermore, reducing the active device area by down-scaling the electrodes leads to current scaling, as well as increased device density. Both of these effects are favorable for high complexity circuits. Currently even though single memristor devices as small as 10 ×10 nm have been demonstrated [21], cross-bar arrays are the most commonly used architecture [46,36] to organize large numbers of individually addressable memristive synapses in a reduced space. In Fig. 3we show a large array of nanoscale memristors that we fabricated using electron beam lithography. This array consists of a continuous Pt bottom electrode and an active layer deposited by Sputtering. Subsequently, several arrays of nano-memristors with a size ranging from 20 to 50 nm were defined using E-beam lithography on PMMA and lift-off of the top Platinum electrode. The array shown here comprises 256 ×256 devices with a periodicity of 200 nm. To access each individual device a conductive Atomic Force Microscope (AFM) tip was used. Such a structure has been used to study the variability of the fabricated devices. Using E-beam lithography for both the top and bottom electrodes a fully interconnected cross bar structure with similar size and pitch may be fabricated. Neuromorphic nanoscale memristor synapses 7 Figure 3: SEM micrograph of a large nanosized memristor array. Top inset shows a zoom-in of the top left corner where the individual devices are distinguished. Bottom left inset shows an AFM image of a small part of the array. Individual devices are addressed by placing a conductive AFM tip on the top electrode. 3. Memristor-based neuro-computing architectures Memristive devices have been proposed as analogs of biological synapses. Indeed, memristors could implement very compact but abstract models of synapses, for example representing a binary “potentiated” or “depressed” state, or storing an analog “synaptic weight” value [47]. In this framework, they could be integrated in large and dense crossbar arrays [48] to connect large numbers of silicon neurons [49], and used in a way to implement spike-based learning mechanisms that change their local conductance. In [25,24] the authors proposed a scheme where neurons can drive memristive synapses to implement a Spike-Timing Dependent Plasticity (STDP) [50] learning scheme by generating single pairs of pre- and post-synaptic spikes in a fully asynchronous manner, without any need for global or local synchronization, thus solving some of the problems that existed with previously proposed learning schemes [51,28]. The main idea is the following: when no spike is generated, each neuron maintains a constant reference voltage at both its input and output terminals. During spike generation, each neuron forces a pre-shaped voltage waveform at both its input and output terminals, as shown in Fig. 4a, to update the synaptic weight value stored in the memristor state. Since memristors change their resistance when the voltages at their terminals exceed some defined thresholds, it is possible to obtain arbitrary STDP weight update functions, including biologically plausible ones, as the one shown in Fig. 4b [50]. Moreover by properly shaping the spike wave-forms of both pre- and post-synaptic spikes it is possible to change the form of the STDP learning function, or to even make it evolve in time as Neuromorphic nanoscale memristor synapses 8 memristor forward spike backward spike pre−synaptic neuron post−synaptic neuron (a) −80 −40 0 40 80 −80 −60 −40 −20 0 20 40 60 80 100 ∆T (ms) ξ (%) (b) (c) CMOS neuron array synaptic fabric ultra-dense spike shaping circuit Tuning params. spike integrator comm. AER to Router spikes to synaptic fabric synaptic fabric spikes from Router Neuron Support Test & Reconf. Nano scale AER Processor AER Chip Processor Router Memristor (d) Figure 4: Single memristor synapse concept.(a) One Memristor synapse with pre- and post-synaptic pulse-shaping neuron circuits. (b) Example of a STDP weight update learning function ξ(∆T), where ∆Trepresents the difference between the timing of the post-synaptic and pre-synaptic spikes. (c) Circuit architecture comprising three neuron layers connected by means of synaptic crossbars. (d) Hybrid memristor/CMOS neurons and AER 2D chip architecture for spike/event routing and processing. Parts of this figure were adapted from [24]. learning progresses [52,25]. Fully interconnected or partially interconnected synaptic crossbar arrays, as illustrated in Fig. 4c, could facilitate hierarchical learning neural network architectures. Since there is no need for global synchronization, this approach could be extended to multi-chip architectures that transmit spikes across chip boundaries using fully asynchronous timing. For example, a common asynchronous communication protocol that has been used in neuromorphic systems is based on the Address Event Representation (AER) [53,54]. In this representation, each spiking neuron is assigned an address, and when the neuron fires an address-event is put on a digital bus, at the time that the spike is emitted. In this way time represent itself, and information is encoded in real-time, in the inter-spike intervals. By further exploiting hybrid CMOS/memristor chip fabrication techniques [55], this approach could be easily scaled up to arbitrarily large networks (e.g., see Fig. 4d). Following this approach each neuron processor would be placed in a 2D grid fully, or partially interconnected through memristors. Each neuron would perform incoming spike aggregation, provide the desired pre- and post- Neuromorphic nanoscale memristor synapses 9 synaptic (programmable) spike waveforms, and communicate incoming and outgoing spikes through AER communication circuitry. Using state-of-the-art CMOS technology, it is quite realistic to provide in the order of a million such neurons per chip with about 104synapses per neuron. For example, by using present day 40 nm CMOS technology it is quite realistic to fit a neuron within a 10µm ×10µ m area. This way, a chip of about 1cm2could host of the order of one million neurons. At the same time, for the nano wire fabric deposited on top of CMOS structures, present day technology can easily provide nano wires of 100nm pitch [21]. This would allow to integrate about 104 synapses on top of the area occupied by each CMOS neuron. Similarly, at the PCB level, it is possible to envisage that a 100-chip PCB could host about 108neurons, and 40 of these PCBs would emulate 4 billion neurons. In these large-scale systems the bottleneck is largely given by the spike or event communication limits. To cope with these limits such chips would inter-communicate through nearest neighbors, exploiting 2D-grid network-on-chip (NoC) and network-on-board (NoB) principles. For example, in [56] the authors proposed a very efficient multi-chip inter-communication scheme that distributes event traffic over a 2D mesh network locally within each board through interchip high speed buses. Reconfigurability and flexibility would be ensured by defining the system architecture and topology through in-chip routing tables. Additionally, by arranging the neurons within each chip in a local 2D mesh with in-chip inter-layer event communication, it is possible to keep most of the event traffic inside the chips. At the board level, the 2D mesh scheme would allow for a total inter-chip traffic in the order of Ev= 4Nch ×Epp, where Nch = 100 is the number of chips per board, Epp is the maximum event bandwidth per inter-chip bus (which we may assume to be around 100 Meps - mega events per second), and 4 reflects the fact that each chip is connected to its four nearest neighbors [56]. With these numbers, the maximum traffic per board would be in the order of Ev≈4×1010eps, which is about 400 eps per neuron just for inter-chip event exchange. In practice, inter-board traffic could be much sparser, if the system is partitioned efficiently. Such numbers are quite realistic for present day CMOS technology, and the approach is scalable. Regarding power consumption of the communication overhead, we can use as reference some recent developments for event-based fully bit-serial inter-chip transmission schemes over differential micro strips [57,56], where consumption is proportional to communication event rate. Each link would consume in the order of 40 mA at 10 Meps rate (this includes driver and receiver pad circuits [57] as well as serializers and deserializers [58]). If each neuron fires at an average rate of 1 Hz, and if each chip has 1 million neurons, the current consumption of the communication overhead would be about 4 mA per chip. If voltage supply is in the 1-2 V range, this translates into 4-8 mW per chip. For a 100 chip PCB the inter-chip communication overhead power consumption would thus be about 400-800 mW, for 1 Hz average neuron firing rate. Neuromorphic nanoscale memristor synapses 16 information from the reservoir. In this way, arbitrary fading memory filters or even arbitrary dynamical systems (in the case when the readout elements provide feedback to the dynamical system) can be learned. One long-standing disadvantage of traditional RC was that readouts had to be trained in a supervised manner. In other words, a teacher signal was necessary that signals at each time point the desired output of readouts. In many real-world applications, such a teacher signal is not available. For example, if the task for a robot controller is to produce some motor trajectory in order to produce a desired hand movement, the exact motor commands that perform this movement are in general not known. What can be evaluated however is the quality of the movement. Recently, it has been demonstrated that noisy readouts can be trained with a much less informative reward signal, which just indicates whether some measure of performance of the system has recently increased [84]. Of course, such reward-based learning can in general be much slower than the pure supervised approach (see, e.g.,[89]). The actual slowdown however depends on the task at hand, and it is interesting that for a set of relevant tasks, reward-based learning works surprisingly fast [84]. Since the functionality of reservoirs depends on its general dynamical behavior and not on precise implementation of its components, RC is an attractive computational paradigm for circuits comprised of nanoscale elements affected by variability, such as the one proposed in Section 4.2. In fact, if the reservoir is composed by a large number of simple interacting dynamic elements – the typical scenario – then heterogeneity of these elements is an essential requirement for ideal performance. Parameter heterogeneity is also beneficial in so-called ensemble learning techniques [90]. It is well-known that the combination of models with heterogeneous predictions for the same data-set tends to improve overall prediction performance [91]. Hence, heterogeneity of computational elements can be a real benefit for learning. Examples for ensemble methods are random forests [92], bagging [93], and boosting [94]. 6. Discussion and conclusions Memristors, and in particular nanoscale solid state implementations, represent a promising technology, baring benefits for emerging memory storage as well as revisiting conventional analog circuits [95]. Given their low-power and small-scale characteristics, researchers are considering their application also in large-scale neural networks for neurocomputing applications. However, the fabrication of large-scale nano-scale cross-bar arrays involves several issues that are still open: the realization of nano sized electrodes requires nanopatterning [96] techniques, such as Electron Beam Lithography (EBL) or Nano-Imprint Lithography (NIL) [97]. This directly correlates to reduced electrode cross section which results in increasing resistance. As electrode resistance scales with length, this can rapidly become a critical issue for fully interconnected nanoscale crossbar structures. Furthermore, down-scaling the electrode size to reduce the device active area requires simultaneous down-scaling of the thickness of the metalizations due to fabrication concerns. This in turn further increases the resistance of the electrodes, Neuromorphic nanoscale memristor synapses 17 much like the interconnects in modern CMOS circuitry. These factors introduce a large offset in the write voltages required to change the state of ReRAMs cells that depends on the position of the cell in the array. This problem is especially critical in neurocomputing architectures where these cells represent synapses, as the offsets directly affect the weight-update and learning mechanisms. Integrating memristors as synapse elements in large-scale neuro-computing architectures also introduces the significance of process variability in memristor dimensions [98], which in turn introduces a significant amount of variability in the characteristics of the synapse properties. In addition to their large variability, another important issue relating to these types of synapses, that is still ignored in the vast majority of neuro-computing studies, is the effect of limited resolution in memristive states. In particular, it is not known what the trade-off between desired synaptic weight resolution and memristor size is. And it is not known to what extent the multi-step synaptic weight model holds true for aggressively down-scaled memristor sizes. These scaling, integration, and variability issues are serious limiting factors for the use of memristors in conventional neuro-computing architectures. Nonetheless, biological neural systems are an existence proof that it is possible to implement robust computation using nanoscale unreliable components and non-von Neumann computing architectures. In order to best exploit these emerging nanoscale technologies for building compact, low-power, and robust artificial neural processing systems it is important to understand the (probabilistic) neural and cortical principles of computation and to develop at the same time, following a co-design approach, the neuromorphic hardware computing substrates that support them. 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