Tool for fast mismatch analysis of analog circuits

A Tool for Fast Mismatch Analysis of Analog Circuits R. Rodriguez-Macias, F.V. Fernandez, A. Rod.riguez-Vazquez, and J.L. Huertas Dept. of Analog Circuit Design. Centro Nacionai de Microelectronica. Edificio CICA, Avda. Reina Mercedes s/n. 41012-Sevilla, Spain. ABSTRACT A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated via the analysis of a Miller OTA in two different configurations and a linearized CMOS transconductor. The CPU time is reduced by a factor of 25 to 90 with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations. I. Introduction The performance of analog cells may be severely deteriorated due to random fluctuations in the electrical parameters of their components: transistors. resistors and capacitors. Crucial features like offset, commonmode rejection ratio (CMRR), power-supply rejection ratio (PSRR), etc., are critically dependent on random-induced mismatches, and require careful design (equivalently sizing) to guarantee that specifications remain within tolerable margins for the largest possible number of circuit samples. However, due to the difficulties encountered in the modeling and evaluation of random fluctuations, this problem is usually handled by simply imposing conservative constraints in the design parameter space; e.g. the transistor area i: a differential amplifier must be larger than say. 100 pm’. This leads to underexploitation of the performance potentials of the technologies. The optimization of the design procedure of analog cells under random fluctuations of the transistor parameters encompasses two different kinds of problems: a) Statistical modeliizg. essentially the capture of statistical features of the components into parameterized models. b) Siatisticul simulation. or the evaluation of the statistical features of the circuit performance induced by random variations of the electrical parameters. The statistical modeling of MOS components has been covered by different authors in recent years 11-41, Our contribution focuses not on the statistical modeling. but rather on statistical simulation. For modeling we rely on the proposal by Pelgrom [ 11 and more specifically, its further refinement as proposed in [2]. Such a model provides the variances of the electrical parameters of MOS devices as a function of their geometry and distances and covers correlations among electrical parameters. According to [2] variances of the electrical parameters of a given device can be evaluated from its layout as A (1) 2WL where D denotes the distance from the device to a common reference point (the coordinate center); WL, its area: and A and SI, are fitting constants, different for each technofogical parameter subject to variation. Let us focus on statistical simulation. Most analog designers use Monte Carlo analysis for this purpose. However. for large analog cells described at the electrical level this is very costly in CPU time. This precludes its usage inside iterative anaIog design procedures [5,6] and motivates looking for more efficient solutions [7.8.9]. Especially significant is the technique proposed by 191, based on a two-step linearization of the circuit performance. Precise results are obtained using the Monte Carlo method with that linearization. However, it assumes that circuit performances do not change significantly. Thus. the examples presented have no node with voltage standard deviation larger than 0.1V. Our contribution aims to use matrix methods to perform statistical analysis of analog integrated circuits starting from correlated electrical model parameters. These have been calculated according to the modeling technique in [4]. In particular, two different matrix techniques have been developed and included in a computer tool whose flowchart is shown in Fig.1. Some significant features of the proposed method are: 1) Statistical features of branch currents and node voltages of any circuit can be evaluated, allowing easy extension to any electrical, DC or AC, performance. 2) Results adequately fit those obtained with Monte Carlo analysis using an electrical simulator. 3) Analysis time is minimized so that the method can be included in an optimization-based design system. 11. Matrix-1 Technique o2 (A P) = 2 +$D2 Variations in the transistor electrical parameters of a 0-7803-2570-2/95 $4.00 01995 IEEE 2 148 given circuit induce changes in its node voltages and branch currents which can be calculated analytically. For a single transistor: =A I where 17~ represents the k-th electrical model parameter. Equation (2) is more conveniently written as, ai ai ai ai av, av, av,y av, -A V +-A V +-A V +-A VB-A I= (3) For a given circuit containing N transistors, and assuming that A4 node voltage variations and N-M branch current variations are chosen as unknowns, the following linear equation system can be formulated: A Ax=b (4) where If j>M otherwise where 6xj (x=D,G,S.B) is I if voltage V, and voltage Vj correspond to the same physical node, or contrarily 0. Cramer's rule is used to solve (4) and enables introducing correlations between transistors in the calculation. Hence, the j-th unknown is given by: (6) 1 Ax = (A,,b, +A2,hz+ ... +A b ) - NI '' IAl where the coefficients AV are the cofactors of the elements in the j-th column. Since we aim to determine variance, (6) must be multiplied by itself and integrated over the entire range of pk parameters. Then, the variance results: NN where ob is given by (7) Table 1 shows the deviations in node voltages and branch currents obtained by Monte Carlo simulations (50 simulation instances) and those obtained by the Matrix- 1 technique. As shown, the Matrix- 1 technique reduces the CPU time by a factor of 90, without significant deviations in the analysis results as compared with those obtained by Monte Carlo simulations. The BSIM model was used considering variations of 16 parameters (and their correlations). Correlations of the electrical parameters in HSPICE simulations were calculated - using the Principal Component Analysis technique 121. However, the Matrix-1 method does not consider eventual excursions of the transistor operating points through different operating regions (i.e. ohmic, saturation, etc.) and thus, may obtain inaccurate results for circuits containing nodes which swing over wide voltage intervals. For example, consider the open loop OTA Miller of Fig.3. Table 2 shows the branch currents and node voltages obtained by Monte Carlo analysis and the Matrix-1 technique. Since the circuit is in open loop, the voltage Vn3 changes over a wide range, taking transistors M, and M7 out of their nominal operating regions and hence, introducing important analysis errors. 111. Monte Carlo analysis on the system matrix: Matrix-2 Technique The Matrix-2 technique solves these problems by performing a Monte-Carlo analysis on vector b. Parameters are generated according to their distribution. A nonlinear system is solved using the Newton-Raphson method and sensitivities are updated at each iteration. Let us define a function Fi for each transistor: Circuit analysis consists in determining the voltages and currents which annul all F,. A Monte Carlo simulation consists in solving the system for a large number ot vectors of electrical parameters pi. The time is reduced considerably by using the system solution at the nominal point as an initial solution of the Newton-Raphson method. The function I;, at the nominal point is: F,=i,-i!(V,pt) i = l,2 ,..., N (10) ~~~j~i~,j-i~,~v,,,p~,~) i = 1,2, ..., N (11) For another vector of electrical parameters pi transistor currents can be approximated as: and the correlation between two entries of vector 6: I' ,~f k = I where the derivative is evaluated at the nominal point. Its corresponding function F, is then: DistMk and DistMl represent distances to the coordinate center. The mean values are assumed equal tQ the nominal values. The OTA Miller in Fig.2, configured as an unitygain buffer, illustrates the performance of this method. Let ub define a function G, as the differencr of' F, dt the nominal point and F, for another set of parametersp,: 2149 Expanding Gi in Taylor series (first order) and making it equal zero to apply the Newton-Raphson method: Applying (15) to (14) and reordering terms obtains in matrix notation: where A is defined as in (5) and Ax is the vector of unknown variations in voltages and currents. In every iteration of the Newton-Raphson method the equation system is solved by LU decomposition and Ax is updated summing the solution &(Ax) to it. The iterative procedure continues until convergence. Performing Monte Carlo analysis on the system matrix is more costly in CPU time than the Matrix-1 technique, but allows more accurate evaluation of variations, as shown in the OTA Miller results in Table 2. Moreover. a precise shape of the distribution is obtained. IV. Statistical features of DC Characteristics Interesting DC characteristics are functions of node voltages and branch currents at one or more operating points. As their relationships are known, their statistical features are easily obtained starting from the voltage and current deviations at the operating points needed for their evaluation. The variation in a DC performance Y, is expressed as: Y, = Y,(A xII, ..., A xin',. .A x,~~. .. .A x,,,) (17) where Axjk is,the increase in the k-th unknown at the 1-ti? operating point. Performances are usually determined by only one unknown; so, (17j is simplified to: (18) Y, = Y3 (A X, ,. . . ., A x~,~) Method- I calculates performance sensitivities with respect to vector AX, and the variance in then given by: where and using conventional statistical estimators. is defined similarly to (9). If Method-2 is used, calculations are reduced to Table 3 shows experimental results for the linearized transconductor in Fig.4. The specifications considered are slope, linearity, input offset, and output offset. Methods 1 and 2 give similar results (except mean values which are assumed equal to the nominal ones in Method-l), because no node experiments large excursions. Speed with respect to Monte Carlo analysis is increased by a factor of around 25 with Method-2 and a factor of 80 using Method-1. V. References h?.J M. Pelgrom, A.C.J. Duinmaijer. and A.P.G. Welhers: "Matching Properties of MOS Transistors", IEEE J. of Soiid-Stare Circuits, Vol. 24, pp. 1433-1440, Oct. 1989. C. Michael and M. Ismail: "Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits", fEEE J. of Soiid-Sfare Circuit.?, Vol. 27, pp.154-166, Feb. 1992. J Shyu. G.C. Temes, and K. Yao: "Random Error Effects in Matched MOS Capacitors and Current Sources", lEEE ./. of Solid-Slufe Circuits, Vol. 19. pp. 948.955, Dec 1984. K Lakshmikumar, R.A. Hadaway, and M.A. Copeland: "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design". IEEE J. of Solid-Sfczfe Circuits, Vo1.21, pp. 1057-1066, Dec 1986. E Medeiro, FV. Femjndez, R. Dominquez and A. Rodriguez- Vfizquez: "A Statistical Optimization-Based Approach for Automated Sizing of .i\nalog Cells", Pro(.. (CCAD, 1994. f! Maulik. R. Carley and D. Allstot: "Sizing of Cell-Level Analog Circuits Using Constrained Optimization Techniques", [€€E J. Wid-Stare Circuits, Vol. 28, pp.233-241, March 1993. H Su. C Michael and M. Ismail: "Statistical Constrained Optimization of Analog MOS Circuits Using Empirical Ikrformance Models", Proc. ISCAS. Vol 1, pp.133-136, 1994. J. Oehni and K. Schuniacher: "Quality Assurance and Upgrade of Analog Characteristics by Fast Mismatch Analysis option in ;Netu, ork .4nalysis Environment". IEEE J. of SoiiASrurr Cim~fr.y. \fol. 28. pp.865-871, July 1993. Z IVang and S. U;. Director. "An Efficient Yield Optimimrion \lethod Vuing 3 Two Step Linear Approxiination of Circuit Performance". PI-oc-. EDAC, pp. 567.57 I. Fch 1994 Matux-2 Jacobi,an hlethod Vanations in the operating point Evaluate deviations in AC-DC chanicteiihtics Figure 1: Flow diagram of the tool 2150 Table 1: Comparative results for Fig 2. Q 1 I JI vss Figure 3: Open-loop Miller OTA Table 2: Comparative results for the circuit in Fig.3 WOutn Figure 4: Linearized CMOS transconductor Table 3 Comparative result5 for the cIrcui+ in Fig 4 using Monte Carlo simulation and the new tool 2151