A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing

Received 30 December 2023; revised 21 February 2024; accepted 9 March 2024. Date of publication 18 March 2024; date of current version 5 April 2024. Digital Object Identifier 10.1109/OJCAS.2024.3378653 A Small-Area 2nd-Order Adder-Less Continuous-Time  Modulator With Pulse Shaping FIR DAC for Magnetic Sensing MANISH SRIVASTAVA 1(Member, IEEE), ALESSANDRO FERRO1(Member, IEEE), ALEKSANDR SIDUN1, JOSÉ M. DE LA ROSA 2(Fellow, IEEE), KILIAN O’DONOGHUE1, PÁDRAIG CANTILLON-MURPHY 1(Senior Member, IEEE), AND DANIEL O’HARE 1(Member, IEEE) 1MCCI, Tyndall National Institute, University College Cork, Cork, T12 R5CP Ireland 2Instituto de Microelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), 41092 Seville, Spain This article was recommended by Associate Editor S. Shah. CORRESPONDING AUTHOR: M. SRIVASTAVA (e-mail: [email protected]) This work was supported in part by the European Union ERC-2020-COG under Award 101002225, and in part by the Microelectronic Circuits Centre Ireland (MCCI) through Enterprise Ireland under Grant TC 2020 0029. ABSTRACT This work presents a small-area 2nd-order continuous-time  Modulator (CTM) with a single low dropout regulator (LDO) serving as both the power supply for the CTM and reference voltage buffer. The CTM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTM consumes 300 μW of power when clocked at 10.24 MHz. The CTM achieves a state-of-the-art area of 0.07 mm2. INDEX TERMS Analog-to-digital conversion, continuous-time delta-sigma modulation, excess loop-delay compensation, FIR DAC, magnetic sensor, sensor interface. I. INTRODUCTION MAGNETIC tracking for image-guided interventions requires sensors with sub-1-mm dimensions to navigate small anatomical features such as the patient’s airways, vasculature, neurological or nasal tracts [1],[2]. An analog- to-digital converter (ADC) is essential in sensor interface circuits to digitise the analog signals from sensors. For the intended application, a small-area low-power ADC is required. In addition to the ADC, the peripheral blocks required by the ADC (reference voltage buffer, power supply regulators, references, and clock generators) can consume substantial area and power. An ADC topology that enables the whole system to be implemented with low power and area is essential to realise a solution that can be co-located with the sensor. The overall ambition of this project is to design an on-chip ADC interface co-located with the magnetic sensor for use in tracking applications where the sensor is typically at the tip of a tiny instrument, tool, or catheter. Continuous-time delta-sigma modulators (CTM) are becoming increasingly popular in sensor systems due to their low power, low area, and relaxed requirements on their input and reference buffers compared to other solutions such as SAR ADC or Discrete-Time M. The employment of a single-bit CTM is an attractive architecture due to the inherent simplification of the digital- to-analog converter (DAC) by eliminating the need for c 2024 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ 42 VOLUME 5, 2024 calibration or dynamic element matching (DEM) requirements [3]. Unfortunately, the large DAC least significant bit (LSB) makes single-bit CTM extremely sensitive to clock jitter and places additional demands on the linearity of the front-end integrator. A finite-impulse response (FIR) feedback DAC can be used to reduce these problems by averaging or low-pass filtering the jitter of the clock signal which also reduces the feedback signal’s step size, improving modulator linearity [4]. The delay introduced by the FIR DAC and other modulator blocks changes the loopfilter transfer function and noise transfer function (NTF), making the system potentially unstable. Excess loop delay compensation (ELDC) is required to compensate for this delay [4]. A cascade of integrators in feed-forward (CIFF) topology is popular for low power CTM[5]. The feedforward paths reduce the output voltage swings at the integrators, allowing for the use of low-power single-stage operational transconductance amplifiers (OTA) while also improving OTA linearity and reducing slew. This usually requires an adder circuit before the comparator to sum the feedforward signals or paths and the ELDC path. The additional adder circuit also requires more area and power, making it less appealing for use in applications requiring reduced area, such as this work. Previously published works have proposed alternative loop-filter implementations to address this limitation. The CTM proposed in [5] used a second integrator as an adder while using DEM logic. While these techniques are appropriate for multi-bit quantisers, they are not applicable to single-bit CTMs. The passive adders were proposed in [6] and [7] which were implemented as capacitive and resistive adders, respectively. However, this technique suffers from both reduction of signal swing at the input of the comparator and being susceptible to parasitics and mismatch [8]. This paper proposes a 2nd-order CTM architecture that eliminates the need for a dedicated adder circuit and also proposes a new scheme of continuous-time pulse shaping DAC (CT-PS DAC) for ELDC that reduces distortion at the summing node and relaxes the design of the reference voltage buffer. The proposed DAC allows a single lowdropout-voltage (LDO) voltage regulator to generate both the power supply and Vref for the modulator, thus reducing the overall area of the system. These strategies allow high performance (see Table 4) while achieving the lowest area published to the author’s knowledge. The paper is organised as follows: An overview of the system design is explained in Section II. The circuit implementation is described in Section III. Section IV discusses measured results with a comparison with the state- of-the-art and finally, conclusions are drawn in Section V. II. PROPOSED MODULATOR ARCHITECTURE As shown in Fig. 1, this modulator will be used in magnetic sensing for position tracking in image-guided or robotic intervention applications, the area of the system is very FIGURE 1. A Block diagram of an on-chip magnetic tracking system with CTM. TABLE 1. The proposed CTM specification. FIGURE 2. A Block diagram of the conventional CTM with peripheral blocks. crucial. The performance of the whole system is limited by the noise of the input sensor and analog-front-end (AFE). To achieve the expected system accuracy for this work (±1 mm), the signal-to-noise-and-distortion ratio (SNDR)oftheCTM also needs to be in the range of 75-80 dB and dynamic range in the range of 80-90 dB. The specification for the proposed CTM is defined in Table 1. Fig. 2shows a block diagram of the conventional CIFF 2nd-order CTM, inclusive of low-dropout-voltage (LDO) regulators and a reference voltage buffer. The analog LDO supplies power to the integrators, while the digital LDO caters to the quantiser and digital-to-analog converter (DAC). The reference voltage buffer serves the purpose of providing a reference voltage for the DAC. The inclusion of these peripheral blocks contributes to an increase in the overall area of the system. As shown in Fig. 2, the feedback path through g implements the complex noise transfer function (NTF) zeros, reducing the quantisation noise within the signal bandwidth [9]. As explained in [9], distributing the zeros of the noise transfer function (NTF)throughout the signal band instead of concentrating them solely at DC, leads VOLUME 5, 2024 43 SRIVASTAVA et al.: SMALL-AREA 2ND-ORDER ADDER-LESS CONTINUOUS-TIME  MODULATOR FIGURE 3. A Block diagram of the conventional 2nd-order CTM with FIR DAC and ELD compensation. to an enhancement in the signal-to-quantisation-noise ratio (SQNR) within the bandwidth. An optimisation process was used to minimise in-band noise by determining the most effective frequency for these zeros. The optimal positions for the zeros are 14 kHz [9]. The loop filter L(s)transfer functions of the ideal CTM shown in Fig. 2, can be defined as follows: L(s)=k2f2 s+k1fss gf 2 s+s2(1) where k1and k2are the feed-forward coefficients and fsis the sampling frequency. The feedback path and gain gallow to place the zeros of NTF in an optimum position in the signal bandwidth. The dotted plot in Fig. 4is the signal-to-noise ratio (SNR) versus clock jitter generated from an ideal Simulink model of the CTMinFig.2. As depicted in Fig. 4,theCTM exhibits strong susceptibility to clock jitter, resulting in a degradation of the modulator’s in-band SNR [10],[11].The impact of the most severe clock jitter scenario (40 ps) for this work results in a reduction of the SNDR to 67 dB, as shown in Fig. 4. To mitigate this issue, switched-capacitor resistor (SCR) feedback may be implemented [12]. A disadvantage of this method is that it causes an increase in the peak-to- average ratio of the feedback waveform [10],[13]. FIR feedback is an alternative strategy to counteract the CTM’s susceptibility to clock jitter, as discussed in [10] and [14]. Employing FIR feedback in conjunction with a onebit modulator effectively reduces the clock jitter sensitivity and substantially reduces the requirement of the 1st OTA to respond to large step input signals, thus easing the linearity prerequisites of the loop filter. This benefit is akin to the advantages of using a multi-bit quantiser [10]. Fig. 3shows a CTM with an FIR DAC added to reduce the susceptibility to clock jitter. The delays added to the loop by the FIR DAC require an additional fast compensation DAC. The output sequence of the CTMis denoted as v[n]in Fig. 3, filtered through an M-tap low-pass FIR non-return-to-zero (NRZ) DAC with a transfer function F(z). Due to this, the magnitudes of the steps in the feedback DAC waveform (represented by v(t)in Fig. 3) are reduced by a factor of M. Since noise due to clock jitter is proportional FIGURE 4. Performance of the modulator (SNR) with increasing clock jitter. to the height of the transitions in the DAC output, it follows that the in-band mean square noise due to jitter is reduced by 20log10(M)dB [4],[15], as illustrated for a 4-tap FIR filter by the dashed plot in Fig. 4. To achieve our desired SNDR of 80 dB, the use of a 4-tap (with equal weights) FIR DAC proves beneficial, enhancing the SNDR by 12 dB. Increasing the number of taps would yield minimal benefits, while introducing additional complexity. These extra taps in both the FIR and ELDC DACs make it challenging to compensate for the added delay, consequently adding system complexity and area requirements. A. FIR DAC COMPENSATION The loop-filter transfer function L(s)changes due to the delays introduced by the FIR DAC and other modulator subblocks, making the modulator unstable and changing the NTF [10]. The NTF of the loop filter can be restored by modifying the loop-filter coefficients and by adding a direct path FIR filter around the quantiser. To restore the loop filter response to the response of the original topology in Fig. 2, open-loop pulse response analysis has been carried out as shown in Fig. 5. It should be noted that the open-loop pulse response does not show the NTF as the NTF is a closed-loop response. Rather, y(t)(solid line) is the open-loop pulse response of the ideal loop filter without any delay, while the dotted line shows the response with FIR DAC added. To restore the response for t/Ts≥M, the coefficients (k1and k2)were modified to ˆ k1and ˆ k2[16]. Mis the number of FIR DAC taps. To restore the response for t/Ts<M,aM-taps ELD compensation with transfer function Fc(Z)was employed. To restore the loop transfer function shown in Fig. 3, the feedforward coefficients k1and k2were optimised [4] and can be calculated as: ⎧ ⎨ ⎩ ˆ k1=k1+k2td Tsl+k21 g(1−l) ˆ k2=k2 (2) 44 VOLUME 5, 2024 FIGURE 5. Open-loop pulse response simulation of the loop filter (a) in ideal conditions (b) with FIR DAC present (c) with FIR DAC and ELD compensation. FIGURE 6. Open-loop pulse response of the ideal loop filter (solid), loop filter with equally weighted 4-taps FIR DAC (dotted), loop filter with FIR DAC and optimised cofficient (dot-dashed), and ELDC DAC with Fc(z) transfer function (vertical dashed lines). where lis defined in (3) and l=Meg−1 egM −1(3) where Ts=1/fsstands for the sampling period. The steps required to correct the open-loop filter step response are illustrated in Fig. 6. The start of the correction is the dotted line, and we want to restore the response to the ideal response of the solid line. Correcting the coefficients using (2) and (3) yields the dot-dash line. The value of taps for excess loop delay (ELD) compensation with transfer function Fc(z)can be computed by the difference of pulse TABLE 2. The coefficients of the proposed CTM. FIGURE 7. A Block diagram of the proposed 2nd-order Adder-Less CTM. response with and without the FIR DAC (|y(t)−ˆy2(t)|)as shown in Fig. 6.InFig.6the ideal response is shown by a solid line, the delayed response as a dotted line, and the coefficients for ELDC are shown in a vertical dashed line and were obtained from |y(t)−ˆy2(t)|the error. The dashed line shows the restored transfer function. B. PROPOSED ADDER-LESS FEEDFORWARD ARCHITECTURE MODELING The proposed modulator design is depicted symbolically in Fig. 7. Without changing the overall loop transfer function, the modulator structure of Fig. 3can be adjusted to create the proposed configuration illustrated in Fig. 7. The final adder is moved in front of the second integrator. The feedforward and ELD compensation paths are differentiated by capacitors before being summed together at the input of the integrator. The modified loop filter transfer function L(s)is defined as: L(s)=ˆ k2f2 s+ˆ k1fss gf 2 s+s2(4) where ˆ k1and ˆ k2are the optimised feed-forward coefficients as explained in Section II-A,fsis the sampling frequency, the feedback path gain gallows to place the zeros of NTF in an optimum position, as discussed in Section II. The coefficients of the ELDC FIR DAC need to be recalculated for the proposed topology using the methodology described in Fig. 5and the coefficients of the modulator can be found in Table 2. The circuit implementation of the proposed architecture will be presented in Section III, focusing on the circuit implementation of the loop filter, FIR DAC, and ELDC of the proposed adder-less CTM. VOLUME 5, 2024 45 SRIVASTAVA et al.: SMALL-AREA 2ND-ORDER ADDER-LESS CONTINUOUS-TIME  MODULATOR FIGURE 8. Simplified single-ended implementation of the proposed CTM. TABLE 3. OTA specification used for the integrator. III. CIRCUIT IMPLEMENTATION Fig. 8displays the simplified single-ended schematic of the proposed second-order 1-bit CTM. The second integrator serves the dual purpose of being both an integrator and an adder circuit which uses less area in comparison to the previously published work [5],[17],[18],[19],[20],[21], [22],[23]. The integrators in the CTM were realised by using folded cascode OTAs, while the feedback FIR DAC is realised as an equal-weighted four-taps resistive DAC. The specification for the OTA can be found in Table 3. A. IMPLEMENTATION OF ZEROS As stated in Section II, the NTF was designed to create a quantisation noise null at 14 kHz. This required a feedback resistor Rfb to implement the gterm. The Rfb was calculated to be 77 M. As shown in Fig. 9,theRfb was implemented as a duty-cycled resistor to save area. Duty-cycled resistors are preferable to pseudo-resistors as they have much less variation [24]. The switching frequency (fd)for the Rfb is a division of fs, to avoid aliasing out-of-band (OOB) shaped quantisation noise [24]. FIGURE 9. Implementation of the duty-cycled resistor. The loop filter transfer function for Fig. 8can be written as: L(s)= RfbCˆ k1R1s+1 RinCinCˆ k2R1Rfbs2−Cˆ k1R1s+1(5) This equation has a sterm in the denominator, unlike (4). This term reduces the quality factor of the loop filter. However, plotting the frequency response of (5) against the ideal transfer function, as shown in Fig. 10, shows only a minor degradation (the difference in location of the zero from (4) to (5), was less than 100 Hz). B. NOISE ANALYSIS OF THE CTM A block diagram of the CTM is shown in Fig. 11 (a). The input-referred-noise (IRN) density of the modulator will be dominated by the 1st integrator and DAC. The noise from the 2nd integrator, as shown in Fig. 11 (b), will be shaped by the gain of the 1st integrator. So, the IRN density of the modulator can be calculated as: v(n,in)=8kTγ gm+4kT(Rin +RDAC)(6) 46 VOLUME 5, 2024 FIGURE 10. Comparing the frequency responses of the ideal loop filter as given by equation (4)and the schematic loop filter as given by (5). FIGURE 11. (a) A Block diagram of the CTM with active RC integrator (b) Main Noise Contributor (active RC integrators and DAC) of the CTM. where kis Boltzman’s constant, T is the temperature in kelvin, gmis the transconductance of OTA used in the integrator, Rin is the input resistor of the integrator, and RDAC is DAC’s resistor. So, by using equation (6) and values from Fig. 8,theIRN density of the CTM can be computed and was found to be ∼ =33 nV √Hz . C. ADDER CIRCUIT IMPLEMENTATION Fig. 12 (a) shows the implementation of the 2nd integrator combining the integration (solid line), proportional gain (dotted line), and ELDC DAC (dashed line) paths. The integrator has a low-pass characteristic, whereas the proportional path (dotted line) and DAC path (dashed line) are AC coupled and have band-pass characteristics, as depicted in Fig. 12 (b). The absence of the proportional signal at low frequencies doesn’t cause errors in the modulator response because its magnitude is small in comparison to the large integrated signal (solid line). In the proportional gain path, the coefficient ˆ k1is implemented as a proportional gain Cˆ k1/Cˆ k2. The ELDC has FIGURE 12. (a) Adder circuit implementation. (b) Magnitude response of the integration, proportional gain, and ELDC signal paths. been realised by a continuous-time capacitor DAC (CDAC). The implementation of the ELDC can be explained as follows; The modulator output Dout[n]is applied to the n DAC capacitor values (CDn)where n represents the number of FIR DAC taps used in ELDC. The capacitors act as differentiators to produce currents which are then added together and integrated by C ˆ k2. The differentiation and integration operations effectively cancel each other out and the resulting signals at the comparator input are the DAC signals gained by CDn/Cˆ k2. D. PROPOSED CONTINUOUS-TIME PULSE SHAPING DAC As shown in Fig. 13 (a), the reference voltage, Vref is applied to the ELDC’s capacitor (CDn)which acts as a differentiator, generating a current Ivref (=CDn dVref dt )that is then integrated by C ˆ k2. Due to the reference buffer’s limited current sourcing capabilities, errors are introduced in the current pulse Ivref causing distortion. The finite current sourcing of the second integrator OTA causes slewing and large voltages at node Vgwhich can disturb the gain and integration modes. VOLUME 5, 2024 47 SRIVASTAVA et al.: SMALL-AREA 2ND-ORDER ADDER-LESS CONTINUOUS-TIME  MODULATOR FIGURE 13. (a) Conventional design (b) The proposed pulse-shaped DAC with resistor Rps. Possible solutions to address this issue are: (a) reducing the output impedance of the reference buffer which will attenuate glitches at the cost of increased power consumption or (b) using a large decoupling capacitor (>100 pF) at the Vref buffer can provide the switching currents required by the CDAC during transitions. Many state-of-the-art ADCs use off-chip decoupling capacitors to maintain a clean reference voltage [4],[5],[19]. As this modulator will be used in applications (in-vivo magnetic tracking) where the area and additional pin for an external capacitor are undesirable, a continuous-time pulse shaping DAC (CT-PS DAC) circuit is proposed. A pulse-shaping resistor (Rps) is added to CDAC before the node Vg, as shown in Fig. 13(b), which limits the peak Ivref : Ivref =Vref Rsw +Rps e−t (Rsw+Rps)CDn (7) where Rsw is the switch resistance, Rps is pulse shaping resistor, and CDn is the ELDC path capacitor where n=1,2,3,4. Fig. 14(a) shows the current flowing from CDn to C ˆ k2, the solid line waveform represents peak current at the Vg node without the pulse shaping resistor Rps, while the dotted line waveform represents the shaped pulse. The magnitude of the peak sourced current has been reduced from 417 μA to 21.7 μA, a reduction by a factor of 20. The reduction in Ivref peak also reduces the slew requirement of the 2nd integrator OTA, thus reducing distortion. The shaped pulse (dotted line ) introduces no error provided the area of its pulse integrated in the sampling time Tsis equal to that of the integrated pulse without resistor Rps (the solid line). To meet this requirement, the maximum value of Rps was chosen to maintain the same charge Qps (i.e., matching the area of the current (Ivref ) pulse integrated in time Ts). The trade-off of area (charge Qps) versus resistance is shown in Fig. 14(b). As depicted in Fig. 14(b), the area of the integrated pulse will decrease as the resistance exceeds 40 k, leading to the aforementioned error. FIGURE 14. (a) Ivref with and without Rps (b) Charge Qps (area under current pulse) with increasing pulse shaping resistor (Rps). It is important to differentiate this work from the previously published work by Ortmanns et al. [12],In their work a switched capacitor resistor (SCR) DAC was introduced, generating a decaying pulse waveform that exhibited insensitivity to jitter. In this work, a continuoustime capacitive DAC (CT-CDAC) approach is introduced. Ortmanns’ contribution entailed generating a current pulse proportional to the DAC signal, which was then subjected to integration. In this work, the current pulse is the differential of the applied voltage step. This differentiated pulse then undergoes integration, effectively nullifying the differentiation process and resulting in an output signal that is a gained/scaled version of the DAC voltage. A low-power and low-area dynamic comparator architecture was used for this work. The design of the comparator was referenced from [25]. E. VOLTAGE REGULATOR/BUFFER CIRCUIT IMPLEMENTATION Fig. 15 presents the schematic of the low-dropout- voltage/reference-voltage-buffer (LDO/VREF-buffer) configuration, providing the supply voltage VDD and 48 VOLUME 5, 2024 FIGURE 15. (a) LDO/VREF-buffer circuit (b) Beta multiplier voltage reference circuit (BMVR). reference voltage (Vref )for the CTM. This configuration employs a beta multiplier voltage reference (BMVR) design to generate a 1.2 V reference for the LDO. To reduce potential switching noise perturbations on the CTM’s power supply, a capacitor (CL)of 15 pF is used at the output of the regulator. This mitigates transient disturbances and noise artifacts and minimises any SNDR reduction of the CTM due to power supply disturbance. The LDO/VREF- buffer with CLoccupies an active area of 0.02 mm2and consumes 47 μA from a 1.5 V power supply. The CT-PS DAC proposed in this study led to a noteworthy decrease in the switching current drawn from the input buffer in the CTM. This not only improves the DAC’s performance but also enables the use of a single LDO for both the CTM power supply and the Vref supply for the DAC. This approach simplifies the system design, reduces the overall area significantly, and lowers the overall power consumption, especially important for applications requiring very small readout circuits. IV. MEASURED RESULTS The proposed CTM is fabricated in a 65-nm CMOS process. As shown in Fig. 16,theCTM occupies an active area of 0.07 mm2and the LDO/VREF-buffer with decoupling cap occupies an area of 0.02 mm2.Fig.17 shows the measurement setup. A signal generator (Keysight 33500b) is used to apply a fully differential input sine wave. The single-bit digital output data was read out using a Digilent Digital Discovery portable logic analyser and further off-chip FIGURE 16. The die photograph shows the overall IC designed for the 65-nm process node. FIGURE 17. The CTM test setup includes an external clock generator and logic analyser. FIGURE 18. Power Spectrum Density of CTM. post-processing was carried out using MATLAB. A 6.17- kHz sine wave input signal with an amplitude of −2.4dBFS (full scale of 1.2 V) is applied to the input of CTM while the sampling clock frequency is set to 10.24 MHz. The output spectrum of the modulator, acquired by an average of eight 130K point FFTs using a Hanning window, is shown in Fig. 18. The modulator achieves 81.5 dB SNDR, with HD3 and HD5of −98.98 dB and −98.0 dB, respectively. Fig. 19 shows the SNDR for a 6.17 kHz tone versus the input signal VOLUME 5, 2024 49 SRIVASTAVA et al.: SMALL-AREA 2ND-ORDER ADDER-LESS CONTINUOUS-TIME  MODULATOR FIGURE 19. SNDR over increasing input signal amplitude at 6.17-kHz. FIGURE 20. Peak SNDR with increasing input signal frequency with amplitude -2.4 dBFS. amplitude level in 20 kHz bandwidth. Sweeping the input signal from −100 dBFS to 0 dBFS demonstrates a dynamic range of 91 dB. It is worth noting that in this application, the dynamic range is more important than SNDR, as the induced voltage in the magnetic sensor ranges from a few hundred nV to an expected max of 100 μV. Fig. 20 compares the measured SNDR in the signal band for four different chips for a range of input signal frequencies; the lowest peak SNDR across four chips occurred at 81.5 dB when evaluated against the input frequency. The improvements in SNDR with frequency are due to the 2nd and 3rd harmonics going outside the signal bandwidth. These measured results show only minor part-to-part variations. The proposed CTM with the LDO/VREF-buffer design operates on a power supply of 1.5 V, with a total power consumption of 380 μW. Fig. 21 illustrates the breakdown of power usage, encompassing both the LDO/VREF buffer and the individual modulator blocks. To demonstrate the sensitivity of the CTM to the jitter on the sampling clock of the modulator, it was tested with two sources: SMA100B from Rohde-Schwarz [26] and True waveform generator from Keysight [27]. The SMA100B has the jitter of <1ps (in a solid line), and the true waveform FIGURE 21. Power breakdown for various CTM blocks including the LDO/VREF-buffer. FIGURE 22. Clock jitter sensitivity to CTM with FIR DAC. generator has <40 ps (in a dotted line). As shown in Fig. 22, the marginal 2 dB performance reduction underscores the insensitivity of the CTM performance to clock jitter, highlighting instead the prominence of thermal noise as the dominant noise source of the CTM. As mentioned previously, the CTM will be used in applications such as magnetic sensing for position tracking in Image-Guided or robotic surgery. To demonstrate the CTM performance for the electromagnetic tracking (EMT) of an on-chip sensor, full EMT system measurements were carried out using the open-hardware ANSER EMT system [28]. The EMT system uses eight signal tones for tracking the instrument during image-guided or robotic interventions [28]. The test setup is shown in Fig. 23.The test setup shows an on-chip sensor coil along with AFE, the CTM and LDO. The signal generator generates 8 tones (20–34 kHz). This induces voltages in the on-chip sensor 50 VOLUME 5, 2024