Novel pipeline architectures based on Negative Differential Resistance devices

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ “This is an Accepted Manuscript of an article published by Elsevier in Microelectronics Journal on Nunez J., Avedillo M.J., Quintana J.M. (2013) Microelectronics Journal, 44 (9), pp. 807-813., available at: https://doi.org/ 10.1016/j.mejo.2013.06.012” Novel Pipeline Architectures based on Negative Differential Resistance Devices Juan Núñez , María J. Avedillo and José M. Quintana Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC) & Universidad de Sevilla Av. Américo Vespucio s/n, 41092, Sevilla (Spain) {jnunez, avedillo, josem} @ imse-cnm.csic.es Abstract. Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the Monostable to Bistable (MOBILE) operating principle can be built from the operation of two series connected NDR devices with a clocked bias. MOBILE gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out. Keywords: Negative differential Resistance (NDR), Fine-grain pipeline, Monostable to Bistable Logic Elements (MOBILE), MOS-NDR. 1 Introduction Different emerging devices like Resonant Tunneling Diodes (RTDs), tunnel transistors or molecular RTD devices exhibit Negative Differential Resistance (NDR) in their I-V characteristic. Many circuits taking advantage of it have been reported covering different applications and with different goals, including high speed, low power or reduced device count [1], [2], [3], so that design techniques exploiting this feature at different levels (circuit, architecture, …) are currently an area of active research. Moreover, exploration of transistor circuits that emulate the NDR characteristic has recently received renewed attention in order to incorporate the benefits of NDR based circuits into transistor technologies [4]-[10]. From the point of view of design, the NDR characteristic is very attractive. On one hand, it can be exploited in non-linear circuits like oscillators or frequency dividers. On the other, it is useful in the implementation of memories due to the existence of stable states associated to the inclusion of NDR elements. In particular, the Goto pair is well known [11]. The circuit consists of two NDR devices connected in series leading to three operating points, two stable and one unstable. The two stable points can be used to represent and store data. On the basis of the Goto pair, logic circuits which operation is based on a Monostable to a Bistable transition (MOBILE) have been developed. MOBILE gates are implemented operating two series connected NDR devices with a switching bias. There is a pair of interesting characteristics of MO- BILEs in comparison to conventional logic gate implementations. First, they increase the functionality implemented by a single gate in comparison to MOS and bipolar technologies and, thus, reducing circuit complexity. In particular, the operating principle of MOBILE is extremely well suited to implement the arithmetic operation on which Threshold Gates (TGs) are based [12]. Different topologies for MOBILE TGs and Multi-Threshold Threshold gates have been reported and experimentally validated [13], [14]. Second, the self-latching property of MOBILEs arising from their NDR characteristic allows the implementation of fine grain pipelines which can be achieved without resorting to memory elements [1], [15]. In this way, exploration of interconnection schemes for MOBILE gates is relevant for the design of functional units for high performance applications, which is currently an area of active research. Originally, it was proposed to operate MOBILE gates in a gate level pipelined fashion using a four-phase overlapped clock scheme. Conventional counterpart of this superpipelining is the operation of Domino logic in a pipelined fashion using an overlapping multi-phase clock scheme and without latches between consecutive clock phases [16]. Variations of this multi-phase domino solution (three to six phases) have been developed by different companies and applied into commercial circuits [17], [18]. However, MOBILE pipelines do not exhibit the functional limitation of domino solutions, and thus, both inverting and non-inverting blocks can be chained. The overcoming of the functional limitation is not the only advantage of the MOBILE architectures, but their edge-triggered feature allows the implementation of other distinctive interconnection schemes. In particular, this characteristic can be exploited to reduce the number of clock-phases, which is attractive both from the point of view of increasing through-output, and for simplifying clock distribution. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. The paper is organized as follows: in Section 2, MOBILE logic style is described. Section 3 presents the MOS-NDR device and the implementation of MOBILE logic gates on its basis. In Section 4 and 5, we describe and analyze the single phase and the two-phase MOBILE pipelines respectively. Section 6 shows experimental results validating their operation and compares both approaches. Finally, some key conclusions are given in Section 7. 2 MOBILE operation principle 2.1 MOBILE logic gates The MOBILE [12] in Fig. 1a is an edge-triggered current controlled gate which consists of two devices exhibiting NDR in their I-V characteristic (Fig. 1b), connected in series and driven by a switching bias voltage, VCK. When VCK is low, both NDRs are in the on-state and the circuit is monostable. Increasing VCK to an appropriate maximum value ensures that only the device with the lowest peak current switches from the on-state to the off-state. Output is high if the driver NDR switches and it is low if the load does. Logic functionality can be achieved if the peak current (IP in Fig. 1b) of one of the NDR devices is controlled by an input. In the configuration of the rising edge-triggered inverter MOBILE shown in Fig. 1c, the peak current of the driver NDR can be modulated using the external input signal Vin. Transistor behaves like a switch, so that for a low input, current flows only through NDRD, but for a high input, the effective peak current of the driver is the sum of the peak currents of NDRD and NDRX. More complex logic functionality can be implemented in two different ways. Clearly, replacing the single transistor in Fig. 1c by an NMOS transistor network, other logic functions are implemented. NDR peak currents are selected such that the value of the output depends on whether the network transistor evaluates to “1” or to “0”. Alternatively, topologies for implementing threshold functions0F 1 [19] have been proposed. The inverter shown in Fig. 1c can be also explained as a threshold gate, with a single input with associated weight w1 = -1 and threshold T = 0. Adding input branches (NDR device plus transistor) in parallel to the driver (load) NDR inputs with negative (positive weights) are implemented. That is, the weighted sum and the comparison to a threshold value which defines the operation of a threshold gate is realized by means of the current controlled switching principle of the MOBILE. Figure 1d depicts a falling edge triggered inverter. Note that branch implementing functionality is now in parallel to the load NDR and uses a p-type transistor. It is well known that a sufficiently slow VCK rising (or falling) is required for MOBILE operation [20]. That is, there is a critical rise time for the switching bias below which the gate does not operate correctly. Under that critical rise time, there is at least one input combination for which the gate does not produce the expected logic output. It is due to AC currents associated to internal parasitics and output capacitive loads (fan-out), which are more important for faster clock changes, that somewhat “alter” the ideal MOBILE operating principle based on peak currents comparison. This critical value depends on both circuit (NDR peak currents, fan-out …) and technological parameters. That is, design requires taking into account this AC currents in 1 A threshold gate (TG) is defined as a logic gate with n binary input variables, xi (i=1, . . . , n), one binary output y, and for which there is a set of (n +1) real numbers: threshold T and weights w1, w2, . . . , wn, such that its input–output relationship is defined as y=1 iff Tx w n i ii ≥ ∑ =1 and y=0 otherwise. Sum and product are the conventional, rather than the logical, operations. order to guarantee the desired relationship between load and driver currents for each input combination when VCK approaches 2Vp, being Vp the peak voltage of the NDRs (see Fig. 1b). Rising (falling) edge-triggered MOBILE logic gates evaluate the inputs with the rising (falling) edge of the bias voltage and hold the logic level of the output while the bias voltage is high (low), even though the inputs change (self-latching operation [21]). The output returns to zero (to one) with the falling (rising) edge of the clock until the next evaluation. The self-latching operation allows the implementation of gate-level pipelined architectures without extra memory elements [1] and without the functional limitation of dynamic based solutions like the widely used domino logic style. 2.2 Interconnecting MOBILE gates As it was stated in previous section, and assuming rising-edge MOBILEs, there are four steps in the operation of each gate: evaluation (clock rises), hold (clock high), reset (clock falls) and wait (clock low). Gate-level pipelining is possible if each MOBILE gate evaluates while those driving it are in the hold state. In this way, it is guaranteed that inputs to each gate are stable during evaluation, and that the reset of the MOBILE gates do not affect those they drive, since they have already evaluated when it happens. Thus, memory elements are not required. Note that this is true both for inverting and non-inverting MOBILE stages, and even when adding and output stage (static inverter or buffer) to the output of the MOBILE blocks to ease management of fan-out and interconnections. That is, fulfilling above stated constraint allows ultra-fine-grain pipeline operation where both inverting and non-inverting stages are allowed. In domino solutions only non-inverting stages are possible which complicates logic design (inverters need to be pushed towards the inputs or some parts of the circuits are duplicated), unless a double rail implementation is used which almost duplicates device count. Conventionally, and because of the four steps in MOBILE operation, cascaded rising edge-triggered MOBILE gates are operated in a pipelined fashion using a four-phase overlapping clock scheme shown in Fig. 2 [1]. VCK, i is delayed with respect to VCK, i-1 by T/4, being T the clock period. Thus, the ith stage evaluates (rising edge of VCK, i) while the (i-1)th stage is in the hold phase (VCK, i-1 high). Four clock signals are enough, since the first phase can be used for the fifth level and so on. In previous section, it was stated that there is a critical rise time below which the gate does not operate correctly. This explains the clock shape with equal rise, high, fall and low times. Thus, for this scheme four gates/stages serially evaluate in one clock period. However other schemes are compatible with the constraint that one stage evaluates while preceding stages are in hold state. Moreover, the constraint can be somewhat relaxed making possible other simpler schemes. Sections 4 and 5 describe two novel architectures developed on the basis of previous statement. 3 MOS-NDR MOBILE Logic NDR I-V characteristics derived from a Λ type NDR topology described in [22], can be emulated with CMOS transistors using the MOS-NDR device shown in Fig. 3a [6]. It consists of two NMOS and one PMOS transistors, which leads to an I-V curve with only one positive differential resistance region (PDR), as shown in Fig. 3b. Both the PDR and the NDR zones of the NDR I-V characteristic are obtained through the current of a NMOS transistor (N1) whose gate-to-source voltage is modulated by the output voltage of the CMOS inverter biased by VDD. For low values of V N1 is working in lineal region (generates PDR region of the I-V curve), until the output of the inverter falls and, thus, N1 cuts off. The peak voltage (VP) and current (IP) can be modified by properly setting up the sizes of the transistor. In this way, IP is increased with the width of N1. Assuming that all transistors have the same gate length, the position of VP is controlled by the ratio between the widths of the NMOS and the PMOS transistors of the inverter. In this way, higher values of VP are obtained by decreasing such ratio. Implementations of MOS-NDR MOBILE gates have been reported [10], [28], [6] leading to compact implementations of complex functions. Figure 3c depicts a MOBILE inverter designed using such CMOS emulator, in which each NDR device have been replaced by a MOS-NDR device. Driver NDR includes logic functionality, which has been implemented by adding two series-connected NMOS transistors: the one of the top represents the weight of the input branch and the other operates as a switch which is enabled by the input. Complex functions can be efficiently implemented by adding input branches in parallel (either with the driver or the load) [6]. Self-latching operation of MOBILE gates implemented with MOS-NDR devices is also observed. Figure 3d shows simulation waveforms corresponding to the MOBILE inverter in Fig. 3c, where it can be inferred that changes of the input when the clock is in hold state do not trigger variations of the output. 4 Single Phase MOBILE architectures A network of MOBILE-based gates can be operated with a single clocked bias signal if rising edge-triggered gates and falling edge-triggered gates are alternated and latches are added at each stage to remove the return-to-reset behavior [23]. However, it has been demonstrated that it is not necessary to remove the return-to-reset behavior to ensure correct operation [24]. It is enough to keep the output of each MOBILE stage until it has been evaluated by the next one. Thus, each latch is replaced by a static inverter/buffer. However, in these architectures, negative edge-triggered MOBILE are used which requires p-type transistors. This translates in larger transistors, and so in larger parasitic capacitances which degrade gate speed. The proposed single phase architecture is built from rising-edge MOBILE gates driven by a single clock signal, and skewed static stages between MOBILE blocks. Figure 4a depicts a block diagram of the proposed architecture. Its correct operation requires satisfying a set of relationships among given timing parameters of its components. That is, for the proposed interconnection scheme to work, different timing constraints must be satisfied. For the purpose of deriving them, lets us introduce the following parameters: 1_ _EvalMOBILE t : MOBILE evaluation time of a logic 1 0__ Eval MOBILE t : MOBILE evaluation time of a logic 0 setMOBILE t Re_ : Reset time of the MOBILE stage 1_Static t : Propagation delay through the static logic of a low to high transition 0_Statict : Propagation delay through the static logic of a high to low transition upStet t_ : Amount of time that MOBILE input must be stable before the clock rising edge Holdt : Amount of time that MOBILE input must be stable after the clock rising edge T : Clock period HT : Clock pulse width Following three types of constraints must be fulfilled by each pair of consecutive stages. 1.- It must be guaranteed that signals do not propagate too slow. That is, in one clock period the MOBILE stage evaluates, and the static logic propagates its output in time for the next stage to correctly evaluate. Formally: Tttt upSetStatic EvalMOBILE <++ _ 1_0 __ (1) Tttt upSet StaticEvalMOBILE <++ _0_ 1__ (2a) Relation (2a) can be relaxed taking into account that tMOBILE_Eval_1 is zero, since the output of the MOBILE was already zero due to the previous reset phase. Moreover, as it was already zero, it means static logic has more than T to propagate a 0, and so, it can be rewritten: setMOBILE HupSetStatic tTT tt Re __0 _2−− <+ (2b) 2.- It must be guaranteed that signals do not propagate too fast. That is, a pipeline stage (MOBILE block + static logic) does not propagate to its output the result of an evaluation associated to a given clock edge before the MOBILE blocks it drives have taken the decision corresponding to that clock edge. Formally: HoldStaticEvalMOBILE ttt >+ 1_0__ (3) HoldStatic EvalMOBILE ttt >+ 0_1_ _ (4a) which as in previous case, taken into account the previous reset of the MOBILE stage can be rewritten: setMOBILEHoldHStatic ttTTt Re_0_ −+−> (4b) 3.- Due to the reset behaviour of MOBILE gates, it must be guaranteed also that the reset of the MOBILE, produced by the falling edge of the clock, does not reaches the output of the static logic in time to be evaluated by following stage with next rising clock edge. Formally: Hold HStatic set MOBILE t TT t t+ − >+ 0_ Re _ (5) Note that constraint 5 is equal to constraint 4b. This is so because when deriving hold constraint, relation 4 was rewritten taken into account the reset behaviour of the MOBILE gates. In addition, every MOBILE block must have enough time to reset. This limits the duration of the clock pulse width (TH), since reset occurs with the falling edge and should be completed before rising edge, which means available time is T – TH. Note that tHold and tset_up are small because MOBILE gates evaluate with the rising clock edge. Static logic must be designed such that it propagates inputs slow enough not to reach next MOBILE too early (constraint 3 and constraint 4b), but not too slow to reach next MOBILE too late (constraint 1 and constraint 2b). According to derived timing relationships, the static logic is designed in order to slow down the low to high output transition with respect to the opposite one in order to full-fill with constraints 4b and 5, and also because upper limit of the low-to-high transition is more relaxed than for the later (constraint 2b versus constraint 1). Nevertheless, detailed electrical simulation is required and equations above must not be considered a design tool at the logic level, but a mean to introduce timing aspects of the proposed architecture. Clearly this architecture works on the basic of the intrinsic self-latching characteristic of MOBILE blocks. A similar one based on domino stages is not possible because evaluation is carried out in this case when the clock is high, instead of being associated to the clock transition. One of the main advantages of this architecture is that a single clock is distributed. However there are some other design challenges that require some explanation. First, these circuits exhibit a minimum operating frequency due to constraints 4b and a maximum operating frequency, that can be determined by any of the other constraints when considering very fine-grain pipeline which is our target. The limit situation of pipeline is a single inverter between consecutive stages, in the sense that more complex static logic (a gate with embedded functionality or several logic levels) could help in relaxing lower bounds on delays which complicates design. For our current purpose of explaining the interconnection challenges, a given MOBILE inverter is considered and the impact of the static inverter on circuit operation is analyzed. From our experience, if the inverter is too much skewed, operation is going to be limited by hold failures (constraint 3) and maximum frequency is reduced from what it could be achieved according to constraints 1 and 2b, leading to a much reduced range of operating frequencies, that might be even unable to tolerate variations of process parameters. Figure 4b shows simulations results of a chain of MOBILE inverters with skewed static inverters between them, corresponding to a WP/LP to WN/LN ratio of the static inverters equal to 35 at a frequency slightly over its maximum operating frequency (1.6GHz). It can be observed that the output of the first stage, VOUT, 1, is correct. Alternating 0`s and 1`s are obtained as expected for the applied input, VIN. This means the MOBILE is able to operate at this speed and with this clock transition times. It can be observed also that low to high transitions of VOUT, 1x are very slow and high to low transitions are very fast. The second MOBILE stage does not work. It correctly evaluates the 0`s of the first stage’s output, but it fails to produce a correct output for 1’s. Note the intermediate voltage level at the output VOUT, 2 which translates in functional failure as it can be seen comparing input VIN and output VOUT. The problem arises from the very fast high to low transition of VOUT1,X, simultaneous to the rising edge of node VCK which acts as the clock for the MOBILE core of the cell, which produces a “hold violation”. Correct operation is observed, for example, for a WP/LP to WN/LN ratio equal to 14 now at a higher frequency (2.1GHz). Process and operation parameter variations can modify the range of operating frequencies. Corner and Monte Carlo simulations of the second design have been also carried out showing correct behaviour. Second concern for fine grained pipelines is related to clock skew tolerance due to the fact that all stages evaluate with the same clock edge. 5 Two-Phase MOBILE architectures An alternative solution to avoid drawbacks found in single-phase interconnection schemes is to use an overlapping two-phase clock [25] scheme as shown in Fig. 5a and 5b. In this configuration each gate evaluates while preceding one is in the hold state and, only two stages serially evaluate in one clock period. Note that inter-gate elements (inverting or not inverting) can also be added if required by logical (to increase design flexibility), or electrical (for example, efficient handling of large loads) considerations. Unlike the single phase architecture, the overlapping of the two clocks allows to directly connect two MOBILE gates since the return to reset of one stage takes place after the evaluation of the next one. A timing analysis, as in the case of the single phase, is also carried out. For each pair of consecutive stages: 1.- It must be guaranteed that signals do not propagate too slow. That is, in half clock period, the MOBILE stage evaluates, and the static logic, if it exists, propagates its output in time for the next stage to correctly evaluate. Formally: 2/ _1_ _0__ Tt tt upSet evalStaticEvalMOBILE <++ (6) 2/_0__1__ Tttt upSetevalStaticEvalMOBILE <++ (7a) Again relation (7a) can be relaxed taking into account that tMOBILE_Eval_1 is zero, since the output of the MOBILE was already zero due to the previous reset phase. Moreover, as it was already zero, it means static logic has more than T to propagate a 0, and so, it can be rewritten: _ _0 _ _ 3 /2 Static eval Set up H MOBILE Reset t t T Tt+ < −− (7b) 2.- Note that there are not conventional hold constraints in this scheme since consecutive stages do not evaluate with same clock edge. 3.- Constraint related to the reset of the MOBILE stage not being “seen” by following stage is also quite relaxed because the two clock phases overlap. It must be only guaranteed that the reset of the MOBILE does not reaches the output of