Advanced Non Inverting Rogowski Integrator Design for SMART Tokamak Current Measurement

Equation Chapter 1 Section 1 Trabajo Fin de Máster Máster Universitario en Sistemas de Energía Eléctrica Advanced Non-Inverting Rogowski Integrator Design for SMART Tokamak Current Measurement Author: Pablo Vicente Torres Tutors: María Ángeles Martín Prats and Juan Manuel Ayllón Guerola Dpto. Ingeniería Electrónica Dpto. de Ingeniería Mecánica y Fabricación Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2023 iii Trabajo Fin de Máster Máster Universitario en Sistema de Ingeniería Eléctrica Advanced Non-Inverting Rogowski Integrator Design for SMART Tokamak Current Measurement Autor: Pablo Vicente Torres Tutores: María Ángeles Martín Prats Profesora titular Juan Manuel Ayllón Guerola Profesor Ayudante Doctor Dpto. de Ingeniería Electrónica Dpto. de Ingeniería Mecánica y Fabricación Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2023 v Trabajo Fin de Carrera: Advanced Non-Inverting Rogowski Integrator Design for SMART Tokamak Current Measurement Autor: Pablo Vicente Torres Tutor: María Ángeles Martín Prats y Juan Manuel Ayllón Guerola El tribunal nombrado para juzgar el Proyecto arriba indicado, compuesto por los siguientes miembros: Presidente: Vocales: Secretario: Acuerdan otorgarle la calificación de: Sevilla, 2023 El Secretario del Tribunal vii A mi familia ix Agradecimientos A lo largo de la historia, la investigación ha permitido un avance sin precedentes de las técnicas, conocimiento y habilidades de los seres humanos. En los últimos siglos, el avance de la ciencia, fundamentado en el método científico, ha propiciado un crecimiento exponencial en todos los campos. La cuestión de refutar o no las concepciones inicialmente planteadas es central en este proceso, pero ¿debe ser para el investigador/a su único y principal objetivo? La historia ha dejado patente que la autenticidad de los descubrimientos debe abrazar este principio único, con el fin de desentrañar la verdad inherente a la naturaleza. Así se concibió en los albores de este método, cuando la filosofía y la ciencia coexistían como una entidad única. No obstante, el método científico es meramente una herramienta en manos del investigador, como Carl Sagan solía expresar con elocuencia: «nuestra pasión por el conocimiento es el instrumento de supervivencia que nos define». Mi pasión por aprender no es más que la esencia de hacerme sentirme vivo en el modo que Sagan lo definía como supervivencia. De cerca, personas me han hecho crecer en todo mi trayecto hasta el día de hoy. Agradecer a mi familia el aporte continuo e incondicional de experiencia, emociones y acompañamiento. A Jorge, por su entrega continua y desinteresada de conocimiento y motivación. A los tutores de este trabajo M.ª Ángeles y a Juanma, por introducirme en el mundo de la fusión y darme esta enorme oportunidad. Y al resto de personas que de una forma u otra me han acompañado en esta experiencia de la investigación y las que aún quedan por descubrir. «Los pigmeos colocados en los hombros de gigantes ven más que los gigantes mismos». (Robert Burtonen, 1624) Pablo Vicente Torres Sevilla, 2023 4.4.5 Random noise 31 4.5 Circuit simulation 32 4.6 PCB circuit construction 35 5 PCB testing 39 5.1 Wiring test 39 5.2 Power supply test 39 5.2.1 Power quality test 40 5.3 Relay test 40 5.4 Noise and drift test 40 5.5 Integration test 40 6 Conclusions and Future Work 43 6.1 Conclusions 43 6.2 Future work 43 Annex A 47 Annex B 49 Annex C 51 References 53 TABLES INDEX Table 2-1 : Power supply features 15 Table 3-1 : Platform comparison: ATCA, VPX and cPCI Express [65] 25 Table 4-1 : Circuit component values 32 Table 4-2 : Individual noise density values of installed resistance 34 Table 5-1 : Measurement points for the wiring test 39 Table 5-2 : Test voltage points and values 40 Table 5-3 : Integration test signal values 41 FIGURES INDEX Figure 1-1 : Fusion power plant concept [1] 1 Figure 1-2 : Archetype of a tokamak structure 2 Figure 1-3 : Topology comparison of tokamaks: spherical and standard [5] 3 Figure 1-4 : PCS control hardware in the loop model [14] 4 Figure 1-5 : Concept closed loop control [15] 5 Figure 1-6 : Simulation of the control of the RZIp rigid plasma model [17] 5 Figure 1-7 : Example of a Hall-effect sensor produced by the Institute of Plasma Physics of the Czech Academy of Sciences [29] 6 Figure 1-8 : Example of a three-axis inductive sensor from the manufacturer NEOSID 7 Figure 1-9 : Topology and distribution of inductive sensors: poloidal flux loop, Rogowski coil, diamagnetic loop, magnetic field probe and saddle loop [26] 7 Figure 1-10 : Generic model of concentrated parameters of a magnetic coil. Self-parameters: inductance (Lp), resistance (Rp) and capacitance (Cp) [31] 8 Figure 1-11 : Generic Bode diagram of a sensor coil [32] 8 Figure 1-12 : Distributed parameter model of a connection line [33] 9 Figure 2-1 : Overall SMART architecture: (a)CAD model of the Vessel and Coils and (b) poloidal section of the tokamak [34] 11 Figure 2-2 : Current forms of the coils and plasma current [36] 12 Figure 2-3 : Voltage-controlled current source architecture of PS 12 Figure 2-4 : Summary of coil and PS connections in SMART 13 Figure 2-5 : Closed-loop control of plasma position and current 13 Figure 2-6 : General architecture of the SMART tokamak power suppliers 14 Figure 3-1 : Representation of the transfer function in the frequency domain: (a) Rogowski coil, (b) Integrator and (c) Combination of both [41] 17 Figure 3-2 : Scheme of integration techniques [41] 17 Figure 3-3 : Digital integrator architecture [31] 18 Figure 3-4 : Example of chopper integrator [46] 19 Figure 3-5 : Analog integrator architecture [31] 19 Figure 3-6 : Analog integrator circuit: (a) Passive and (b) Active [51] 19 Figure 3-7 : Configuration of operational amplifiers: (a) Inverting and b) Non-inverting 20 Figure 3-8 : Tore Supra reactor integrator drift test [55] 20 Figure 3-9 : EAST integrator circuit design [54] 21 Figure 3-10 : Integrator architecture installed in EAST [54] 21 Figure 3-11 : Servo compensation system on the WEST tokamak: (a) Analog design (b) Digital design [57] 21 Figure 3-12 : General master-slave integrator architecture 22 Figure 3-13 : System architecture: (a) Master and (b) Slave integrator [59] 22 Figure 3-14 : System architectures with ADCs on the integrator board [60] 23 Figure 3-15 : Hardware design of the integration system [59] 24 Figure 3-16 : Example of ATCA-MIMO-ISOL board developed by IPFN [65] 25 Figure 4-1 : Work rout map 27 Figure 4-2 : Block diagram of the integrator system 28 Figure 4-3 : Schematic of the OP-AMP configuration in the integrator circuit. Reprinted from [70] 28 Figure 4-4 : Reset circuit model 29 Figure 4-5 : Op-Amp total offset voltage model 30 Figure 4-6 : Equivalent input circuit 31 Figure 4-7 : Frequency response of the theoretical model of the integrator and the low-pass filter 32 Figure 4-8 : The results of the curves of the theoretical circuit simulated in Simulink® 33 Figure 4-9 : Result of integration into LTspice simulation. 33 Figure 4-10 : Frequency response of the complete system in the LTspice simulation 33 Figure 4-11 : Voltage Noise Density vs Frequency LTspice simulation 34 Figure 4-12 : Contribution to noise density by individual resistors 34 Figure 4-13 : Evolution of drift voltage: op-amp 1 (green), op-amp 2 (blue) and Output(red) 35 Figure 4-14 : Assembly of SMD components 36 Figure 4-15 : Assembly of through-hole components 36 Figure 4-16 : PCB inside the shielding case 36 Figure 4-17 : Layout of input and output signals 37 iii Glossary VDE Vertical Displacement Event TOKAMAK TOroidal’naya KAmera MAgnitnymi Katushkami SMART SMall Aspect Ratio Tokamak NBI Neutral Bean Injection PCS Plasma Control System RWM Resistive Wall Mode SISO Single input single output NTM Neoclassical Tearing Modes a Plasma minor radius Ro Plasma minor radius PS Power Supply ADC Analog-Digital Converter SAS Signal Acquisition Systems OP-AMP Operational amplifier PWM Pulse Width Modulation SMA SubMiniature version A RMS Root Mean Square PID Proportional Integral Derivative HIL Hardware in the Loop A Aspect ratio 1 INTRODUCTION 1.1 Nuclear fusion and fusion reactors Nuclear fusion of light atomic nuclei to form heavier atomic nuclei is one of the most common nuclear reactions in the universe. The mass deficit results in the release of energy according to Einstein's equation; therefore, the mass of the nucleus is directly related to both its potential energy and its binding energy, the energy needed to disassemble the atomic nucleus into its individual components. In fusion reactions, two nuclei must overcome the Coulombic interaction (electrostatic repulsion). The particles must come close enough and with enough energy to overcome the electrostatic repulsion between the positively charged nuclei for the fusion reaction to take place. In the case of stars, because of their enormous mass, the force of gravity is extreme, fusion reactions can occur simultaneously and spontaneously. On Earth, the force of gravity is low and, for fusion to take place, it is necessary to compensate for this fact by heating and compressing the material. The fuel of the fusion reactions (a mixture of Deuterium and Tritium in a D-T reaction) at elevated temperature is in a plasma state; in this case the electrons are separated from the ions, obtaining a fluid with electromagnetic properties. Under the proper conditions, the products of the D-T reaction are one Helium nucleus ( 𝐻𝑒 2 4 ) with a kinetic energy of 3.5 MeV and one neutron ( 𝑛 0 1) with 14.1 MeV represented in Equation (1–1). 𝐷 1 2+ 𝑇 1 3→𝐻𝑒 2 4+ 𝑛 + 17𝑀𝑒𝑉 0 1 (1–1) Strong magnetic fields contain the plasma at very high temperatures, allowing it to be compressed away from the walls of the vessel. Otherwise, the surface would be damaged by the enormous temperatures. This method is known as magnetic confinement method. The use of powerful lasers to compress a small fuel bullet is known as the inertial method. A conceptual fusion power plant as shown in Figure 1-1, where the thermal energy generated from the fusion reaction is converted into electrical energy through a traditional steam cycle, as a traditional thermal power plant. Figure 1-1 : Fusion power plant concept [1] Introduction 2 1.2 Magnetic confinement In nuclear fusion, the D-T mixture in plasma state can be confined, as mentioned in the previous section, through strong magnetic fields that keep the plasma away from the surface of the tank. The main characteristics of this technique will be described in this section. Magnetic confinement makes it possible to contain and maintain plasma at extremely high temperatures in a controlled medium, where the nuclei can fuse and release the massive amount of energy. There are two main topologies for achieving magnetic confinement: tokamaks and stellarators. Tokamaks are toroidal-shaped magnetic confinement devices that use a strong toroidal magnetic field combined with a poloidal magnetic field to keep the plasma in a circular trajectory. However, stellarators are more complex devices that employ helical magnetic fields to achieve plasma stability. The TOKAMAK (TOroidal’naya KAmera MAgnitnymi Katushkami) is the most investigated technology for fusion reactors. A summary of their parts is described in Figure 1-2. This device was devised by Soviet physicists in the 1950s. The inaugural tokamak, known as T-1, began operation in 1958. By the mid-1960s, tokamak designs began to demonstrate markedly superior performance. Promising results attracted further investment, leading to the development of larger devices such as the JET, JT-60, and TFTR in the 1980s. The largest example of public project investment is with ITER (International Thermonuclear Experimental Reactor), with a capital budget of more than 24 billion euros, it will start operations in 2025 [2]. Recently, private sector investments have formed private companies along the same lines, such as Commonwealth Fusion Systems (CFS), funded in 2018 with an investment of $1.8 billion according to The Wall Street Journal [3]. Figure 1-2 : Archetype of a tokamak structure [4] The basic structure of a tokamak is usually composed of the same elements: • Toroidal magnetic Fiel Coils: its main function is to confine the plasma, as it is the major component of the magnetic field in a tokamak. • Poloidal magnetic Field Coils: the poloidal field generated by the coils is perpendicular to the main toroidal magnetic field created by the toroidal coils (next point), critical to control and stabilise the plasma, as well as its shape, position, and possible parasitic currents mitigations. • Central Solenoid: like the primary of a transformer, the solenoid induces an electromotive force that initiates and maintains the plasma current producing a poloidal magnetic field. The slope of its current makes it possible to modify the plasma current. It is constituted by an air core in order to avoid saturation regimes. • Vacuum Vessel: The plasma generated is housed inside, it is the physical tank, the interior of which is under ultra-high vacuum and is usually made of non-ferromagnetic materials. It is used as a chassis for auxiliary elements and must support important loads, materials such as Stainless Steel (SS) - 316 are normally used. The topology of the vacuum vessel is closely related to the plasma shape to be obtained. The tokamaks are 3 classified according to the ratio between their major and minor radii, described in Figure 1-3. The minor radius is defined as the distance between the centre of the plasma and its surface. The major radius is defined as the distance between the centre of the plasma and the axis of revolution. They are classified as: low aspect ratio (spherical tokamak) and large aspect ratio (standard tokamak), they are described in Figure 1-3. The spherical topology allows for greater simplicity of parts and maintenance. The natural elongation shape (without shaping fields) of the plasma makes it less susceptible to vertical instabilities. The more compact design makes the use of external magnetic fields more efficient [5], [6]. Projects like Spherical Torus Experiment (STX) previously known as START, ST-40, NSTX-U or Pegasus have contributed to the testing of spherical tokamaks. In Spain, SMART (SMall Aspect Ratio Tokamak) is being built, it is described in the next Section 2. It is a compact design tokamak that aims to obtain different plasma geometries that were not previously studied in this tokamak topology [7]. Figure 1-3 : Topology comparison of tokamaks: spherical and standard [4] Once the general parts of a tokamak have been outlined, it is necessary to define other parts or elements that have to be considered for their operation. First, a power supply is needed to generate and control the huge currents (>1 kA ) flowing through each of the coils to generate the required magnetic fields. Obtaining an ultrahigh vacuum (10-10 Torr) inside the chamber is essential for successful operation. On the other hand, it is possible to increase the plasma temperature by means of the ohmic effect and the use of the central solenoid, but this technique is not sufficient and, for this purpose, radio frequencies, such as microwaves (~kW) or high energy particle injections with the Neutral Bean Injection (NBI) are used. 1.3 Tokamak plasma control The hot ionised gas (plasma) is confined inside of the vessel for a specific period to facilitate the fusion reactions. A combination of externally applied toroidal and poloidal magnetic fields, together with a poloidal magnetic field generated by a substantial current flowing within the plasma itself, is used to contain this ionised gas away from the vessel walls. The synchrony between the solenoid, coils, fuel control, and NBI enables plasma regimes to be achieved according to the case studies. The 2D position control is a basic control in the poloidal plane, where the magnetic field generated by the poloidal coils is adjusted in combination with the current induced by the solenoid to adjust the plasma to the required position and shape. It is one of the most simple and primary controls, and it will be described in the following section. 1.3.1 Plasma current control The central solenoid, as described before, generates an electromotive force that establishes the plasma current. There is consequently a correlation between the voltage applied to the solenoid (𝑉𝑐) and the plasma current obtained (𝐼𝑝). Values such as inductance (𝐿𝑐) and resistance (𝑅𝑐) of the solenoid and the plasma (𝐿𝑝,𝑅𝑝) as well as their mutual inductance (𝑀𝑝𝑐) are values which influence according to the next transfer function SISO presented in Equation (1–2). 2 TOKAMAK SMART This chapter provides a more detailed description of the implementation of a first control system for the SMART Tokamak. A review of the confinement coils installed in the tokamak is carried out, as well as the PS used to supply the required current. The response times of the PS are evaluated as a function of their architecture. 2.1 Overview The Tokamak SMART has a compact design (Ro = 0.4 m, a = 0.25 m, A<2) with the aim of being cost-effective, having educational purposes, and providing a high versatility in nuclear fusion research. It will explore positive and negative triangularity in this spherical topology, as well as serve as a platform in control system development, diagnostics, high elongation (κ<2.3) and different divertor configuration (single/double null divertor). This will provide an excellent training ground for researchers in this area [38]. SMART tokamak is currently in the assembly and testing phase. Figure 2-1 describes the construction parts of SMART. Figure 2-1 : Overall SMART architecture: (a)CAD model of the Vessel and Coils and (b) poloidal section of the tokamak [38] Firstly, the vessel, made of AISI 316 L, is coloured in grey. All the coils necessary for the operation are mechanically installed on it [39]. The solenoid was installed in the central part, where toroidal field coils are connected on the inside (coloured orange). The structure must support the combined stresses, interesting studies have validated these designs [7]. Finally, the coils in the toroidal section (coloured yellow) consist of poloidal field coils (PFC) and divertor coils (Div). Tokamak SMART 12 Figure 2-2 : Current forms of the coils and plasma current [40] The currents required for the operation have been obtained through axisymmetric Grad-Shafranov force balance solver (FIESTA) in conjunction with the rigid current displacement model (RZIp) [41]. The currents exported from the simulations (Figure 2-2) will be transferred to the control systems of the power supplies connected to each coil in order to sequence and manage all the coils [42]. The installed power supplies require a detailed analysis which will be described in the following section. 2.2 Power supplies Power Supplies (PS) are connected to the coils to obtain the expected magnetic fields. There are many topologies and architectures that solve this need. In SMART, a modular design has been created that allows scaling and increasing the design power by adding a greater number of units. Its technology is based on supercapacitors such as energy storage systems and Insulated Gate Bipolar Transistors (IGBTs) with modulation for power control (PWM). Figure 2-3 : Voltage-controlled current source architecture of PS All architectures are based on a voltage controlled current source as described in Figure 2-3. The function of the control loop is to measure the output current and adjust the trigger times of the PWM control to adjust the output voltage and thus obtain the required current. The predefined current curves are transferred through an ethernet cable to each module that manages a specific group of coils. A master PC sequences all the power supplies that control each coil through a trigger signal. Each of the PS provides the specified current at the specified time. Toroidal, divertor, poloidal, and solenoid coils have a crucial role in the operation of the fusion reactor, and they are powered independently by the PS, as illustrated in Figure 2-4. These coils are integral components of the magnetic confinement system, which is at the core of controlling and stabilising the superheated plasma within the reactor vessel. A centralised control system manages the operation of these coils and ensures that they are supplied with the appropriate currents according to predefined curves. These predefined curves are derived from extensive simulations and research, providing a baseline for plasma control. However, it is important to note that a real discharge operation within the fusion reactor cannot be completely predefined. Figure 2-4 : Summary of coil and PS connections in SMART The complex and dynamic nature of plasma behaviour implies that unexpected variations and instabilities can occur. The use of real-time data and feedback mechanisms to adjust and fine-tune the operation is fundamental to control of the plasma and to obtain the required specifications, ensuring that it remains stable, confined, and at the necessary temperature. For this reason, real-time control of the coils in SMART is necessary. By design, the PS of the Div2 coils have a fast communication bus to inject the current setpoints in real time. 2.3 First control loop design There are many control architectures, an adaptation of the control loop presented in Figure 1-5 will be made in this section. For this purpose, two loops are connected, one after the other. The first loop is the current control loop, already defined in Figure 2-3. On top of this loop is the adjustment and reconstruction control loop. A simple control model has been proposed in Figure 2-5. This loop is intended to give a general idea of the operating times at which the system can operate and, therefore, what its expected response speed can be. Firstly, the measurements are defined by the 𝑇𝐶.𝑚.𝑠 and 𝑇𝑃.𝑚.𝑠 time constants, these time constants are determined by the type of sensor (Section 1.5), as well as by the capacitances and inductances in the conduction as described in Section 1.7; the use of signal adaptive electronics such as integrators up to the data acquisition systems. Figure 2-5 : Closed-loop control of plasma position and current Signals are digitised through the Analog Digital Converter (ADC) and are delayed by the sample and hold method used to capture the signal level, represented by 𝑇𝑆𝐻 constant. The time constant 𝑇𝑟𝑒𝑐 , represents the specific value of time that the reconstruction code takes. It adds the times of communication between buses, Tokamak SMART 14 signal concentration, processing, and obtaining the value of the plasma current 𝐼𝑝𝑙 (𝑘) or position 𝑅𝑐 𝑍𝑐(𝑘). 𝑇𝑐𝑜𝑖𝑙 represents the time constant due to the RL circuit formed by the active coil. And finally, 𝑇𝑃𝑠 represents the time constant associated with the switching of the IGBT and the time constant of the filter at the output of the PS. Once the control loop is defined, the actual characteristics of the installed components will be analysed in order to evaluate their response time. 2.3.1 Control loop features This section describes some actual characteristics of components already installed or under design. It is intended to provide a preliminary calculation guide to be used in the future as a basic calculation for more robust and better-defined control systems. According to the loop presented in the previous chapter (Figure 2-5) it is proposed to define the current control loop and the current control bubble. For this case, two control circuits have been analysed: DIV2 and solenoid PS. 2.3.1.1 Current loop Open-loop control mainly involves PID control, the switching circuit, and the active coils. The PID, consisting only of its proportional and derivative part, has a time constant of 𝜏𝑐𝑙 = 0.63∗ 0.5 ms[43]. The rest of the constants are obtained through the values of the installed physical components. Figure 2-6 : General architecture of SMART tokamak power suppliers The construction of all PS installed in SMART is similar, although there are differences according to the needs or requirements of the coil to which it is connected, an example of this architecture is presented in Figure 2-6, and will be taken as a reference for the calculation of the time constants. In this model some elements have been simplified, but it is enough to obtain an approximate value. The LC filter installed in both PS have the same constructive characteristics of different value as expressed in the Table 2-1. It consists of an LC circuit and its transfer function presented in Equation (2–1). 𝑉𝑜(𝑠) 𝑉𝑖(𝑠)=1/𝐿𝑓𝐶𝑓 𝑠2+𝑅𝑠 𝐿𝑓𝑠+ 1 𝐿𝑓𝐶𝑓 (2–1) The resistance of the supercapacitor bank is presented by 𝑅𝑠 where it is connected in series with the filter. The supercapacitor has a capacitance of several farads, does not consider the possible discharge, and is considered as an ideal source. The IGBTs used (5SNA 3600E170300) have a response time of 10 µs according to the datasheet. The output of the PS is connected to a coil which creates a magnetic field according to the needs imposed by the control. This magnetic field is created through a variable current (𝐼𝑐) imposed by the voltage variations of the PS (𝑉𝑝𝑠). The active coil, disregarding the characteristics of the connection cables, behaves like a basic LR circuit presented in Equation (2–2). The values are described in the Table 2-1. 𝐼𝑐(𝑠) 𝑉𝑝𝑠(𝑠)=1/𝑅𝑐 𝐿𝑐 𝑅𝑐𝑠+ 1 (2–2) A transducer from the HAX1000-S range from the manufacturer LEN was used to capture the signal. According to the datasheet, it has a response time of less than 5 µs. This value has been taken as its delay constant. The discretisation time is considered to be well below this value and will therefore not be taken into account in the control loop. The complete transfer function of this control loop has been obtained, according to the characteristics of the components presented in Table 2-1, also considering the delays introduced by the switching of the IGBTs. The total time constant is 725.3 µs for the solenoid loop and 775.7 µs for the DIV2 control loop (Table 2-1). Both constants have been considered to give 63% of the final target value. Table 2-1 : Power supply features Parameter C. Solenoid 2xDiv2 Coil resistance (mΩ) 33.4 2*14.9 Coil inductance (mH) 1.93 2*1.42 Filter L (µH) 15.0 6.7 Filter C (mF) 13.5 30.2 Number of supercapacitors in the bank 4 5 Serie bank resistance (mΩ) 6.2 3.3 Constant open loop (µs) 725.3 775.7 2.3.1.2 Position loop The position loop has as a strategy to adjust the error made in both the current and the plasma position. By having two nested loops and for correct tuning, the integration constant of the PI control is set to a value 10 higher than the constant taken for the current control loop. The PI integration constant is therefore 𝜏𝑐𝑙 = 3.15 ms. The time constants of the sensors cannot be included in this section, as they have not yet been prototyped and are still in the design phase. The signal adaptation is performed by an analogue integrator which is described in the next chapter. The digitiser used is a PXIe-6349 from the supplier National Instrument, with a latency of 2 µs. The reconstruction of the plasma can introduce a long delay in the loop; therefore, the following formula should be considered to evaluate its time constant: 𝜏= ∑(𝑇𝑓𝑢𝑛) 𝑁 0. It is therefore considered that the minimum value that the whole calculation will take is equal to the sum of all the times associated with each individual operation (𝑇𝑓𝑢𝑛), considering basic mathematical operations (addition, subtraction...). In the literature, control operations range from 50 µs to 10 ms actuation [44]. Parameters such as the total pulse duration or the plasma constant (maximum flow variation that can occur in a differential time) determine the individual reactor constants. These parameters are currently being studied for the SMART tokamak. 3 REFERENCE INTEGRATOR DEVICE The voltage induced in the magnetic coils must be integrated to measure the value of the magnetic field generated and not the differential value with respect to time. There are different integration techniques with their associated hardware and software solutions. In this chapter, an introduction to integrators and their application in nuclear fusion is introduced. 3.1 Introduction As described in Section 1.6, the output signal of the magnetic sensors must be integrated. A simplified bode diagram is shown in Figure 3-1. The transfer function of the Rogowski coil, which works as a high-pass filter up to its cut-off frequency 𝑓𝐻. On the other side, the integrator has a transfer function similar to that of a low-pass filter with cut-off frequency 𝑓𝐿. The conjunction of both transfer functions has a constant gain between the frequencies 𝑓𝐿 and 𝑓𝐻. These frequencies define the bandwidth of the integrator. The magnetic flux measured by the magnetic sensor has a constant gain that is not dependent on the frequency of the signal at the output of the integrator. Figure 3-1 : Representation of the transfer function in the frequency domain: (a) Rogowski coil, (b) Integrator, and (c) Combination of both [45] There are different methods (Figure 3-2) to perform the mathematical function of integration function such as software as hardware. Each offer advantages and disadvantages in terms of complexity, cost, speed, noise immunity, and bandwidth. Figure 3-2 : Scheme of integration techniques [45] Out-Integration techniques require special consideration. They can be categorised into two main groups: active and passive integrators. Digital integration is the use of computer codes and programmes based on mathematical algorithms to integrate the signal. Analogue integration uses electronic components to perform mathematical functions. The components can be active or passive, and each of them has different characteristics. All these integrators are described in the following sections. In an ideal situation, the integrated output is only due to the integration of the signal being measured. In a real application an additional voltage is known as drift voltage. The value of the drift voltage induces errors that must be identified. It is one of the main characteristics taken into account in integration systems. Reference Integrator Device 18 3.2 Digital integrator Digital integration has been used as a method to perform real-time integration of magnetic sensor signals. The mathematical operation in the continuous domain must be adapted to the discrete-time domain. An algorithm based on summations [46], is represented by Equation (3-1). 𝑦𝑘=1 𝑅∑(𝑥𝑛−𝑋) 𝑘 𝑛=0 −1 𝑅∑(𝑏𝑛−𝐵) 𝑘 𝑛=0 (3–1) The integral is defined as a sum of the values sampled divided by the number of samples collected in the interval. The parameter 𝑥𝑛 describes the digitized value in the at time k, 𝑏𝑛 defines the measured parameter, and X and B are constant setting value. R defines the number of samples in the range k. The integrated output value is 𝑦𝑘. Sampled signals have an important process from the physical domain to the digital domain. First the signal is adapted to the appropriate voltage levels, in this case the hardware architecture depends very much on the type of signal. The signal can be amplified, attenuated, or converted (current level to voltage) [47]. The signal is filtered according to the signal bandwidth and sampling frequency of the analogue-to-digital converter (antialiasing filter). At this stage, signals that are not of interest for the measurement are filtered out. The frequencies that exceed half of the sampling frequency according to the Nyquist-Shannon theorem are filtered [48] and finally it is digitized through an Analog-Digital Converter (ADC). Two main processes involve: quantification and encoding. In quantisation, the signal is divided into different voltage levels, and coding is the assignment of a binary value according to specific hardware and software considerations. According to the conversion speed and bit size of the encoding, there are different architectures such as: Flash ADC, Pipeline ADC or Sigma-Delta ADC and others [49]. The signal part is isolated from the control part by galvanic isolation. It also includes auxiliary memories or registers to store data such as the sum of the integration. The data have two routes, the storage for post-processing and for the real-time control process described in Figure 3-3. Figure 3-3 : Digital integrator architecture [35] A prototype integrator on the DIII-D tokamak was proposed and designed for use in ITER. It allows a pulse integration of up to 1200 s whit 5 mVs of drift error approximately. It has an RC filter with the objective of eliminating high frequencies and attenuating the overvoltage produced in the measurement of the magnetic sensors. It also includes an amplifier stage and an ADC [46]. To mitigate the effect of drift, the chopper technique was introduced. This method allows attenuating the offset errors as well as the variations due to thermal drifts. These integrators allow to obtain a high accuracy. In [50] is described a chopper integrator used in the tokamak EAST, with a 300 µVs drift in pulse duration of 1000 s. The input signal is switched according to a clock signal (the input signal is inverted at a specific frequency by a switch written in the circuit of Figure 3-4) but different topologies are possible. Switching constants are stored for use in signal demodulation. The signal is integrated according to the programme algorithms used for synchronous rectification of the chopped signal, resulting in a significant elimination of the drift voltage and reduction of the 1 / f of the noise signal. Can be used as a high-pass filter if the switching frequency is appropriate [51]. The use of this technique has also been done in ITER [52], with remarkably positive results. Twelve architectures were evaluated, with various types of anti-aliasing filters and types of ADCs (SAR, ΔS and ΔΣ). The maximum drift achieved was 250 µVs. Other results taken from the COMPAS experiments show that there is no large drift or loss of information due to chopper noise. COMPASS experiments show that there is no large drift or loss of information due to chopper noise. The experience gathered in these tests will be the basis for the construction of the new acquisition systems to be installed in COMPASS-U based on ATCA [53]. Figure 3-4 : Example of a chopper integrator [50] Recent research in this area has introduced digital integration algorithms using high-speed analogue-to-digital converters with very satisfactory results [54]. This technology allows for rapid development and simple simulation; in addition, it introduces the possibility of using specialised digital filters for the type of signal being measured, introducing the quantised signal directly into the control loop. As a disadvantage, to comply with high quality indexes it needs a high bandwidth and immunity to strong magnetic fields. 3.3 Analogue integrator Analog integrators need a different external component to operate. A timing decoder is essential to synchronise the integration and analogue-to-digital conversion. The analogue integrator is connected to the ADC as shown for digital integrators. The signals are captured by two acquisition system, for real time processing and for post pulse processing shows in Figure 3-5. Figure 3-5 : Analogue integrator architecture [35] The signal integration module may be composed of simple a circuit formed by passive elements as a resistor and capacitor shown in Figure 3-6 a). This would function as a low pass filter and is considered one of the simple ways to achieve integration, however, it introduces a natural attenuation of the signal and a low input impedance [55]. These types of integrators have been used in the field of partial discharges because of their simplicity and bandwidth of up to 500 MHz [56]. Passive integrators are consequently used for high frequency applications, while active integrators, based on operational amplifiers (Figure 3-6 b), are used in lower frequency applications [57]. Figure 3-6 : Analogue integrator circuit: (a) Passive and (b) Active [55] Reference Integrator Device 26 A digital integrator has been developed to mount on the board presented previously. A PCB was designed with the same topology as the modules intended for signal adaptation and digitisation, this new design had the function of a digital integrator with very significant results and will be used in COMPASS-U [53]. It is important to take into account all existing architectures to guide future designs that will be supported by these platforms. The following chapter will describe the design of an analogue integrator prototype. 4 INTEGRATOR DESIGN In this chapter, the integration function required to adapt the signal from the Rogowski coil to the current measurement in the tokamak SMART will be solved. According to functionality and cost, an analogue integrator will be used. A non-inverting configuration of op-amp has been selected due to the unavailability of components. The design and construction of this circuit will allow to gain a lot of experience in PCB design, as well as, to allow to make modifications and to be the basis for signal adaption systems for future designs. The possibility of a digital integrator is discarded as the data acquisition system is already built and the addition of a chopper system for drift control could be complex. The development of a separate acquisition system is also not justified due to the high cost and time required for its development. Therefore, the criteria of simplicity, economy, and development efficiency have been chosen. The workflow is described in Figure 4-1, first of all, the basic requirements of the integrator were defined, as well as some electrical and mechanical quantities. An architecture was designed to meet the described needs, and the components to be used were selected. MATLAB together with Simulink® supported the theoretical analysis part of the design, offering a high speed in the design calculation. Once the theoretical model were correct, the data was exported to LTspice, where the real components were simulated. The data exported from the real simulation was checked to be within the limits imposed by the requirements. For the manufacturing of the physical circuit, all the hardware was designed in EasyEda and manufactured by JLPCB. Figure 4-1 : Work rout map 4.1 Integrator requirements For integrator design, it is necessary to delineate the prerequisites of the system under evaluation. They are as follows. • The system must execute the mathematical integration function. • The system must be modular and configurable. • The system must provide the internal temperature of its circuits. • The system must have a high input impedance. • The system must maintain a relation between functionality and cost. • The system must have a reference isolated from the physical ground. The technical requirements of the system, which are specific to certain functions, are also described: • The system must operate with a range of input voltages from 1 to 50 v. • The system shall have a full-scale output of ±10 V. • The system shall be capable of operating at a DC voltage of 12 V. • The system shall withstand an overvoltage of 1000 V. • The system shall filter overvoltage. Integrator Design 28 28 • The system shall have SMA type connections for signal inputs and outputs. • The system shall guarantee a maximum operating deviation of 0.5 % of full voltage scale during operation. • The system will have a reset to remote integration. 4.2 Architecture According to the specifications, a conceptual diagram is presented in Figure 4-2, a TVS diode (Transient Voltage Suppressor) will be installed [58], and a Low Pass Filter (LPF) will further attenuate the overvoltage that may occur in the magnetic sensors. The board will be connected through an AC-DC 220 V 50hz voltage source. Relays will be used to reset the integration time. A temperature sensor will be connected and installed in the circuit to provide board status information, the data obtained will be processed by high-level algorithms to correct for temperature deviations and increase the calibration speed in real operation, and a set of op-amps will provide the necessary integration function. Figure 4-2 : Block diagram of the integrator system Due to the current geopolitical situation and international markets, there is an important deficit in electronic components. In this context, the circuit has had to address these considerations. One of the most significant points was the galvanic isolation between the signals. As the construction of a digital integrator was discarded, optocoupling is not an option. Analogue isolation amplifiers could be used, but those available on the market at the time of development did not satisfy the requirements. For this reason, the integrator circuit is based on a noninverting configuration of op-amps. To mitigate the drift effect, an architecture similar to the one presented in [74] has been selected, but with a new configuration of the integrating op-amps as described in Figure 4-3. Figure 4-3 : Schematic of the op-amp configuration in the integrator circuit. Reprinted from [74] The architecture presented in Figure 4-3 offers a reduction in the components used compared to the one already presented in the bibliography [58], based on the self-compensation of the drift from a symmetric circuit (two op-amps have been removed). The high impedance is achieved with a non-inverting configuration, and no instrumentation amplifier is used. Compared to the architecture presented in [74], the isolation amplifier is eliminated because of the impedance offered by this configuration. Therefore, this configuration is cheaper and initially with less latency. In addition, the TVS is maintained to protect against possible overvoltage. 1 2 4.2.1 Resetting architecture The integration time is the instant at which the signal is to be evaluated and, therefore, integrated. The main signal is integrated, as well as the sum of all signal levels at the input of the op-amp, regardless of the input signal being connected or not. For this reason, the instant of integration must begin when evaluating the input signal, and there are many strategies for this purpose. One strategy is to short-circuit the integrating capacitor, ideally obtaining a voltage of 0 V. A MOSFET transistor can be used as a switching element, but the polarisation of the capacitor can change according to the signal and a high impedance is necessary so as not to affect the established transfer function. In addition, it induces parasitic capacities characteristic of these elements. Nondesirable effects. As a solution, it is proposed to use a relay connected to both terminals of the capacitor as described in Figure 4-4. Figure 4-4 : Reset circuit model The relay will be used in its normally connected format, and once it is energised, it will open to start the integration period. This device has a high resistance when opened and can accept the short-circuit current of the capacitor. It also has galvanic isolation from the control signal. The disadvantage is that it has a certain latency or delay in the opening time that must be evaluated in order to include it in the control time margins of the device. 4.3 Component selection Depending on the requirements of the circuit, different components were used; an overview is given in this chapter. The Annex C can be used as a guide for clarity. These included miniature KEMET EC2/EE2 signal relays to reset the integration time. Its small format and low power consumption offer excellent characteristics to be implemented in this circuit. There are many other types of relays on the market, and this component should be reviewed to reduce its size as much as possible. It is expected that in future circuits only one instead of two will be used. To operate the relays, the DRDNB21D-7 drivers were installed from the manufacturer Diodes Incorporated. An Ultralow Noise and EMI enhanced ADA4522-1 op-amp was used, serving in the integrator circuit. Capacitors for energy storage, based on polypropylene material with low dielectric loss and low leakage current are used. The TVS diode is SMCJ45, from manufacturer Littelfuse®, protecting the input from transients of up to 1KV. The sensor for PCB temperature monitoring is TMP1075 with Digital interfaces: SMBus and I2C. SMA connectors for input and output signals, a DB-9 connector for data transmission, a DC-DC switching power supply for efficient voltage insolation (RS PRO 1W isolated DC-DC converter), voltage regulators to maintain stable power levels, and various passive components. Each component played a crucial role in achieving the circuit's intended functionality, with specific attributes and specifications tailored to their respective tasks. The total circuit component is described in Annex C. 4.4 Theorical model In this section, a theoretical model of the different characteristics of the circuit is described, such as the transfer function (voltage gain), the voltage drift, the input impedance, CMRR, or the random noise introduced by the resistors. 4.4.1 Voltage gain The gain of the low-pass filter in the Laplace domain is defined by: Integrator Design 30 30 𝐺1(𝑠)=𝑉ℎ𝑓(𝑠) 𝑉𝑖𝑛(𝑠)=1 𝑅ℎ𝑓𝐶ℎ𝑓 1 𝑠+1 𝑅ℎ𝑓𝐶ℎ𝑓 ⁄ (4–1) The gain of the integrator circuit (1 and 2 op-amp) in the Laplace domain is defined by: 𝐺2(𝑠)=𝑉𝑂3(𝑠) 𝑉ℎ𝑓(𝑠)=𝑠+(𝑅1+𝑅𝑓) (𝑅1𝑅𝑓𝐶1) ⁄ 𝑠+1 𝑅𝑓𝐶1 ⁄ (4–2) The Laplace domain differential amplifier gain is defined by: 𝐺3(𝑠)=𝑉𝑜𝑢𝑡 𝑉𝑜𝑝1−𝑉𝑜𝑝2=𝑅𝑎 𝑅𝑏 (4–3) 𝐼𝑓 𝑅𝑎=𝑅𝑏→ 𝐺3(𝑠)=1 (4–4) The final gain of the system in the Laplace domain is expressed as: 𝐺(𝑠)=𝐺1(𝑠)∗ 𝐺2(𝑠)= 1 𝑅ℎ𝑓𝐶ℎ𝑓 1 𝑠+1 𝑅ℎ𝑓𝐶ℎ𝑓 ⁄𝑠+(𝑅1+𝑅𝑓) (𝑅1𝑅𝑓𝐶) ⁄ 𝑠+1 𝑅𝑓𝐶 ⁄ (4–5) 𝐼𝑓 𝑅ℎ𝑓𝐶ℎ𝑓 =(𝑅1𝑅𝑓𝐶) (𝑅1+𝑅𝑓) ⁄→ 𝐺(𝑠)= (𝑅1+𝑅𝑓) (𝑅1𝑅𝑓𝐶) ⁄ 𝑠+1 𝑅𝑓𝐶 ⁄ (4–6) 4.4.2 Voltage drift The integrator circuit by the design of the op-amp has a bias current, an offset current, and an offset voltage. These quantities, in addition to the measured signal, are integrated and cause an increasing linear offset over time in the integration output, known as drift (described in Section 3.3). It was presented in Figure 4-5. Figure 4-5 : Op-Amp total offset voltage model The mathematical models are described. Offset voltage Voff, IB+, as bias current in the non-inverting connection, and IB-, as bias current in the inverting connection. 𝑉𝑜𝑢𝑡(𝑡)= −∫𝐼𝑐𝑑𝑡 𝐶+𝑉𝑎(𝑡) (4–7) 𝑉𝑜𝑢𝑡(𝑡)= 𝑅𝑓𝐼𝑅1(𝑡)+𝑉𝑎(𝑡) (4–8) 𝐼𝑐1(𝑡)=𝐼𝑅1−𝐼𝐵 −−𝐼𝑅𝑓 (4–9) 𝑉𝑜𝑢𝑡(𝑡)=−1 𝐶∫[𝑉𝑎 𝑅1−𝐼𝐵 −−(𝑉𝑜𝑢𝑡 −𝑉𝑎 𝑅𝑓)]+𝑉𝑎(𝑡) (4–10) 𝑂𝐹𝐹𝑆𝐸𝑇 (𝑅𝑇𝑂)= 𝑉𝑜𝑢𝑡(𝑡,𝐼𝐵,𝑉𝑜𝑠)=1 𝑅𝑓𝐶1[(1+𝑅1 𝑅𝑓)𝑉𝑜𝑠 +(1+𝑅1 𝑅𝑓)𝑅𝑝𝐼𝐵 +−𝑅1𝐼𝐵 −](1−𝑒 −𝑡 𝑅𝑓𝐶1) (4–11) The OFFSET (RTO) value describes how the output voltage is due to offset currents and voltages. Both a large capacitor and a high resistance (𝑅𝑓𝐶1) lead to long charging periods and therefore to a decrease of the drift slope. Although capacitor and resistor values are defined by the bandwidth and integration characteristics, it is possible to attenuate the effect of these voltages and currents by evaluating the input level. Therefore, the input offset value, 𝑂𝐹𝐹𝑆𝐸𝑇 (𝑅𝑇𝐼), is defined as follows: 𝑂𝐹𝐹𝑆𝐸𝑇 (𝑅𝑇𝐼)=𝑉𝑜𝑠+𝐼𝐵+𝑅𝑝−𝐼𝐵−𝑅𝑓𝑅1 𝑅𝑓+𝑅1 (4–12) 𝑂𝐹𝐹𝑆𝐸𝑇 (𝑅𝑇𝐼)=𝑉𝑜𝑠 𝑖𝑓 𝐼𝐵+= 𝐼𝐵− 𝑎𝑛𝑑 𝑅𝑝= 𝑅𝑓𝑅1 𝑅𝑓+𝑅1 (4–13) An adequate ratio between the biasing resistors (𝑅𝑝) and the other resistors allows to reduce the input value of the offset voltage of the operational amplifier. 4.4.3 Input impedance The equivalent input impedance circuit is shown in Figure 4-6, the op-amp has been considered to have an infinite impedance at its non-inverting input. On the other hand, it has been considered that the TVS does not have any parallel impedance. In the experimental models, its real impact will have to be evaluated. Figure 4-6 : Equivalent input circuit The final value of the impedance in the Laplace domain is expressed as: 𝑍𝑖𝑛(𝑠)=2𝑅𝐻𝑓+2𝑅𝑝𝑠 𝑠+2𝑅𝑝 𝐶𝐻𝑓 (4–14) 4.4.4 CMRR It is considered that for a CMRR = ∞, the resistance ratio must be 𝑅1=𝑅3 and 𝑅2=𝑅4, due to the different configuration of the op-amp in the last section (Figure 4-3). This consideration should be measured in the actual implementation of the circuit [74]. 4.4.5 Random noise Thermal agitation of charge carriers in electrical conductors has influence on electronic devices. When electrical resistance is applied at a certain temperature, the inherent randomness of the kinetic energy of the electrons leads to voltage variations known as Johnson noise [75]. Equation (4–15) shows that the power spectral density 𝐸𝑛(𝑉/𝐻𝑧) of the voltage noise is directly proportional to the absolute temperature 𝑇 (𝐾), the resistance 𝐸𝑛(Ω), and the observation bandwidth ∆𝑓 (𝐻𝑧). The higher the temperature, resistance or bandwidth, the higher the voltage noise level. 𝐸𝑛= √4𝑘𝑇𝑅 ∆𝑓 (4–15) Integrator Design 32 32 According to [76] integrator circuits, the effect of Johnson noise on the resistors can be neglected, due to the large capacitor connected as feedback. In the final stage of the differential amplifier, the noise introduced by resistors must be calculated. 4.5 Circuit simulation MATLAB has been used in the initial phase to allow simple analysis of circuit behaviour, transfer functions, and characteristics in the Laplace domain. As a design condition, the high capacitor C1 value is set; this causes the resistance R1 values to be as small as possible and mitigates the impact of the offset current. For this purpose, it is set to 10 µF (in the reference [60] the value is 1 µF). The effect of the capacitor on the overall transfer function is to increase the cutoff frequency as its value decreases [77]. The time constant is defined as 20 ms (27 ms in [59]) according to the current curve to be integrated. According to [78] it is described as a criterion that 𝑅𝑓=1000∗𝑅1. Taking these considerations and the one already described by the transfer function G(s) in Section 4.4.1. The set values are described in Table 4-1. Table 4-1 : Circuit component values Component Value 𝑅𝑓 (MΩ) 33.4 𝑅1(KΩ) 3.33 𝑅ℎ𝑓 (KΩ) 33.3 𝑅𝑝(KΩ) 10 𝐶1(µF) 10 𝐶ℎ𝑓(µF) 1 The exported value was substituted into the integrator function G (s), which providing the transfer function described in Figure 4-7. Signals with frequencies below 50 Hz are attenuated by 1 dB, but not integrated. This behaviour has been achieved by the Rf resistor which prevents low frequency signals from saturating the integrator. All other frequencies are integrated. Phase characteristics over the entire integration range are important, as this avoids different delays depending on the signal being measured. At low frequencies there is some transition from 0 to 90 degrees, and it stays static over most of the integration range. Figure 4-7 : Frequency response of the theoretical model of the integrator and the low-pass filter A similar circuit shown in Figure 4-3 was implemented in the MATLAB tool through Simulink® and Simscape™. The selected values from Table 4-1 were substituted. The expected current curve was recreated, and a derivative function was applied to it, obtaining the signal expected by the Rogowski coil; this signal was connected to the circuit and the signal at the output of the integrator was similar to that of the plasma currents illustrated in Figure 4-8, results that were expected according to the simulated specifications. Figure 4-8 : The results of the curves of the theoretical circuit simulated in Simulink® A higher fidelity of reality was achieved with the LTspice® electronic circuit simulator which is a powerful free software from the distributor Analog Devices. The op-amp models specified (ADA4522-1) are the same as those used in the simulation including non-ideal characteristics. This simulation has provided a better understanding of the behaviour of the complete system. The study circuit was made according to the architecture presented in Figure 4-4, for further clarification see Annex B. First, a verification test was performed with the same input signal (Rogowski measurement) on the circuit used in the MATLAB simulation (Figure 4-8). In the real component simulation presented in Figure 4-9 an offset voltage was also found at the output not higher than 150 µV, conforms with the requirements imposed, and that the integration is perfectly obtained, thus the plasma current with the characteristic shape. Figure 4-9 : Result of integration into LTspice simulation. Red line the input signal; green line the input signal. The frequency response is shown in Figure 4-10, and values that differ somewhat from those exported in the theoretical model expressed in Figure 4-7 have been obtained; this is due to the readjustments that have had to be made to the component values. Figure 4-10 : Frequency response of the complete system in the LTspice simulation There has been a vertical shift in the frequency response upward as the value of the resistance Rf has increased. The latency of the system is <800 ns over the full bandwidth of 10 Hz to 100 kHz. (V/s) Delay (ms) Gain (dB) Integrator Design 34 34 The noise density of the circuit has been evaluated. This noise comes mainly from the installed resistors, a high value or a high temperature leads to a higher noise level (previously described in Section 4.4.5). In Figure 4-11 is described the noise level of the whole circuit. Figure 4-11 : Voltage Noise Density vs Frequency LTspice simulation The total rms noise level at the output (green line) is 6.04 V. in the range from 1-100 kHz. The allowed input noise level (blue line) must be below 72.224 mV rms; in this case, the output noise will be less than 6.04 µV and will be masked by the noise of the integrator circuit itself. The gain of the system is described by the red line; it works as a low-pass filter, as described in the integration function, with the noise level it has the same behaviour. Figure 4-12 : Contribution to noise density by individual resistors The spectral density of each individual resistor was obtained to evaluate the influence of each resistor as described in Figure 4-12. The major contribution between 0-19.6 Hz is provided by the resistor associated with the low-pass filter circuit (green line). In the rest of the band, the major influence is provided by the amplifier resistors in differential configuration (pink line). Table 4-2 : Individual noise density values of installed resistance Component Voltage(rms) 𝑅𝑓 1.34 nV 𝑅1 38.72 nV 𝑅𝑜 80.53 nV 𝑅𝑝 32.72 nV An analysis was performed to evaluate the effect of the drift. For this purpose, it was simulated in transient mode for 200 s (with short-circuited input signal). As described in 4.4.2, it has an exponential response until it reaches a value determined by the offset currents and voltages and the ratio of the connected resistors. The results at the output of each op-amp are depicted in Figure 4-13 according to the voltage reference of Figure 4-3. Taking into account the output of the two op-amps, which is very similar, it tends to a final value of 0.537 mV, starting from an initial voltage of -3.737 mV, with the time constant value as the period in which 63% of the final signal 𝜏= ~ 22 ms/V is reached. Figure 4-13 : Evolution of drift voltage: op-amp 1 (green), op-amp 2 (blue) and Output(red) The difference between the two integrated signals is described by the red line in Figure 4-13, which represents the voltage at the output of the operational amplifier in differential configuration. The differential voltage starts around 80 μV but tends to zero as the current flowing through each of the integrators decreases. This characteristic needs to be studied in more detail experimentally to evaluate the real impact of these currents and voltages. It is suggested that the system could evolve to steady state, and thus the reference could be taken as an offset and not as a drift. The value at the output of the complete circuit is 27.351 µV rms. This simulation does not consider the effects caused by the temperature rise of the components or the effect of their tolerances. 4.6 PCB circuit construction For the first prototype, a through-hole component design was proposed. This approach facilitates the redeployment and monitoring of all installed components. Elements that would not be replaced, such as the temperature sensor or the driver for the relays, were surface-mounted components. For the design of the printed circuit board, a simple free online programme known as EasyEDA was used. This programme has a large repository of elements and datasheet that are linked by an internal distributor. Basic design rules were used for the PCB design. The board consists of 4 layers, distributed in: signal, +12V, - 12V, and GND. For correct isolation, an individual DC/DC supply was used for each integrator board. This is a feasible solution to increase the galvanic isolation between the signals and the rest of the power supplies. Its dimensions are 100*80 mm, it has a width of 1.6 mm (±10 %), constructed with FR4-Standard Tg 130-140 material and with an Outer Copper Weight of 1 oz. These characteristics are based on economic criteria and imposed specifications, in accordance with the supplier standards (JLPC). For the assembly of the components, the following steps will be taken: • PCB cleaning: in this case, it was not necessary because the PCB supplied was vacuum packed and cleaned at the factory. It is always necessary to check the cleanliness of the solder area to facilitate the soldering process and allow the solder to distribute correctly. • SMD parts assembly: the smaller surface mount elements were assembled first (Figure 4-14). For this, the SMD stencil (Solder paste stencil) supplied by the PCB manufacturer was used to place the solder paste on each pad correctly. The solder used was Chipquik® smd291. All electronic components were placed and soldered with a heated air tool according to the soldering curves provided by the manufacturer. 6 CONCLUSIONS AND FUTURE WORK 6.1 Conclusions All the objectives of this document have been fulfilled successfully. A concise review of the current needs for SMART control has been made, as well as a general review of the state of the art of integration systems with main application in nuclear fusion. The requirements for the design of analogue integrators have been defined, and their theoretical behaviour has been evaluated by means of simple mathematical models. The evaluation of these models has allowed to obtain the values of some essential passive components for the circuit. Simulations of these values have been conducted in LTspice to evaluate if the requirements imposed are complied with. Similar curves to those in operation have been simulated and responded with an excellent level of integration, near-zero latency over the entire bandwidth. A noise analysis has been performed, and it is below the limits imposed by the specifications. The drift has been measured and is below the imposed levels. Therefore, it is concluded that the architecture presented, works according to the theoretical models and the simulations carried out, which has made it possible to have an integrator with the same characteristics as the bibliography presented but with greater simplicity and, therefore, a reduction in costs and latency than the existing integrators. 6.2 Future work The following tasks are defined as a continuation of the work described in this document. • The next steps are to connect the board in a real environment and to perform real drift and operation tests. It is expected to gain experience from these tests and thus improve future designs of greater complexity and train engineers in this field. • It is anticipated that embedded systems with a larger number of inputs and functions will be able to be developed, facilitating remote operation, calibration, and commissioning, as well as error detection and redundancy. • Further research is expected to bring together the necessary components to realise a real-time plasma monitoring system. New institutions see SMART as an opportunity in this field and are expected to develop these with possible collaborations. ANNEX A Test points on a PCB, or Printed Circuit Board, are strategic locations designed to facilitate verification and diagnosis of potential circuit problems. These points are often connected to critical power or signal sources to perform voltage, current or digital signal measurements during manufacturing, assembly, or maintenance. This appendix describes the points used and their location on the board. Test point Description Tp_Vint+ Input signal + Tp_Vint- Input signal - Tp_InOpam+ U1.1 Input Tp_OutOpam+ U1.2 output Tp_inOpam- U2.1 input Tp_OutOpam- U2.1 output Tp_Out U3.1 output Tp_5V Output signal + Tp_0V ext. 5V ref. Tp_Vcc ext. GND ref. Tp_-12 ext. 12V ref. Tp_GND PCB -12V Tp_+12 PCB GND Tp_+15 PCB +12V Tp_-15 PCB +15V Tp_Talt PCB -15V Tp_Tscl ext. ALT T. sensor Tp_Tsda ext. SCL T. sensor Tp_AREL1 ext. SDA T. sensor Tp_AREL1 ext. relay Annex A 48 48 ANNEX B Circuit model in LTspice ANNEX C PCB schematic References 58 58