Discontinuous PWM Operation of a Single-Phase PV Generator With Low-Voltage Energy Storage

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published by IEEE Transactions on Industrial Electronics available at: 10.1109/TIE.2024.3436625 “© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Discontinuous PWM Operation of a Single-Phase PV Generator with Low-Voltage Energy Storage Ezequiel Rodriguez, Member, IEEE, Ramon Leyva, Senior Member, IEEE, Qingxiang Liu, Student Member, IEEE, Glen Ghias Farivar, Senior Member, IEEE, Sergio Vazquez, Fellow, IEEE, Christopher D. Townsend, Member, IEEE, Hossein Dehghani Tafti, Senior Member, IEEE, and Josep Pou, Fellow, IEEE Abstract—Using energy storage in grid-connected photovoltaic (PV) generators is an efficient solution to deliver regulated power to the grid despite fluctuations in solar irradiance. The paper analyses a single-phase grid-connected PV generators with energy storage, where the energy storage has a low voltage, namely without too many series-connected storing cells. The PV generator consists of three subsystems connected by a common dc-link capacitor: a PV unit, an energy storage unit, and an inverter. Furthermore, in the proposed solution, the inverter does not switch for a significant portion of the grid period, resulting in lower switching losses. The single-phase inverter discontinuous operation implies the need of an appropriate control strategy in the boost dc-dc converter of the energy storage unit. The proposed control employs an augmented state model that accounts for resonant variables. The proposed PV solution with low-voltage energy storage, including its control, is validated in a 350-VA experimental prototype to verify the novel approach. I. INTRODUCTION Grid-connected photovoltaic (PV) generators can incorporate energy storage (ES) capability to address solar irradiance fluctuations and ensure grid code adherence [1]– [5]. A typical PV power plant with ES, as shown in Fig. 1, may consist of three subsystems connected by a common dc-link capacitor: (i) a PV unit that contains a solar array and a dc-dc converter acting as a maximum power point tracking (MPPT) regulator, (ii) an ES unit that contains a battery or a supercapacitor and a dc-dc converter working as an ES processor, and (iii) an inverter for grid power delivery. Optimizing the design of each of these subsystems and the overall system, specifically minimizing losses and cost, is of paramount importance for further expanding the deployment of PV generators. ES can be built with batteries, supercapacitors, or a combination of the two. Supercapacitors have advantages over batteries in PV applications because they have a higher power density and a lower equivalent series resistance. However, using a supercapacitor as an ES typically requires a low terminal voltage (less than 48 V). Even if an ES is built with batteries, due to charge equalization concerns, low-voltage battery design strategies could have advantatges in reliabiliy and safety terms [6], [7]. Low-voltage ES requires the ES processor to be a step-up topology. In grid-connected PV applications without ES, the inverter’s efficiency can be increased by using discontinuous modulation (DPWM) or unfolding strategies [8]–[14]. In both strategies, the inverter stops switching for a significant fraction of the Fig. 1: Block diagram of grid-connected PV power plant with ES. grid period. In the context of DPWM, the inverter switches at a high frequency for a portion of the grid period, and the dc-link voltage is not intentionally shaped [10], [11], [13]. On the other hand, in the unfolding strategy, the inverter switches at the grid frequency, and the dc-link voltage is deliberately shaped to a rectified sinusoidal form. The shaping of the dc-link capacitor voltage is carried out by injecting a specific capacitor current with the purpose of synthesising a desired dc-link capacitor voltage waveform [8], [9], [12], [14]. DPWM is usually reported for three-phase inverters, as in [13], whereas it is in an incipient stage for single-phase multilevel inverters [10], [11]. Concerning unfolding strategy methods, [8], [9], [12] report buck-boost unfolding strategies for gridconnected single-phase PV inverters without ES, whereas [14] proposes an unfolding strategy for a three-phase motor drive application. Specifically, reference [8] uses an interleavedboost stage cascaded with a buck stage to shape the dclink capacitor voltage at the input of the H-bridge inverter, reference [9] uses a Cuk converter, and [12] uses a twisted buck-boost approach. The approach proposed in this paper applies to single-phase PV generators with ES, combining the properties of DPWM and unfolding strategies. Specifically, it can be framed as DPWM, because the inverter does not switch for a significant portion of the grid period. Furthermore, it shares with unfolding strategies the feature that the dc-link capacitor voltage is shaped to a quasi-rectified sinusoidal shape. Fig. 2 depicts the voltage waveforms for the proposed voltage shaping approach and a conventional sinusoidal PWM (SPWM) in which the dc-link voltage is set to a constant value greater than the grid voltage peak. Note that the voltage variables in Fig. 2 are shown in Fig. 1, with the exception of vinv, which is an This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 2: Voltage waveforms on the ac-side vinv and on the dcside vCDC−link of the H-bridge inverter, when operating the gridconnected PV generator with the proposed voltage shaping approach and with a conventional sinusoidal PWM approach. internal voltage between the inverter H-bridge and the inverter filtering inductor. A cyan shaded area indicates the fraction of time within half a grid period in which the H-bridge inverter does not switch. The proposed strategy is inspired by [15]. Nevertheless, in [15], the ES processor is based on a buck converter, which is not suitable when the ES operates at low voltage. The main contribution of the paper is the introduction of a novel approach for shaping the dc-link capacitor voltage as a quasi-rectified sinusoidal form for PV generators with lowvoltage ES units, as well as the corresponding resonant-action- based control. In addition, the following can be considered secondary contributions: •To enhance the tracking of the rapidly changing quasirectified sinusoidal voltage reference, the proposed PV generator with low-voltage ES uses a very small dc-link capacitor, which could result in a smaller inverter size. •The proposed approach has been experimentally validated for a single H-bridge inverter, and it can be easily extended to a cascaded H-bridge topology. •An analytical model of switching losses in the H-bridge inverter is developed and experimentally verified to assess the benefits of the proposed voltage shaping strategy. The subsequent sections of the paper are organized as follows. In Section II, the system model of the grid-connected PV power plant with low-voltage ES in Fig. 1 is described, detailing each of the three subsystems. Section III presents the scaled-down experimental setup and some results. Finally, Section IV summarizes and concludes the paper’s main ideas. II. STATE-SPACE MODEL OF THE GRID-CONNECTED PV POWER PLANT WITH LOW-VOLTAGE ES Based on the system shown in Fig. 1, this section reviews the state-space model of each subsystem, i.e., the inverter, the PV unit, and the ES unit, in three subsections. Also, the proposed control laws are described. A. Inverter Model The inverter interfaces the dc-link capacitor voltage, vCDC−link , and the grid voltage, vg, as shown in Fig. 3. The Fig. 3: Circuit diagram of inverter stage. Fig. 4: Inverter resonant control law. single-phase inverter consists of four power semiconductors, which form an H-bridge structure with three possible output voltage levels, and a filtering inductor, Linv. The set of discontinuous switching positions {0, , 1}of each top switch, Sinv−A,Sinv−B, are controlled by a fixed carrier frequency pulsewidth modulation (PWM) circuit, and complementarity between top and bottom switches is assumed. The locallyaveraged dynamics of the inverter output current, iLinv , according to Fig. 3, is given by: Linv ˙ iLinv =−RLinv iLinv +δinvvCDC−link −vg,(1) where CDC−link is the dc-link capacitance and RLinv models the series resistance of the filtering inductor, Linv. Note that, as shown in Fig. 3, the locally-averaged H-bridge input current, ii inv, corresponds to ii inv =δinviLinv , where the modulation signal δinv represents the locally-averaged control input of the inverter over the PWM carrier period, Tc. Note that δinv ∈ [−1,1]. The locally-averaged inverter output current, iLinv , has to track a sinusoidal reference, i∗ Linv , to exchange a given active power, P∗ g, and reactive power, Q∗ g, with the grid, i∗ Linv (t) = √2P∗ g Vg cos (ωgt) + √2Q∗ g Vg sin (ωgt),(2) where ωgis the grid angular frequency, and Vgdenotes the grid voltage rms value. 2 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS A control strategy has to be implemented to ensure that iLinv tracks i∗ Linv . A feedback control law that takes into account resonant variables is considered [16]. Other harmonic errors, such as the third harmonic 3ωg, can be similarly considered. Also, the integral of the tracking error can be taken into account. Specifically, the applied resonant control strategy is shown in Fig. 4, where the control input δinv corresponds to, δinv =1 vCDC−link (vg+Kinvxinv),(3) with Kinv =Kinv1Kinv2··· Kinv6and xinv = ˜ iLinv xinv2··· xinv6T, and where ˜ iLinv =iLinv − i∗ Linv is the inverter output current tracking error, xinv2= Rt 0˜ iLinv (τ)dτ is the integral of the tracking error, and xinv3, xinv4,xinv5,xinv6are resonant variables. Specifically, ˙xinv3 ˙xinv4=0 1 −ω2 g−2ζrωg xinv3 xinv4+0 1˜ iLinv , (4) where ωgis the resonant frequency of system (4), and it coincides with the grid angular frequency, and ζris a positive damping factor near to zero [16]. The actual control implementation includes additional resonant variables xinv5,xinv6 to drive the steady-state error at three-times the angular grid frequency, i.e., 3ωg, to zero. Namely, ˙xinv5 ˙xinv6=0 1 −9ω2 g−6ζrωg xinv5 xinv6+0 1˜ iLinv . (5) Due to the desire to operate in discontinuous mode, the averaged control input δinv is saturated at 1or −1. Forcing |δinv|= 1 in (3), yields 1 = 1 vCDC−link |vg+Kinvxinv|.(6) Consequently, vCDC−link has to track the following reference, v∗ CDC−link =|vg+Kinvxinv|,(7) during the time that vCDC−link is being shaped, i.e., during the time the inverter does not switch. As will be explained below, the ES processor control is responsible to drive vCDC−link to the reference v∗ CDC−link . However, since the ES processor corresponds to a boost topology, the condition |δinv|= 1 can only be satisfied when the ES voltage, vES, is below the dc-link voltage, vCDC−link , thus (7) must correspond to, v∗ CDC−link = max {|vg+Kinvxinv|, vES},(8) over all the grid period. Note that in (8), when the max {} function takes the first parameter, the inverter is not switching, as shown in Fig. 2; whereas when the max {}function takes the second parameter, the inverter switches with a constant carrier period Tc. In summary, the inverter controller in Fig. 4 drives the grid current, iLinv , and also is in charge to indicate the reference signal v∗ CDC−link to the ES processor. In this solution, feedback gains Kinv1,Kinv2, ..., Kinv6are chosen via pole-placement technique. PV String MPPT Regulator + iLPV LPV Boost R LPV v CPV - C DC-link SPV C PV + v CDC-link - iPV + io PV ii inv io ES Fig. 5: Circuit diagram of PV unit. B. PV Unit Model A boost converter is used as the MPPT regulator, interfacing the PV array and the dc-link capacitor, as shown in Fig. 5. The boost converter consists of a capacitor CP V at the PV array terminals with voltage vCP V , an inductor LP V with current iLP V , and two power semiconductors. The bottom switch, SP V ∈ {0,1}, is controlled by a fixed carrier frequency PWM circuit. According to Fig. 5, the locally-averaged dynamics of the PV unit is given by: LP V ˙ iLP V =vCP V −RLP V iLP V −d′ P V vCDC−link ,(9) CP V ˙vCP V =iP V −iLP V ,(10) where RLP V models the parasitic resistance of the inductor LP V , and {vCP V , iP V }are the locally-averaged PV array voltage and current, respectively, with iP V =f(vCP V )a nonlinear mapping that models the PV array voltage-current relationship. Note that, as shown in Fig. 5, the locally-averaged PV unit output current, io P V , corresponds to io P V =d′ P V iLP V , where d′ P V stands for the complementary duty cycle of the switching signal SP V . The linearised model of the PV unit can be expressed as, "˙ ˜ iLP V ˙ ˜vCP V #="−RLP V LP V 1 LP V −1 CP V −mP V CP V #˜ iLP V ˜vCP V + vCDC−link LP V 0˜ dP V ,(11) where ˜vCP V =vCP V −V∗ CP V is the PV capacitor voltage regulation error, with V∗ CP V as the PV capacitor voltage reference, ˜ iLP V =iLP V −P∗ P V /V ∗ CP V is the inductor current regulation error, with P∗ P V as the PV power reference, ˜ dP V is the incremental duty cycle of the MPPT regulator, and mP V is the slope of the PV nonlinear mapping at the operating point, and corresponds to mP V =−∂f (vCP V )/∂vCP V |V∗ CP V . A control strategy has to be implemented to ensure that vCP V tracks V∗ CP V . The reference for the PV capacitor voltage V∗ CP V is provided by an MPPT [17], [18] (or flexible power point tracking [3], [19]) strategy. Namely, ˜ dP V in the proposed solution is chosen as, ˜ dP V =1 vCDC−link   KP V1 KP V2 KP V3   T  ˜ iLP V ˜vCP V xP V3  ,(12) 3 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS iLES LES Boost R LES C DC-link SES SES + v CDC-link - + ES Processor Energy Storage io ES io PV ii inv + v ES - Fig. 6: Circuit diagram of ES unit. where xP V3=Rt 0˜vCP V (τ)dτ is the integral of PV capacitor voltage regulation error. In this solution, feedback gains KP V1, KP V2,KP V3are chosen via pole-placement technique. Note that the MPPT regulator duty cycle expression corresponds to, dP V =1−V∗ CP V vCDC−link +˜ dP V .(13) Since the MPPT regulator is based on a boost topology, the condition V∗ CP V ≤vCDC−link has to be fulfilled for correct PV unit behaviour. Note that a boost topology has been chosen for simplicity, but other topologies, such as buck-boost, could have been considered. C. ES Unit Model A bidirectional boost converter is used as ES processor, interfacing the low-voltage ES and the dc-link capacitor, as shown in Fig. 6. The boost converter consists of an inductor LES with current iLES , and two power semiconductors. The bottom switch, SES ∈ {0,1}, acts as the subsystem control variable. According to Fig. 6, the locally-averaged dynamics of the ES unit is given by: LES ˙ iLES =vES −RLES iLES −d′ ESvCDC−link ,(14) CDC−link ˙vCDC−link =d′ ESiLES +io P V −ii inv,(15) where RLES models the parasitic resistance of the inductor LES,vES is the ES voltage, and d′ ES stands for the complementary duty cycle of the switching signal SES. Note that, as mentioned, locally-averaged current variables io P V and ii inv in (15), correspond to io P V =d′ P V iLP V and ii inv =δinviLinv , respectively. The nonlinear averaged dynamics of the ES unit subsystem are linearised around the reference trajectory v∗ CDC−link , according to (8), with reference values i∗ LES and d′∗ ES coherent with (14) and (15), resulting in, "˙ ˜ iLES ˙ ˜vCDC−link #="−RLES LES −d′∗ ES LES d′∗ ES CDC−link 0#˜ iLES ˜vCDC−link +   v∗ CDC−link LES −i∗ LES CDC−link  ˜ dES,(16) where ˜ iLES =iLES −i∗ LES represents the inductor current error in the ES processor, ˜vCDC−link =vCDC−link −v∗ CDC−link denotes the dc-link capacitor voltage tracking error, and ˜ dES stands for the incremental duty cycle of the ES processor. Note that a coherent reference value for i∗ LES corresponds to i∗ LES =1 d′∗ ES CDC−link ˙v∗ CDC−link −io P V +ii inv,(17) where d′∗ ES =vES/v∗ CDC−link . Note that including the terms io P V and ii inv feedforwards changes in the PV current and the grid current, respectively. Besides, the derivative term ˙v∗ CDC−link is calculated by means of the quadrature component of v∗ CDC−link when the inverter is not switching, while it is zero when the inverter is switching. These feedforward terms improve the transient behaviour, and consequently, the error integral terms in the controller have smaller excursions. Next, control state variables, including error integral terms, are explained. The reference v∗ CDC−link , according to (8), has an important component at twice the fundamental frequency, thus the control should take into account resonant variables in a similar way as it is described in the inverter control. Specifically, a state-feedback controller that considers the resonant variables and has the form ˜ dES =KESxES, with KES ∈R7, is considered, being xES, xES =˜ iLES ,˜vCDC−link , xES3, xES4,··· , xES7T.(18) Fig. 7 shows the proposed state-feedback control law for the ES processor. State variables {xES3, xES4, xES5}, defined in (19) and (20), ensure zero steady-state error in the dc component of ˜vCDC−link , and zero steady-state error in the twicefundamental-frequency component of ˜vCDC−link , ˙xES3= ˜vCDC−link ,(19) ˙xES4 ˙xES5=0 1 −4ω2 g−4ζrωg xES4 xES5+ 0 1˜vCDC−link ,(20) where 2ωgis the resonant frequency of system (20). Note that other additional resonant variables could be added to consider multiples of twice the angular grid frequency. In fact, in the experimental prototype, resonant variables to impose zero steady-state error in the four-times-fundamental- frequency component of ˜vCDC−link , i.e., at 4ωg, have been considered. It is also important to note that the ES processor must follow a fast current reference i∗ LES , according to (17), which implies that the inductor LES must be small enough, and consequently the current ripple is nonnegligible. Furthermore, increasing the switching frequency may not always be technically appropriate. State variables {xES6, xES7}, defined in (21), observe high-frequency components in ˜ dES and can be 4 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Energy Storage Unit Control with Resonant Action + v CDC-link ~ * + iLES iLES iLES ~ * v CDC-link v CDC-link 2(2ωg) + s 1 2 ζr s + (2ωg) 2 s 2(2ωg) + s 2 ζr s + (2ωg) 2 KES3 KES4 KES5 KES2 xES4 xES5 + + + + + + KES1 s 1 xES3 + KES6 KES7 xES6 xES7 dES ~ vES * v CDC-link + + 1 + + dES dES ' * + s 1 2 2 ωc 2ωc s + + s 2 2 ωc 2ωc s + s Fig. 7: Proposed resonant state-feedback control law for the ES processor. added to the system model and fed back for limiting highfrequency components in the control signal ˜ dES, ˙xES6 ˙xES7=0 1 −ω2 c−2ωc xES6 xES7+0 1˜ dES, (21) where ωc= 2π/Tc(Tcis the fixed PWM carrier period). The control feedback gains KES can be determined using the pole-placement technique, similar to the inverter and PV unit. Nevertheless, given that in the ES processor dynamics (16), most of the coefficients can have a nonnegligible uncertainty, the determination of the control feedback gains has been carried out using a linear matrix inequalities (LMIs) strategy [20]–[22] that treats the uncertainty in a polytopic manner [23], [24]. Specifically, the uncertain parameters considered are nv∗ CDC−link , i∗ LES , d′∗ ESo, i.e., v∗ CDC−link ∈vES,√2Vg, d′∗ ES ∈vES/√2Vg,1, and i∗ LES ∈−Imax LES , Imax LES , being Imax LES a prescribed maximum value for the energystorage processor current. Thus, the uncertainty polytope has dimension three, viz., it is an hiperectangle with eight vertices. Also, the LMI strategy is able to incorporate constraints to limit the switching ripple propagation, as reported in [22]. Note that the choice of the desired location of the poles in the pole-placement technique can be made in an iterative manner. Also, the region where the poles are to be located in the LMI technique could require a few iterations. III. EXPERIMENTAL RESULTS With the purpose of illustrating the performance of the proposed resonant-action control law for a discontinuouslyoperated grid-connected PV generator with low-voltage ES, experimental results are obtained on a scaled-down laboratory prototype that is shown in Fig. 8. In the prototype, the grid voltage is provided by an ITECH IT7900-series power supply, B-Box Controller Grid Simulator DC-DC Converters Fig. 8: Experimental setup. TABLE I: PARAMETERS OF THE EXPERIMENTAL SETUP Parameter Value Nominal grid voltage, Vg80 V Grid angular frequency, ωg100πrad/s Inverter stage inductance, Linv 5mH ES voltage, VES 48 V DC-link capacitance, CDC−link 60 µF ES processor inductance, LES 333 µH PV maximum power (standard test conditions) 344 W PV maximum power point voltage (standard test conditions) 80 V MPPT regulator inductance, LP V 200 µH PV-side capacitance, CP V 200 µF PWM carrier frequency, fc20 kHz and the low-voltage ES is emulated by a GE&EL 15 kVA CINERGIA working as a bi-directional dc power supply. IMPERIX PEH2015 H-bridge modules are used to implement the three converters, i.e., the inverter, the MPPT regulator, and the ES processor. Parameters of the scaled-down prototype are shown in Table I. It can be appreciated that the size of the dc-link capacitor, CDC−link, and the inductance of the ES processor, LES, are small, thus allowing a fast dynamic. The proposed control schemes depicted in Fig. 4 and Fig. 7 are implemented using a B-Box RCP board from IMPERIX. The B-Box RCP has a dual-core DSP (2x ARM Cortex A9 1GHz, 1GB DDR3), in which the proposed controller is implemented with 60 kHz sampling. Specifically, the duty cycles are generated at a sample rate of 60 kHz for the PV unit, the ES unit, and the inverter. The PWM is implemented in a Kintex-grade FPGA (Xilinx Kintex 7 125K) with a time resolution of 4ns, using a 20-kHz 32-bit triangular carrier. Voltage and current magnitudes depicted in the following figures have been captured using a YOKOGAWA DLM4038 oscilloscope. In the proposed control law for the inverter (3), depicted in Fig. 4, the feedback gains have been chosen such that the closed-loop transfer function has three pairs of two complexconjugate poles at −ζiωn,i ±jωn,ip1−ζ2 i, with ωn,i = 4/(ζiTset,i), where Tset,i and ζiare the desired settling time and damping coefficient of the ith pair (i∈ {1,2,3}), respectively. Specifically, Tset,1= 7.5ms, Tset,2= 10 ms, Tset,3= 12.5ms, and ζi=√2/2,∀i. Particularly, the inverter 5 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 9: Transient experimental waveforms of a sudden irradiance increase where the PV array power changes from 275 W to 400 W. On the left side, the conventional sinusoidal PWM with v∗ CDC−link = 135 V. On the right side, the proposed voltage shaping approach. Both control strategies operating at P∗ g= 480/√2W and Q∗ g= 0. Upper plots: PWM inverter voltage, vinv, dc-link capacitor voltage, vCDC−link , and the 48-V ES voltage, vES ; Middle plots: grid voltage, vg, and grid current, iLinv ; Bottom plots: ES current, iLES . feedback gains are, Kinv =−12.3321,−2259.2129,−542454.2395, −2365.4614,1265767.9895,−6257.4191 .(22) Regarding the PV unit, the feedback gains of control law (12) have been chosen such that the closed-loop transfer function has a simple pole at −4/Tset, and a pair of two complex-conjugate poles at −ζωn±jωnp1−ζ2, with ωn= 4/(ζTset),Tset = 0.8ms, and ζ=√2/2. Particularly, the PV unit feedback gains are KP V1= 2.9937,KP V2=−3.0220, KP V3=−10204.0816. The proposed control for the ES processor considers not only the resonant variables at twice the fundamental frequency (2ωg) in the capacitor voltage tracking error ˜vCDC−link , as in (20), but also resonant variables at 4ωg. Therefore, the state feedback gain KES is augmented with two additional gains. We refer to the augmented state feedback gain as Ka ES in the experimental description. Using the parameters from Table I, setting the prescribed maximum value for the ES processor current as Imax LES = 8 A, the following feedback gain Ka ES is obtained using an LMI approach [24], Ka ES =−0.0150,−0.0062,−1.8672,74.9488, −4.1879,13671111904.9396,173006.0733, −3794.8340,−6.4543 .(23) Next, the paper discusses the experimental results obtained when the PV array power is providing 275 W and the inverter is delivering an active power Pg= 480/√2W, as well as the effects of a sudden change in the PV array power. The proposed approach also allows for the exchange of a specific amount of reactive power. The harmonic content of gridside signals, and switching losses of the converters, are also discussed, for both the proposed voltage shaping strategy and a conventional SPWM strategy. In both strategy cases, the feedback control gains used, shown in (22) and (23), and the dc-link capacitance, CDC−link = 60 µF, are the same. 6 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 10: Harmonic spectra of waveforms when the PV array power is 275 W. (a) Grid current, iLinv , spectrum for conventional PWM. (b) Grid current, iLinv , spectrum for the proposed voltage shaping approach. (c) PWM inverter voltage, vinv , spectrum for conventional PWM. (d) PWM inverter voltage, vinv, for the proposed voltage shaping approach. Fig. 9 shows the experimental waveforms in the ES unit and the inverter when the PV array power is providing 275 W and suddenly changes to 400 W at t= 0.1s. In this specific experiment, the inverter is providing a current iLinv (t) = 6 cos (ωt) to a grid voltage vg(t) = 80√2 cos (ωt). The left-column plots of Fig. 9, i.e., Fig. 9(a), Fig. 9(c) and Fig. 9(e), show the behaviour when the dc-link capacitor voltage is controlled to v∗ CDC−link = 135 V, whereas the right-column plots of Fig. 9, i.e., Fig. 9(b), Fig. 9(d) and Fig. 9(f), correspond to the case when the dc-link capacitor voltage is shaped according to (8), with vg(t) = 80√2 cos (ωt)and vES = 48 V. It can be observed that, in both cases, the transient in ES unit and inverter waveforms is very fast, in terms of the grid period. It is worth noting that the dc-link voltage, vCDC−link , in Fig. 9(b), is accurately shaped to the desired quasi-rectified sinusoidal shape, v∗ CDC−link , which corroborates that the proposed resonant structure works as expected. The shaped quality of vCDC−link allows an almost perfect discontinuous operation in the inverter, which can be corroborated by the reduction of the number of switching events over a grid period in the PWM inverter voltage, vinv, despite the fact that the inverter has its own controller. In Fig. 9(c) and Fig. 9(d), it can be observed that the grid current, iLinv , and grid voltage, vg, exhibit an excellent sinusoidal shape and the transient is almost imperceptible. This means that the controller of the ES processor completely rejects disturbances coming from the PV unit, as well as allows the desired discontinuous operation. This rejection of disturbances is obtained thanks to the ES current reference used, i.e. i∗ LES in (17), which includes feedforward terms. Also, it is worth noting that the ES current, iLES , for both cases, shown in Fig. 9(e) and Fig. 9(f), present approximately the same peak-to-peak range, and the transient at t= 0.1s is fast. In Fig. 9(d), it can be observed that the grid current, iLinv , tracks accurately its sinusoidal reference despite the discontinuous operation. The harmonic spectra of the grid current, iLinv , is depicted in Fig. 10(a) and Fig. 10(b), for the conventional SPWM and the proposed voltage shaping strategy, respectively. The obtained total harmonic distortion (THD) (calculated considering up to 50th harmonic order, and the steady-state condition corresponding to the first half of Fig. 9) is reported in the corresponding figures. It can be observed that the proposed strategy reduces the even harmonics in the current compared to the conventional approach. Notably, the second harmonic is reduced from 0.3% in the conventional approach to 0.1% with the proposed approach. Moreover, the fourth harmonic experiences a notable reduction from 0.2% to nearly 0%, and the sixth harmonic similarly decreases from 0.1% to nearly 0% when employing the proposed voltage shaping strategy. The bottom plots of Fig. 10, i.e., Fig. 10(c) and Fig. 10(d), show the corresponding harmonic spectra of the PWM inverter voltage, vinv, for the conventional SPWM and the proposed voltage shaping strategy, respectively. In this case, the THD has been calculated across the entire frequency range. As can be seen, the proposed strategy significantly reduces PWM inverter voltage THD from 64.65% to 13.99%, facilitating the filtering action or, equivalently, allowing the use of smaller filtering inductors. It is important to note that with the proposed approach, the inverter only switches for about one-third of the fundamental period, for the experimental parameters given in Table I, as shown in Fig. 9(b), which stands in contrast with the conventional SPWM that switches over all the grid period, as shown in Fig. 9(a). Moreover, in the proposed approach, the inverter switches when the grid current is close to zero. This means that the inverter switching losses are significantly reduced (analysis is reported in the Appendix section). For the experimental parameters from Table I, and using (32), results in a 95% reduction in the inverter switching losses. With regard to the losses in the ES processor, it is worth 7 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 11: Averaged switching losses over a grid period when the PV array power is 275 W. Red represents the conventional sinusoidal PWM strategy, while blue represents the proposed voltage shaping strategy. mentioning that, as shown in Fig. 9(e) and Fig. 9(f), both strategies have similar shapes and RMS values of ES current, iLES . Furthermore, the switch blocking voltage of the ES processor, i.e., vCDC−link , is reduced in the proposed strategy. This means that adopting the proposed strategy does not decrease the efficiency of the ES processor, but it increases it. For the same reason, the efficiency of the MPPT regulator does not change significantly. Specifically, for the prototype shown in Fig. 8 and parameters from Table I, the loss reduction has been corroborated using the recorded experimental data corresponding to the steady-state condition of the first half of Fig. 9, i.e., when the PV array power is 275 W. Fig. 11 depicts the obtained switching losses values normalised with respect to the total switching losses in the conventional SPWM strategy. The reduction in switching losses in the inverter is 95%, which is consistent with the expected value according to the Appendix analysis. Additionally, the switching losses in the ES processor and MPPT regulator have been reduced by 18% and 38%, respectively. This reduction is due to the fact that the blocking voltage of the dc-dc converter switches corresponds to the quasi-sinusoidally rectified dc-link capacitor voltage in (8) when adopting the proposed strategy. The instantaneous switching losses, which are proportional to the blocking voltage at the switching instant [25], are lower with the proposed approach compared to using a fixed voltage with a conventional strategy, as shown in Fig. 12. Furthermore, from measurements of the battery voltage and current, PV array voltage and current, and grid voltage and current, it can be stated that the proposed voltage shaping strategy reduces the overall losses, which includes conduction losses, by 45%. This reduction in overall losses, as well as the THD results, justify the proposed resonant control technique used in the ES processor, which allows for voltage shaping of the dc-link capacitor. As a final feature of the proposed approach, it is worth mentioning that the proposed PV generator can manage the exchange of reactive power with the grid, according to (2). Fig. 13 shows the waveforms of the PV generator when it is exchanging P∗ g=−320/√2W and Q∗ g=−320/√2var with the grid. It can be observed that the proposed strategy is able to shape the dc-link capacitor voltage as desired such that the Fig. 12: Simulated switch blocking voltage in the ES processor boost converter (bottom switch) when operating the grid-connected PV generator with a conventional sinusoidal PWM approach and with the proposed voltage shaping approach. Fig. 13: Experimental waveforms when operating at P∗ g= −320/√2W and Q∗ g=−320/√2var. Channel CH1 (yellow) shows the PWM inverter voltage, vinv, Channel CH2 (green) shows the grid voltage, vg, Channel CH3 (magenta) shows the 48-V ES voltage, vES , Channel CH4 (cian) shows the dc-link capacitor voltage, vCDC−link , Channel CH5 (red) shows the ES current, iLES , and Channel CH6 (orange) shows the grid current, iLinv . inverter does not switch for a significant portion of the grid period. IV. CONCLUSION The paper has proposed a novel control of a grid-connected PV generator with low-voltage ES that reduces the switching losses. The PV generator consists of three subsystems connected by a common dc-link capacitor: a PV unit, an ES unit, and an inverter. The inverter is operated in discontinuous mode, which implies that the common dc-link capacitor voltage is shaped to a quasi-rectified sinusoidal shape. The controller for the ES unit that shapes the dc-link capacitor voltage uses integral and resonant variables. It ensures zero steadystate error at dc and at twice and four times the grid frequency. Experimental results corroborate an excellent behaviour of the overall system design, which yields a 95% saving in averaged switching losses in the inverter while reducing PWM inverter voltage THD from 64.65% to 13.99%, facilitating the filtering action. The proposed PV generator can exchange both active and reactive power with the grid. Experimental results show fast transitions for changing irradiance conditions. 8 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3436625 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.