A tunable floating-gate CMOS transconductor based on current multiplication

A Tunable Floating-Gate CMOS Transconductor Based on Current Multiplication José M. Algueta Miguel # , Antonio J. López Martín # , Jaime Ramírez Angulo † , Ramón González Carvajal * # Department of Electrical and Electronic Engineering, Public University of Navarra Campus Arrosadia, Pamplona E-31006, Spain 1 [email protected] 2 [email protected] † Klipsch School of Electrical and Computer Engineering, New Mexico State University Las Cruces, New Mexico 88003-0001 (USA) 3 [email protected] * Department of Electronic Engineering Department, University of Seville, Spain 4 carvaj[email protected].us.es Abstract - In this paper a novel transconductor based on floating gate techniques that performs current multiplication for tuning is presented. The multiplication is achieved using transistors operating in weak and moderate inversion together with floating voltage sources implemented conveniently by floating capacitors. Besides, a tuning scheme is proposed to set the transconductance parameter accurately. The resulting circuit features compactness, low voltage operation, and rail-to-rail input range. Measurement and simulation results using a 0.5um CMOS technology are presented to confirm all the circuits and strategies proposed. Index Terms—OTA, Floating gates, CCII-R, Low voltage I. I NTRODUCTION PERATIONAL Transconductance Amplifiers (OTAs) are versatile analog building blocks featuring high bandwidth and tunability that can find application in many fields. However, the linearity and input voltage are relatively poor. Some attempts have been proposed in order to improve the linearity of OTAs, such as adaptive biasing or nonlinearity cancellation, but they often require generating extra currents increasing the area and power consumption, and/or rely on the MOS square law which is unrealistic in modern processes [1]. Another alternative is to use Current Conveyors (CCII) [2] and a passive resistor for forming the OTA obtaining very low distortion, but continuous tuning of the resistor is not possible and the input range can also be limited. To overcome these drawbacks in this paper floating-gate techniques together with CCIIs and passive resistors are introduced for providing tunability, low voltage operation, and rail-to-rail input range. Tunability is achieved using a current multiplication cell based on a floating-gate current mirror operating in weak or moderate inversion. The paper is organized as follows. Section II provides a quick review of floating gate transistors and a solution based on a layout technique for avoiding the initial trapped charge. Section III presents the general block diagram of our proposal and a compact implementation at transistor level allowing a rail-to-rail input and tunability of the OTA. A transconductance tuning scheme is mentioned in Section IV. Measurement and simulation results from a fabricated prototype using a 0.5um CMOS technology are presented in Section V validating all the techniques and ideas proposed in this paper. Finally some conclusions are drawn in Section VI. II. A B RIEF I NTRODUCTION TO THE F LOATING -G ATE T RANSISTORS The equivalent circuit of a floating-gate transistor (FGT) [3] is shown in Fig. 1. The gate voltage is set though the n input terminals that are capacitively coupled to the floating gate. Assuming that input capacitors are much larger than the parasitic capacitances of the transistor, the gate voltage can be expressed as nnFG VaVaVaV ⋅ + + ⋅ + ⋅ = ... 2211 (1) where ∑ = ≈ n ii k k C C a 1 (2) Hence a weighted averaging of the input voltages is achieved in a compact way. Here, it has been supposed that trapped charge at the gate is zero, which can be enforced during manufacturing process (hence not requiring post-fabrication removal of such charge) using the technique reported in [4]. III. T UNABLE T RANSCONDUCTOR BASED ON FGMOS C URRENT M IRRORS The tunable transconductor presented is shown in Fig. 2. Both input and output are differential, and the circuit is composed of two current conveyors. The CCIIs have been O V 1 C 1 C 2 C n V 2 V n C GD C GS V D V S V B C GB V FG Fig. 1. Equivalent circuit of a n-input floating gate transistor. built using voltage followers and current mirrors that can scale the buffer output current by a factor K. Input signal is scaled by the factor “a” using techniques based on floating-gate transistors (FGT) in order to allow rail-to-rail input range. The element which performs the V-I conversion is a passive resistor placed between the CCIIs. In Fig. 2(a) this resistance R is represented by two R/2 resistors, so that we can sense the common mode voltage of the driving stage easily. From Fig. 2(a) it can be shown that i R is given by R VVa i inin R )( −+ − = (3) where a is the attenuation factor that multiplies the input signal in order to allow rail-to-rail operation. The differential output current is 2Ki R , so the transconductance parameter can be expressed as R Ka V i G in d out d m 2 == (4) The proposed schematic of tunable transconductor using the scheme of Fig. 2(a) is shown in Fig. 2(b), where the voltage follower is performed by transistors M 1N (M 2N ), M 7P (M 8P ), M 3P (M 4P ) and currents 2I B [5] respectively. In this scheme, assuming for the moment V F1 =V F2 , the resistor current can be easily mirrored using transistors M 1P (M 2P ) to the highimpedance output terminal. A. Gm Tuning by FGMOS Programmable Current Mirrors. In Fig. 2(b), the current mirror formed by M 3P -M 1P (M 4P - M 2P ) uses floating gates to achieve current multiplication [6] that is continuously programmed by voltages V F1 and V F2 . This linear K factor is possible when the transistors that form the current mirror are operating in weak or moderate inversion [7]. Thus high aspect ratios were selected for these FGTs to make them operate in weak or moderate inversion, in order to achieve a dependence as linear as possible between control voltages and current gain and to minimize distortion [7]. A more detailed analysis of the inversion level of transistors M 1P (M 2P ) and M 3P (M 4P ) is done in Section V. B. Input Range Increase. Note from Fig. 2(b) that, using conventional current mirrors, drain voltage of transistor M 1N would be V DD -V SG3P , so the upper limit of the range over which V in + can swing keeping M 1N in saturation would be very limited when low supply voltages are used. The same problem would occur with M 2N and V in -. However, if FGMOS mirrors are used, drain voltages of M 1N and M 2N can be adjusted by varying the common mode voltage of V F1 and V F2 . Specifically, when V F1 =V F2 =V FCM these two voltages can be expressed as CMFPGND V b b V b V− + − = 1 1 1 31 (5) and CMFPGND V b b V b V− + − = 1 1 1 42 (6) where b is a constant ( 0 < b < 1 ) determined by the ratio between the capacitors of the floating-gates. Therefore, the signals at the drains of M 1N and M 2N are V G3P and V G4P respectively, expanded by 1/(1-b) and dc shifted by [b/(1-b)]V FCM , so that V FCM must be set properly in order to increase the input range without affecting the operation of the upper current sources. In turn, transistors M 1N and M 2N have been replaced by a couple of two-input FGMOS transistors. One of the inputs is set to V DD , and input signal (V in + and V in - in each case) is applied to the other terminal. A detailed view of M 1N is shown in Fig. 3(a). The gate voltage V G1N is given by + + + + = inDDNG V CC C V CC C V 21 2 21 1 1 (7) so it is an attenuated and up-shifted version of V in +, allowing rail-to-rail input signals as shown in Fig.3 [3]. Note from (7) that when V in +=V DD then V G1N =V DD . However, when V in +=V SS , the value of V G1N depends on the relation between the capacitors C 1 and C 2 . In order to get rail-to-rail operation, C 1 and C 2 have to be chosen properly, so that when V in +=V SS , V G1N (and therefore V S1N ) is high enough to allow bottom current sources to work correctly. This idea is represented in Fig. 3(b). Note that factor a that appears in (3) and (4) is given R/2 Voltage Follower Current Follower x K x a V in + Y X Z CCII 1 i R i R K i R V ’CM R/2 Voltage Follower Current Follower x K V in - Y X Z CCII 2 i R i R K i R x a (a) VP R i OUT 1 M1N 2I B I B V in + VF1 VF2 M1P M3P M2N 2I B V in - M4P i R I B +i R K(I B +i R )K(I B -i R ) M7P M8P VP M5P VP I B I B I B -i R VP I B VF1 i OUT 2 M2P M6P VF2 (b) Fig. 2. Tunable transconductor based on FGMOS current mirrors. (a) Diagram (b) Schematic. V DD V DD V SS V FG MIN Vin+V G1 (a) (b) M 1N C 1 C 2 Vin+ V G1 V DD Fig. 3. Input FGMOS transistor. (a) Schematic (b) Scheme of rail-to-rail signal compression. by a=C 2 /(C 1 +C 2 ). In the other half of the circuit the situation is similar. IV. T RANSCONDUCTANCE T UNING One of main drawback of the programmable current mirrors is the fact that the value of V F1 and V F2 should be set precisely in order to guarantee that transistors are operating in weak or moderate inversion. Thus it could be desirable to set the transconductance parameter externally using know currents and/or voltages. Also this approach allows compensation for fabrication tolerances of resistors. Tuning has been achieved using a replica circuit. In our case only one half of the circuit has been replicated because it is completely symmetrical. For this reason the replica circuit, which is shown in Fig. 4, has been named Gm1/2. The voltage V’ CM is sensed from the central point of R in the transconductor of Fig. 2(b) (between two R/2 resistors placed in series). This voltage V’ CM is copied to the negative input of the amplifier, so half of the transconductor is simulated. A simple one-stage differential amplifier has been used, because a more complex topology is not required to operate as voltage follower. C C is a compensation capacitor. The output current of Gm1/2 circuit is given by )( )( 2/ CMinbiasmB CMinINBOUT VVGKI Vv R Ka KIi −+= −+= (8) where V CMin is the common mode input voltage. Hence, if transconductor of Fig. 2(b) and the control block share V F1 and V F2 , the transconductance Gm will be controlled by V BIAS and I TUN . The whole system is shown in Fig. 5. V F1 has been set externally, so the only adaptive parameter is V F2 , which has been connected to the output terminal of the control block. Under these conditions, the current gain K of the programmable current mirrors will be given by )( 2/ CMinBIASB TUN VV R a I I K −+ = (9) V. M EASUREMENT AND S IMULATION R ESULTS The transconductor of Fig. 2(b) was fabricated in a 0.5µm CMOS technology, with nominal nMOS and pMOS threshold voltages of 0.78V and -0.94V, respectively. A microphotograph is shown in Fig. 6. The resistance R of 40KΩ was made of nonsilicided polysilicon. A supply voltage of ±1.65V and a bias current I B of 50µA were applied. The current sources were implemented with cascode sources. Cascode transistors are biased with dc voltages V n =0.1V (for nMOS) and V p =0.2V (for pMOS). V p is the same for the cascode transistors of programmable current mirrors, which have been introduced in order to increase the output resistance. Aspect ratios (in µm/µm) of the transistors of the current sources were (30/1.05) in the case of nMOS and (199.95/1.05) for pMOS. The ratio W/L is twice for the nMOS transistors which have to provide a current of 2I B . The input transistors M 1N and M 2N have W=30µm and L=1.05µm. Finally, in order to achieve weak or moderate inversion, an aspect ratio of (250.05µm/0.90µm) was chosen for the transistors of the programmable current mirrors (M 1P ,..., M 8P ). V F1 and V F2 common mode voltage was 0.5V. The two FGMOS input capacitances of the current mirrors were identical (1 pF). In the differential input pair, a capacitance of 1 pF was associated to input signal (V in + and V in -) and V DD input is applied to a capacitance of 1.5 pF. Hence, the attenuation factor a is 0.4, so the maximum current across R will be 0.4(3.3/40.10 3 )=33µA. Therefore, the input currents of the mirrors swings between 17µA (I B -i Rmax ) and 83µA (I B +i Rmax ). The characteristic current for the pMOS V P R/2 i OUT M 1 N Vbias _ + A CC M 3 N V F1 V F2 M2 P VCM 2I B I B I B M 1P ' M 7P V P M 5P Fig.4. Transconductance control circuit (Gm1/2 block). Gm 1/2 V BIAS V CMin Gm V in + V in - + - V F1 1K 1K V CMin I TUN VF1 VF2 VF1 VF2 Fig. 5. Transconductance control system. Fig.6. Transconductor microphotograph. transistors of the programmable mirrors is I S =2K p (W/L)nU T2 ≈15.5µA. The inversion factor I d /I S is employed to define the MOS inversion level. Weak inversion corresponds to I d /I S <<1, strong inversion to I d /I S >>1 and moderate inversion to intermediate values (typically 1< I d /I S <10). In our case 17µA<I d <83µA. Thus, the inversion factor ranges in 1<I d /I S <5.3, so the transistors operate in moderate inversion. Fig. 7 shows the I od -V id dc response for five different V F1 -V F2 values, and harmonic distortion measured at 100KHz is shown in Fig.8. Second-order distortion is quite high due to the experimental setup (made by off-chip Op-Amps and resistors), as HD3 should be dominant in a fully differential circuit like this, and in fact it is dominant in simulation. Fig. 9 shows harmonic distortion for several values of V F1 -V F2 . Note that distortion has a minimum when current mirrors have unity gain (V F1 -V F2 =0) and increase with |V F1 -V F2 |, although this increment stops around |V F1 - V F2 |=100mV. Finally, the system of Fig. 5 has been simulated for K values from 0.5 to 2. Aspect ratio for M 3N is (120µm/1.05µm), and Cc is 3pF. Results are shown in Table I. Note that the achieved K is similar to its theoretical value (error≈8% in the worst result of the table), and harmonic distortion increases as we move away from K=1. However, the minimum distortion is situated at a value of K slightly less than 1. Also, note that linearity deteriorates faster for K>1 (amplification) than for K<1 (attenuation). In general, amplification affects linearity more than attenuation, as the output transistors are closer to strong inversion in this case. VI. C ONCLUSION In this paper a novel tunable transconductor has been proposed. The structure is based on CCIIs and programmable current mirrors using floating gate transistors operating in weak or moderate inversion. In order to set the transconductance accurately a replica bias dc tuning has been proposed. Measurement results from a fabricated CMOS prototype have been shown for demonstrating the viability of the cells and techniques proposed in the paper. R EFERENCES [1] E. Sanchez-Sinencio and J. Silva-Martinez, “CMOS transconductance amplifiers, architectures and active filters: a tutorial”, IEE Proc. Circ. Dev. Syst., vol. 147, pp. 3-12, Feb. 2000. [2] A. Sedra and K. Smith, “A second-generation current conveyor and its applications,” IEEE Tran. Circ. Theory, vol. CT-17, pp. 132-134, Feb. 1970. [3] J. Ramirez-Angulo, S.C. Choi and G. Gonzalez-Altamirano, “Lowvoltage circuits building blocks using multiple-input floating-gate transistors,” IEEE Trans. Circ. Syst. I, vol. 42, pp. 971-974, Nov. 1995. [4] E. O. Rodríguez-Villegas and H. Barnes, “Solution to trapped charge in FGMOS transistors,” Electron. Lett., vol. 39, pp. 1416-1417, Sep. 2003. [5] T. Lakshmi Viswanathan, “CMOS Transconductance Element,” Proceeding of the IEEE, vol. 74, no. 1, pp. 222-224, Jan. 1986. [6] E. Özalevli and P.E. Hasler, “Programmable flotating-gate CMOS resistors”, in Proc. IEE Int. Symp. Circuits Syst., 2005, vol. 3, pp. 2168- 2171. [7] A. J. Lopez-Martin, J. Ramirez-Angulo, R. G. Carvajal, and L. Acosta “CMOS transconductors with continuous tuning using FGMOS balanced output current scaling,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1313-1323, May 2008. Fig.7. Measured DC response of the transconductor. Fig. 8. Measured harmonic distortion at 100KHz with V F1 -V F2 =0. Fig. 9. Harmonic distortion measured for several values of V F1 -V F2 TABLE I S IMULATION R ESULTS O F T RANSCONDUCTANCE C ONTROL S YSTEM Theoretical K value THD (dB) (≈HD3) Real K (simulation value) K=0.5 (I TUN =30µA) -62 0.546 K=0.75 (I TUN =45µA) -71 0.795 K=1 (I TUN =60µA) -63 1.036 K=1.5 (I TUN =90µA) -53 1,5 K=2 (I TUN =120µA) -50 1,943