A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors

electronics Article A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors J. del Pino 1,† , Sunil L. Khemchandani 1,*,†, D. Galante-Sempere 1,† and C. Luján-Martínez 2,† 1Departamento de Ingeniería Electrónica y Automática, Institute for Applied Microelectronics (IUMA), Universidad de Las Palmas de Gran Canaria, E-35017 Las Palmas de Gran Canaria, Spain; [email protected] (J.d.P.); [email protected] (D.G.-S.) 2Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, E-41092 Las Palmas de Gran Canaria, Spain; [email protected] *Correspondence: [email protected] † These authors contributed equally to this work. Received: 9 September 2020; Accepted: 29 September 2020; Published: 30 September 2020   Abstract: This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 µ m process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 µ m 2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ± 1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands. Keywords: radio frequency variable gain amplifier (RF-VGA); wideband amplifier; broadband amplifier; second-generation controlled current conveyor (CCCII); BiCMOS; ISM; MICS; SDR 1. Introduction In radio frequency integrated circuits, the design of wideband amplifiers has been intensively discussed over the past few decades [ 1 ]. The most widely used wideband amplifier architecture is the distributed amplifier, which requires high power consumption and a large area due to the considerable number of stages and the extensive use of inductors [2–4]. Another commonly used technique is the use of feedback amplifiers [ 5 – 10 ]. This solution offers a good return loss, but, due to the feedback, it is difficult to achieve a low noise figure with a reasonable power consumption. As an alternative to these two previous topologies, some authors have proposed the design of wideband circuits by converting narrowband circuits into broadband [ 11 – 13 ]. This is usually achieved by modifying the input matching network to act as a broadband filter and replacing the narrowband load (typically a tank circuit) with any of the wideband RC load implementations: series-peaking, shunt-peaking, shunt-series-peaking, etc. [ 14 – 16 ]. Again, as in the case of the distribute amplifier technique, the main limitation of this solution is the area as they use a large number of inductors. Note that the issues of large area and high power consumption are aggravated when variable gain is desired. Electronics 2020,9, 1600; doi:10.3390/electronics9101600 www.mdpi.com/journal/electronics Electronics 2020,9, 1600 2 of 12 To reduce the area constraints, some authors have proposed the use of common-base or common-gate wideband amplifiers [ 14 – 16 ]. These topologies take advantage of the fact that, in such configurations, it is possible to obtain a broadband input impedance equal to 50 Ω by properly biasing the transistor. However, the gain and noise figure are determined by this biasing and consequently fixed to a certain value. At system level, when implementing a wideband analog RF front-end, the most popular scheme includes a wideband low noise amplifier (LNA) followed by a variable gain amplifier (VGA). This maximizes the dynamic range of the upcoming stages and prevents the saturation of the receiver if a high-powered signal is received [ 17 ]. In these cases, the implementation of a wideband RF-VGA is of upmost interest. This work addresses the design of a very compact, low power, low voltage, and high bandwidth RF-VGA using second generation controlled current conveyors. A CCCII is a four terminal device that can perform many useful analog signal processing functions when arranged with other electronic elements in specific circuit configurations [ 18 ]. CCCIIs have been successfully used in high frequency current mode applications such as filters [ 19 ] and LNAs [ 20 ]. The proposed radio frequency variable gain amplifier (RF-VGA) is based in the CCCII proposed in [ 21 ] and has been designed and fabricated in a low cost 0.35 µ m SiGe BiCMOS technology. The rest of the paper goes as follows: Section 2reviews the CCCII and describes the proposed RF-VGA topology and the design methodology, Section 3 focuses on the circuit performance and the analysis of the obtained results; finally, some conclusions are drawn in Section 4. 2. RF-VGA Based on the Current Conveyor CCCIIs can be used to implement numerous functions, such as filtering, amplification, or impedance transformation. They also provide better performance than traditional OTAs, namely, improved power consumption and larger cut-off frequency [19]. A CCCII is a device with three ports ( X , Y and Z ) and a DC bias current ( I0 ). Each port is characterized by an impedance ( ZX , ZY and ZZ ) resulting from the implementation of the conveyor with non-ideal components. These impedances are defined by parasitic elements, which are highly dependent on the selected technology of fabrication and the bias current I0 . Thus, the concept of controlled current conveyor appears due to this dependence on I0 . The relationship that governs the interactions between the ports of the conveyor is defined as follows: •between ports Xand Zthe device acts as a current follower, •between ports Yand Xit operates as a voltage follower, •between ports Zand Yit behaves as a transconductor. The matrix that defines these relationships is given by    IY VX IZ   =   YY(I0)0 0 β(s)ZX(I0)0 0α(s)YZ(I0)   ·   VY IX VZ   (1) where YY is the conductance of port Y , and YZ , the conductance of port Z . In addition, the terms α(s) and β(s) represent the unity current and voltage transfer functions. The resistive component of ZX (defined as RX) is particularly relevant since it can be used to define the interaction between ports. Variable gain amplifiers can be implemented using CCCIIs [ 19 – 21 ], where the gain tuning is performed by means of adjusting the bias current of the conveyor. The dependence of RX on the bias current I0 can be exploited to provide wideband input matching without including a single passive component, resulting in a circuit with a very low input return loss. This situation is desirable in scenarios where the amplifier is the first integrated circuit in the reception path. For example, if a preceding LNA is added externally, the proposed RF-VGA facilitates impedance matching with Electronics 2020,9, 1600 3 of 12 this element, and the signal coming from the LNA is received with a very low loss. In addition, the proposed design can potentially obtain a high cut-off frequency and low die footprint due to the reduced number of active devices needed to implement the conveyor. To implement an RF-VGA, two CCCII blocks are connected as shown in Figure 1[ 20 ]. Provided that the impedances ZX1 and ZX2 are entirely resistive, VIN(t) is transformed into a current IIN(t) . This current is then converted into a voltage signal again thanks to ZX2 . Due to the relationship between RXand the bias current I0, it can be proved that the gain Gof the amplifier reduces to: G=VOUT(t) VIN(t)=I01 I02 (2) Figure 1. Connection of two CCCII blocks to provide voltage amplification. Since the node Y1 presents a high input impedance [ 19 ], the input signal is applied at node X1 . By doing so, the input impedance is reduced and can be controlled by the bias current I01 . Thus, the input impedance ZIN of the RF-VGA can be adjusted by means of adjusting the value of the bias current I01, which is fixed to obtain |ZIN|=50 Ω. The value of the bias current I01 can be fixed to perform wideband input matching, and so the gain can be adjusted by setting the value of I02 . Due to the inversely proportional relationship given by (2) , it is possible to increase the gain by reducing the bias current I02 . Therefore, higher gain settings lead to lower power consumption. A simple Class-A implementation scheme with CCCIIs is shown in Figure 2a. To obtain the structure depicted in Figure 1, nodes Z1 and X2 must be connected together, yielding the circuit depicted in Figure 2b. As mentioned above, the input signal is applied at node X1 to facilitate input matching, allowing the elimination of transistor Q11 . The resulting scheme after simplification is presented in Figure 3. With this result, the number of BJTs is reduced as much as possible, yielding a higher cut-off frequency and a better noise performance [ 22 ]. The required values of the bias current I01 obtained in simulation to achieve a 50 Ω input impedance are plotted in Figure 4 for various transistor areas from the 0.35 µm SiGe design kit used. The voltage gain and the bandwidth of the RF-VGA are plotted in Figure 5. The values between 100 µ A and 250 µ A present a trade-off between gain and bandwidth and can be used to determine the optimal combination of device area and bias current I02 . When I02 augments, the gain of the circuit drops while the bandwidth raises. The gain is not significantly affected by the variation in the transistor area, but, as expected, the bandwidth is increased if the area is reduced. Although the RF-VGA may be preceded by an LNA, its noise figure (NF) is one of the most relevant parameters in the design. If the LNA gain is low, the RF-VGA must provide a reduced NF and high gain to avoid degradation of the receiver performance. Electronics 2020,9, 1600 4 of 12 Figure 2. Class-A CCCII basic schematic ( a ) and topology of a voltage-mode amplifier using two basic class-A blocks (b). Figure 3. Schematic of the RF-VGA after simplification. Figure 4. Bias current I01 vs. transistor size to obtain an input impedance of 50 Ω. Electronics 2020,9, 1600 5 of 12 Figure 5. Simulated gain and bandwidth results of the RF-VGA at VDC =±1.5 V. Depending on the application of interest, a trade-off between gain, noise, and bandwidth must be considered by the designer. In this implementation, the number of elements in the signal path is kept as low as possible (only tree BJTs), and there is a total absence of passive elements. Consequently, the noise introduced by spurious elements is minimized and the main noise contribution is due to the input transistor Q21. Figure 6depicts the simulated NF of the circuit for different transistor areas, where it is shown that the NF decreases when the device area is increased. The noise figure of the RF-VGA is also plotted against I02 in Figure 7for a transistor area of 20 µ m 2 . Note that the noise figure is strongly dependent on the bias current, so that, when I02 increases, the gain is reduced and the NF augments. If a high gain and a low NF is desired, a lower I02 and a higher transistor area are required. However, this situation limits the achievable bandwidth since a low bias current combined with a high aspect ratio yields a reduced frequency performance (see Figure 5). As a result, a trade-off between noise figure, gain, and bandwidth is present and should be considered depending on the design specifications. Electronics 2020,9, 1600 6 of 12 Figure 6. Noise figure vs. transistor area. Figure 7. Noise figure vs. I02 for a transistor with 20 µm2. The final RF-VGA schematic is shown in Figure 8, where the current sources have been replaced with MOS transistors. The RF-VGA was designed and laid out in a BiCMOS SiGe 0.35 µ m process with a DC supply of ± 1.5 V. The layout of the circuit is presented in Figure 9. The layout was realized taking into account critical aspects of analog RFICs, such as circuit symmetry and transistor matching techniques to reduce PVT variations. The selected areas for each transistor were chosen to achieve a Electronics 2020,9, 1600 7 of 12 maximum gain of 18 dB and a 900 MHz bandwidth with a total current consumption below 2 mA. The size of Q21 is 20 µ m 2 , which is twice the size of Q12 and Q22 , with 10 µ m 2 each. The aspect ratio of the NMOS and PMOS transistors is 20/1 (µm/µm). Figure 8. Schematic of the proposed RF-VGA. Figure 9. Die micro-photograph of the RF-VGA. 3. Measurements Probe pads were added for on–wafer measurements. Two ground-signal-ground (GSG) and two signal-ground-signal (SGS) pads structures with 150 µ m pitch were used. The DC supply is ± 1.5 V and the amplifier draws a current of 1.7 mA. The total chip size of the RF-VGA including pads is 800 × 430 µ m 2 , but the core of the circuit occupies an area as low as 62 × 44 µ m 2 . The voltage gain of the RF-VGA is plotted in Figure 10 for a frequency range of DC–3 GHz vs. bias current I02 . A good agreement between measurement and simulation can be found with an error below ± 1.1 dB in the entire band. As expected, when I02 is increased, the gain of the circuit decreases while the bandwidth raises. The simulation and measurement results of the NF of the proposed design are depicted in Figure 11. As can be seen, the NF increases with the bias current I02 . A reduced bias current (i.e., higher gain) is needed if a low noise figure is required. As mentioned above, the drawback is a reduction in the bandwidth of the amplifier. In many applications, it is desirable to extend the bandwidth thus a multistage approach or a bandwidth enhancement technique would be needed to obtain a high-gain and wide-band. For NF, the error between simulation and measurement is below 1.4 dB. Electronics 2020,9, 1600 8 of 12 Figure 10. Measured and simulated gain of the RF-VGA for different bias currents I02. Figure 11. Measured and simulated NF of the RF-VGA for different bias currents I02. Electronics 2020,9, 1600 9 of 12 Another key parameter for the performance of the RF-VGA is the input return loss. When the LNA is implemented externally, the RF-VGA is the first integrated device in the receiver; thus, a broadband 50 Ω input match is required. The simulated and measured S11 are shown in Figure 12, where the measured magnitude for the S11 is better than 20 dB for frequencies up to 10 GHz. Figure 12. Measurement and simulation of the input return loss S11 for for I01 = 600 µ A and I02 = 50 µ A. The linearity of the proposed RF-VGA was evaluated by measuring the input 1-dB compression point ( P1dB ) using a test tone of 666 MHz. The measurement results for maximum gain settings ( I01 = 600 µ A and I02 = 50 µA) are plotted in Figure 13, obtaining a value of –20.18 dBm for the input P1dB. Figure 13. Measurement of the input 1-dB compression point for I01 =600 µA and I02 =50 µA.