Common DC-Link Capacitor Harmonic Current Minimization for Cascaded Converters by Optimized Phase-Shift Modulation

Citation: Zhou, X.; Choy, W.J.; Alcaide, A.M.; Wang, S.; Guenter, S.; Leon, J.I.; Monopoli, V.G.; Franquelo, L.G.; Liserre, M.; Galea, M.; et al. Common DC-Link Capacitor Harmonic Current Minimization for Cascaded Converters by Optimized Phase-Shift Modulation. Energies 2023,16, 2098. https://doi.org/ 10.3390/en16052098 Academic Editors: Ralph Kennel and Mohamed Abdelrahem Received: 7 December 2022 Revised: 25 January 2023 Accepted: 26 January 2023 Published: 21 February 2023 Copyright: © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). energies Article Common DC-Link Capacitor Harmonic Current Minimization for Cascaded Converters by Optimized Phase-Shift Modulation Xuanyi Zhou 1, Wei Juin Choy 2, Abraham M. Alcaide 3, Shuo Wang 1, Sandro Guenter 1, Jose I. Leon 3,4 , Vito Giuseppe Monopoli 5, Leopoldo G. Franquelo 3,4 , Marco Liserre 6, Michael Galea 7, Chris Gerada 2 and Giampaolo Buticchi 1,* 1Key Laboratory of More Electric Aircraft Technology of Zhejiang Province, Department of Electrical and Electronic Engineering, University of Nottingham Ningbo China, Ningbo 315104, China 2Power Electronics, Machines and Control Group, University of Nottingham, Nottingham NG7 2RD, UK 3Electronic Engineering Department, Universidad de Sevilla, 41004 Seville, Spain 4Department of Control Science and Engineering, Harbin Institute of Technology, Harbin 150001, China 5Department of Electrical and Information Engineering, Politecnico di Bari, 70126 Bari, Italy 6Power Electronics Department, Christian-Albrechts Universität zu Kiel, 24118 Kiel, Germany 7Department of Industrial Electrical Power Conversion, University of Malta, MSD 2080 Msida, Malta *Correspondence: [email protected] Abstract: This paper investigates the influence of a constant carrier phase shift on the DC-link capacitor harmonic current of cascaded converters used in fuel-cell and mild-hybrid electric vehicles. In these applications, a DC-DC converter can be adopted between the battery and the motor drive inverter in a cascaded structure, where the two converters share the same DC-link. Since the DC- link capacitor of such a system represents a critical component, the optimization of the converter operation to limit the current stress and extend the lifetime of the capacitor is an primary objective. This paper proposes the use of a carrier phase shift between the modulations of the two converters in order to minimize the harmonic current of the DC-link capacitor. By harmonic analysis, an optimal carrier phase shift can be derived depending on the converter configuration. Analytical results are presented and validated by hardware-in-the-loop experiments. The findings show that the pulse width modulation carrier phase shift between the interleaved boost converter and the voltage source motor drive inverter has a significant influence on the DC-link capacitor current and thus on its lifetime. A case study with two-cell and three-cell interleaved boost converters shows a possible DC-link capacitor lifetime extension of up to 390%. Keywords: DC-link capacitor; capacitor harmonic current; harmonic minimization; interleaved boost converter; phase-shift modulation 1. Introduction The electrification of transportation modes, both passenger and freight, is considered to be one of the key approaches for tackling carbon emissions in order to address the pressing environmental issues [ 1 ]. In fuel-cell and mild-hybrid applications, a low-voltage battery typically powers a voltage source inverter that controls the electric machine. In order to optimize the electric drive design, a DC-DC converter can be adopted between the battery and the inverter, and the two converters share the same DC-link. The lifetime of the DC-link capacitor is very important for the reliability of the whole converter system [2–5]. The capacitor lifetime heavily depends on the temperature of the capacitor, which is related to the root-mean-square (RMS) of the DC-link capacitor harmonic current. To reduce the capacitor harmonic current, many related studies have been carried out, aimed at either hardware solutions or modulation strategies. Many different hardware topologies have been discussed to achieve a current ripple reduction for the DC-link in different areas [ 6 – 15 ]. Owing to the requirement for highly Energies 2023,16, 2098. https://doi.org/10.3390/en16052098 https://www.mdpi.com/journal/energies Energies 2023,16, 2098 2 of 15 constrained systems with low volume and low weight, ref. [ 6 ] pointed out a generalized method to optimize a DC capacitor tank. In this case, different systems require different DC capacitor tanks, thus the cost could not be ignored. Consequently, adding one more power conversion stage between the battery and the inverter is explored as the highest adoption technique to balance the current energy of the DC-link [ 7 – 15 ]. The method utilizes a back-to-back converter containing a rectifier and an inverter, which could reduce the capacitor harmonic current when the pulsed DC-link current of the rectifier and inverter are synchronized [ 7 ]. However, this method only explains the harmonic current could be controlled at an acceptable range. A bidirectional buck-boost converter is operated as a power decoupling stage to handle the harmonic content of the DC-link. This system increases the complexity, and some instability is caused by the difference between the stored and released energy of the decoupling capacitor [ 8 ]. In [ 9 ], an active power filter is added to a three-phase traction system and the capacitor of the DC-link is decreased from 2200 µ F to 100 µ F. With the concerns of larger inductor current, high operation frequency, and power loss, this method is hard to use in practical applications. Additionally, for converter systems in fuel-cell applications, a comparative study pointed out that the voltage source inverter (VSI) connected in cascade with a boost converter is the best choice for the transformerless converter when considering the system complexity and power rating with other topologies, such as current source inverter, z-source inverter, and current fed full-bridge converter [ 10 ]. Consequently, one conventional boost converter and one VSI are connected to reduce the current ripple of the DC-link capacitor current in [ 11 – 13 ]. In particular, the modulations and power factor are unity in [ 11 ] and various power factors are used in [ 13 ]. For the harmonic current ratios, it reached 17–20% in [ 11 , 12 ] and 37% in [ 13 ], and all values were less than 40%. In addition, according to the performance analysis of interleaved boost converters in [ 14 ], the two-cell interleaved boost converter shows a better current ripple reduction than the conventional boost converter. Consequently, interleaved converters have been widely used in electric vehicles (EVs) to extend the power capability of such systems [ 15 ]. Therefore, the topology used for the investigation presented in this paper contains one VSI cascaded with two/three-cell interleaved boost converters to achieve a reduced capacitor current. Despite hardware-based methods, another way to achieve a reduction in capacitor current is via modulation strategies, which are presented in the following. A method to reduce the current ripple is presented in [ 7 ]; while the achieved reduction is acceptable, the procedure increases the capacitor stress depending on the output modulation index and power factor. In [ 16 ], the authors proposed a special single-phase modulation method that only switches on or off one of the three-phase legs in each PWM-carrier period. The experimental results show that the harmonics distortion is reduced from 4.9% to 4.1%. The carrier can shift the output current pulse of the DC-DC converter to match with the inverter input current, so that the current ripple could be decreased, but the reduction ratio is no more than 20% [ 11 ]. An optimal space vector modulation method was studied in [ 17 ]. The current ripple reduction of DC-link can be achieved without increasing the switching frequency or inductance, but the ripple factor can only be reduced from 100% to 56.7%. With calculation, the harmonic current reduction is 43.3%. In hybrid electric vehicle (HEV) DC-DC-AC systems, a modified triangle carrier is utilized with a double switching frequency like that of the inverter, and the capacitor current ripple could achieve a 50% reduction rate [ 18 ]. Table 1summarizes some of previous current cancellation methods alongside the harmonic reduction ratio. The proposed method aims to improve the ratio of harmonic reduction. As the adaptive phase shift technology has been widely used for different applications [ 19 – 21 ], this paper proposed the use of a phase shift between the PWM carriers of the cascaded converters. Energies 2023,16, 2098 3 of 15 Table 1. Comparisons of previous harmonic cancellation methods. Methods [11] [12] [13] [16] [17] [18] Harmonic reduction ratio 17% 20% 37% 4.9–4.1% 43.3% 50% If one signal processor is used to control both cascaded converters, it is possible to set a constant carrier phase shift in between the pulse-width modulation (PWM) of two converters. Thus, this paper proposes to set a constant PWM carrier phase shift to minimize the DC-link capacitor harmonic current. A comparison between a two-cell and three-cell interleaved boost converter cascaded with a VSI motor drive is conducted in order to find the optimal PWM carrier phase displacement. Furthermore, due to the interleaved topologies of the boost converter, an optimal switching frequency ratio between the PWMs of the cascaded converters is derived from analytic harmonic analysis. These optimal switching frequency ratios and the PWM carrier phase displacement lead to a minimized DC-link capacitor harmonic current and thus extend its lifetime. This manuscript is structured as follows. After a brief system description in Section 2, in Section 3the common capacitor DC-link is analyzed and equations for the DC-link currents are derived. In Section 4the details of the proposed current harmonic minimization are illustrated. Then, experimental results are given in Section 5with some extended theoretical analysis of capacitor lifetime. Finally, Section 6is summarized to explain the main contribution of the proposed method. 2. System Description of the Proposed Cascaded Converter In Figure 1, the structure of the proposed cascaded converter is shown, which contains a two-cell interleaved DC-DC converter and a VSI connected to a permanent magnet synchronous motor (PMSM). For the DC-AC stage, six insulated gate bipolar transistors (IGBT) switches are used as the top switches ( Sa , Sb , Sc ) and bottom switches ( ¯ Sa , ¯ Sb , ¯ Sc ), respectively. Similarly, the DC-DC converter consists of top switches ( S1 , S2 ) and bottom switches ( ¯ S1,¯ S2). Here, ic,dcdc is the DC-link current of the interleaved boost converter and ic,vsi is the VSI demand current. The current through the capacitor is ic and the relationship can be expressed as Equation (12). In a complex power conversion system such as the one proposed in Figure 1, the capacitor stress of the common DC-link is of crucial importance for the reliability of the whole power conversion system and also affects the overall loss of the system. Thus, these three currents are the key points to investigate. Futhermore, Vd is the input voltage, Vo is the output voltage of the interleaved DC-DC converter, and ia , ib , and ic represent the AC current, which flow out from the VSI. i1 and i2 represent the DC-DC inductor current. Sa S1S2 Sa Sb Sb Sc Sc Vo Vd ia ib ic O a b c Ln S1 i1 i2 S2 ic,dcdc ic,vsi ic Figure 1. Simplified multi-port converter composed of a two-cell boost converter and a traditional two-level VSI. ©2021 IEEE [22]. Energies 2023,16, 2098 4 of 15 Furthermore, Figure 2displays the relationship between current ripple cancellation factor and the duty cycle variations. The current ripple cancellation factors include the DC-DC converter current ic,dcdc and the inverter demand current ic,vsi . The duty cycle depends on the voltage ratio between Vd and Vo , and the optimal harmonic cancellation phase number N of the interleaved converter is obtained. However, for a system containing several converters in a cascaded structure, the influence of the other converters needs to be taken into account in order to find the optimal number of interleaved phases. Moreover, considering the proposed harmonic current reduction method, a certain harmonic current of the DC-DC converter can be beneficial in order to compensate for the harmonic current of the VSI and thus reduce the DC-link capacitor current. Furthermore, depending on the application, the number of parallel connected modules can be varied. Therefore, in the following analysis, the cases with two and three interleaved DC-DC converters will be considered. 0 0.2 0.4 0.6 0.8 1.0 Duty Cycle 0 0.2 0.4 0.6 0.8 1.0 Current Ripple Cancelation Factor 1 phase 2 phases 3 phases 4 phases 5 phases 6 phases Figure 2. Second terminal capacitor current ripple cancellation factor as a function of duty cycle for a different number of active phases. ©2022 IEEE [23]. 3. Analysis of the Common Capacitor DC-Link The main stressors for the capacitors are represented by the voltage, the temperature, and the humidity [ 4 ]. The latter is often ignored under the assumption of proper environmental isolation of the power electronics. The most common lifetime model for capacitors can be expressed as: L=L0V V0−n eEa kB1 T−1 T0(1) where Land L 0 are the lifetime under the operational conditions and testing conditions (usually given by the manufacturer), respectively. The temperatures Tand T 0 are defined in the same manner. K B is the Boltzmann’s constant. The activation energy E a and the exponent nare specific for the capacitor type. For aluminum electrolytic capacitors, nis about 3 to 5 and E a is 0.94 eV [ 4 ]. Since the temperature and voltage represent the main stressors, it is important to estimate the hotspot temperature for the correct design of the DC-link. An overall model of an electrolytic capacitor is reported in Figure 3a, where C represents the main capacitance value, and the other elements represent the temperaturedependent ( Rt=Rt0eTb−T SF , with Tb as the base temperature and SF as the temperature sensitivity factor) and frequency-dependent (parallel of RD and CD ) components of the Energies 2023,16, 2098 5 of 15 equivalent series resistance (ESR). R0 is the base value. It was highlighted in [ 24 ] that for the PWM harmonics (kHz range) the variation of the ESR due to the dielectric loss is minimal, whereas it is important to correctly estimate the temperature, since Rt has a wide range of values (as shown in Figure 3b). 102103104105 0 0.2 0.4 0.6 0.8 1.0 25ºC 50ºC 75ºC RESR (Ohm) Frequency (Hz) a b Figure 3. ( a ) Electrolytic capacitor series model. ( b ) Example of the dependence of the ESR parameter in a electrolytic capacitor with frequency and temperature. ©2022 IEEE [23]. The power loss due to the harmonic current components and the ESR represents the heat source, and with the knowledge of the thermal impedance of the capacitor and ambient temperature, the overall hotspot temperature can be determined. It appears evident that, given the operating point of the electrical machine, the power balance between the two stages must be ensured, meaning that the average values of the input/output current are fixed. The degrees of freedom are represented by the frequencies of the single converters and their relative phase-shift. Other degrees of freedom (i.e., the modulation) are not explored for the sake of simplicity. 3.1. Harmonic Analysis of the Current Injected by Interleaved DC-DC Converters The influence of the interleaved DC-DC boost converter over the harmonic spectrum of the current absorbed on the DC side of the inverter is studied by the Fourier Series, because it is a uni-dimensional problem [ 25 ]. In other words, the duty cycles, which are to be compared with the triangular carriers, do not vary periodically with time in a steady state system. In these terms, this mathematical tool enables the decomposition of any periodic signal to a DC component plus an infinite sum of sines and cosines as f(t) = a0 2+ ∞ ∑ n=1hancos(nωt) + bnsin(nωt)i an=2 TZT 0f(t)cos(nωt)dt bn=2 TZT 0f(t)sin(nωt)dt. (2) Energies 2023,16, 2098 6 of 15 where ω is the frequency under study, that is, the carrier frequency of the DC-DC system (fc,dcdc) in this case and anand bnare Fourier’s coefficients. In addition, if the DC-DC interleaved converter is composed of several power cells, the resulting output is determined by the summation of the current of each power cell in an independent way. The resulting output current is highly influenced by the phaseangle displacement adopted in the operation of the parallel converter. This influence is determined by N ∑ j=1 ij(t) = N ∑ j=1 a0j 2+ N ∑ j=1 ∞ ∑ n=1hanj cos(nωt−nφj) +bnk sin(nωt−nφj)i(3) where φjis the phase-displacement angle applied to the j-th power cell. After some mathematical manipulation, each particular harmonic component (n) injected in the common capacitor DC-link shown in (3) can be re-written in a compact form as ic,dcdc,n(t) = cos(nωt)N ∑ j=1 anj −bnj tan(nφj) q1+tan(nφj)2 +sin(nωt)N ∑ j=1 bnj +anj tan(nφj) q1+tan(nφj)2 =C1ncos(nωt) + Cn2sin(nωt) = Hn(4) where it is possible to decompose the magnitude and phase as kHnk=qC2 1n+C2 2n ∠Hn=arctan C2n C1n(5) Remark: Note that index n represents a harmonic order, meaning a multiple of the particular carrier frequency. On the other hand, the coefficient values for ank and bnk are strictly determined by the specific DC-DC converter topology under study. In the application case of the bidirectional DC-DC interleaved boost converter considered in Figure 1and also illustrated in Figure 4b, the resulting output current can be defined as iak(t) = mt +ILwhere m=Vd−Vo L(6) Then, considering (2) and the definitions shown in Figure 4, the coefficients an and bn can be calculated as an=2 TZ(1−D)T 2 −(1−D)T 2 (IL+mt)cos(nωt)dt =2IL nπsin(nπ(1−D)) bn=2 TZ(1−D)T 2 −(1−D)T 2 (IL+mt)sin(nωt)dt =mT n2π2hsin(nπ(1−D)) +nπ(1−D)cos(nπ(1−D))i(7) Energies 2023,16, 2098 7 of 15 iout(t) IL D(t) (1-D)T 0.5DT a b L Sn Sn C v o (t) V d iL(t)iout(t) Figure 4. ( a ) Bidirectional DC-DC boost converter topology ( b ) Triangular carrier, modulating signal, and output current (the average value of the inductor current IL is also represented). © 2022 IEEE [ 26 ]. 3.2. Harmonic Analysis of the Current Demanded by the Inverter The influence of the inverter drive connected to the system over the common capacitor DC-link is studied by the double Fourier Transform, since, unlike the DC-DC system, it is a two-dimensional problem because of the variation of the duty cycle during the fundamental period [ 27 ]. Considering a conventional two-level voltage source inverter (2L-VSI), as shown in Figure 1and using the double Fourier Transform, the resulting harmonic spectrum of the current absorbed on the DC side of the inverter is given by ic,vsi(t) = 3 4MI0cos(Φ) + ∞ ∑ m=1 ∞ ∑ n=−∞A0 mn cos mωct+nω0t +B0 mn sin mωct+nω0t(8) where M is referred to as the modulation index, Io is the fundamental output current, and Φ is the resulting power factor. Additionally, coefficients A0 mn and B0 mn are determined by: A0 mn =Amn1+2 cos n2 3π B0 mn =Bmn1+2 cos n2 3π µ= I0cos (m+n)π 2cos(Φ) mπ Amn =µhJn+1mπ 2M−Jn−1mπ 2Mi Bmn =µhJn+1mπ 2M+Jn−1mπ 2Mi (9) where coefficients m , n are referred to as the specific harmonic group ( m ) and the particular harmonic component inside the group ( n ). The decomposition in terms of magnitude and phase (denoted as Zk for convenience) of each particular harmonic component can be performed in a similar way, as carried out in (5). Energies 2023,16, 2098 8 of 15 kZkk=qA0 mn2+B0 mn2 ∠Zk=arctan B0 mn A0 mn (10) Remark: Note that indexes m and n are different from those used in the analysis presented in Section 3.1. Index k is related to the specific harmonic order, which is calculated as k=mR +n(11) where parameter R is referred to as the ratio between the fundamental frequency and the carrier frequency. From the analysis used in (8) , it can be seen that the current demanded by the inverter is decomposed by a DC component plus a sum of carrier harmonic and side-bands harmonic components. These carrier harmonic components are highly influenced by the operational condition of the drive inverter, that is, the magnitude of the coefficients A0 mn and B0 mn is determined by the fundamental output current, as well as the resulting power factor (i.e., the active and reactive powers). Additionally, it is also possible to observe that the main harmonic component of the capacitor current is located at the frequency given by m= 2 and n= 0, as shown in Figure 5[27,28]. 100 150 200 250 300 0 2 4 6 m =1 m =2 n =0 m =3 n =±3 n =±3 n =±6 Harmonic order (n) Capacitor current (A) Figure 5. Example of the capacitor current harmonic spectrum decomposition by using the Double Fourier integral. ©2022 IEEE [23]. 4. Capacitor Current Harmonic Minimization The operation of the whole power conversion system is, in general terms, decoupled. As shown in Figure 6, each subsystem is operated by an independent control structure and the time-synchronization between both systems is not strictly required. On one hand, the conventional control scheme for a DC-DC interleaved converter is shown in Figure 6a. As a result, the energy in the harmonic spectrum of the current injected to the common DC-link is located at N times fc,dcdc , considering a completely balanced operation. On the other hand, the conventional stationary dq-frame control strategy for a motor drive is also shown in Figure 6b. As previously discussed, not only the magnitude and phase of the harmonic spectrum are highly dependent on multiple factors such as the fundamental current magnitude and resulting power factor, but also the location of these harmonic components is dependent on the fundamental output frequency. In general terms, only the harmonic component located at m= 2 and n= 0 remains in this location during the operation of the inverter, as shown in Figure 5. Fortunately, this harmonic component is the main harmonic component in the demanded current by the inverter drive. In fact, the Energies 2023,16, 2098 9 of 15 frequency of the base-band harmonics normally changes because it is necessary to change the modulating signal frequency to achieve speed regulation. dq abc PWM PWM abc dq wr w £ iq id PI PI PI + - + - + - PI i d = 0 * iq * vabc * iabc Sx S n abc * Encoder PMSM PI vn V0 Vd* 2Vd 1+- vn * In * P* In PI +- Vo * Vo dn a b Phase displacement ' Figure 6. Conventional control structure for ( a ) an interleaved DC-DC boost converter. ( b ) Conventional stationary dq-frame control strategy for a motor drive. ©2021 IEEE [22]. Finally, applying Kirchoff’s first law in the common DC-link capacitor, it is possible to obtain the resulting current flowing through the capacitor as ic(t) = ic,dcdc(t)−ic,vsi(t)(12) Thus, a partial harmonic minimization can be achieved if a specific carrier frequency ratio between subsystems is adopted and an optimum phase-shifting is applied between them. In other words, and considering the system shown in Figure 1, the carrier frequency of both subsystems should fulfill 2fc,inv =N fc,dcdc (13) which ensures that the main harmonic components of both subsystems are located at the same frequency. At the same time, the phase displacement angle between carriers of both subsystems should minimize the resulting ic(t). That is, ϕ: min Hn+Zk(14) where coefficients n and k should be selected according to the appropriated harmonic order. 5. Experimental Results In order to verify the performance of the proposed method, several sets of experiments have been conducted to highlight the reduction in the capacitor harmonic current. The real-time experiment setup is shown in Figure 7, and an oscilloscope was used for data measurement. The PLEXIM RTBox 3 was connected with the LAUNCHXL-F28069M by an interface PLEXIM board. The prototype was separated into a controller part and a plant part. The controller part is displayed in Figure 6, and the plant part is set up as shown in Figure 1. The DC voltage power supply is 250 V and boosts to 800 V when using the multi-phase interleaved converter. Moreover, with the hardware-in-the-loop technique, the controllers of the two converters can be synchronized. The plant specifications are listed below in Table 2.