On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line

On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line. Sara Escalera, Carlos M. Dominguez-Matas, J. Manuel Garcia-Gonzalez, Oscar Guerra and hgel Rodriguez-Vazquez .. Instituto de Microelectrdnica de Sevilla (IMSE-CNM-CSIC) AV. Reina Mercedes, lIOIbSevilla, SPAIN. E-mail: [email protected] Abstract - This paper presents a CMOS 0,6pm mixedsignal MODEM ASlC,for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulationidemodulation (PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, decision circuitry, etc.) plus the logic circuitry needed for control purposes. The circuit operates correctly in the whole industrial temperature range, from -45 to 80°C, under 5% variations of the 3.3V supply voltage. control of the devices connected to the system, but not too large, taking into account that the main objective is to provide the largest number of channels as possible, to allow the control of a high number of devices2. Having all this into account, a global frequency range (that will contain all the communication channels) from 90kHz to 3501iHz will be used to avoid interferences with the HFM, with a minimum speed limit of 100bitsis. Again, to increase the transmission quality, two channels will be simultaneously available; one to control the quality ofthe communication and a second one to enable the data transmission. Of course, it is obligatory that the ASIC functionality has to be ensured if some, or even all, the channels are active. The type of modulation used has to be able to maximize the number of channels Providing high reliabiliW against be presence of mukiple signals in the transmission line, noise, line impedance changes, etc. 1. Introduction ' is well how [hat the use of communication to control multiple home devices enables a regulation on their cost and allows their control outside home. To anain this objective, it is mandatory to provide systems able to deal with multiple data transmission channels with sufficient speed to allow, with a IOW cost, a permanent link between the control centres that provide the access to those devices, the user and the devices themselves. Current systems, based on communication networks, have to deal with very high installation costs due to the need of a parallel network to enable the communication. However, this limitation can be surpassed by using the existing low-voltage power-line to allow the data transmission. Of course, this altemative is not free from some concems: 9 High reliability requires a supervision logic to control the data transmission. * Low cost implies a high integration of the electronic circuitry. * Data transmission speed involves the exploration of adequate modulation techniques. To overcome all these limitations, an ASIC composed by two different basic blocks has been designed as described below: figure 1. MODEM architecture A pan of the ASIC sigh Frequencies Module from now on) All the modules in the communication network will include has to send and receive signals using two different channels (to these blocks although only partially enabled depending on their ensure the communication in case of transitory degradation of requested functionality. one of the channels). This block will enable the communication Taking into account the position within the communication with the control centre that can be as far as one kilometer beyond network, the developed modem has to work with the following the modem. In the approach presented here, the frequency of the requirements, that are illustrated in Fig. 2. channekhas been settled to 375kHz and 450kHz, due to the low level of noise experimentally found at these values. .Main Master Modules (MMM) that can communicate A second block (Low Frequencies Module from now on), with the control centre using the HFM and their own High will be used to control the communication inside each building. Frequencies Control Module (HFCM). Also, they can Thus, the basic requirements for this block are to enable the data communicate with other master and slave modules using one of transmission through small distances (between 50 and 100 the LFM's for each channel. The Low Frequencies Control meters),with a speed that has to be enough to ensure a real-time Module (LFCM) has to be able, at any moment, to assign any of the low frequency channels to be either communication or *Simple Master Modules (SMM) that are not allowed to 2. ASIC operation modes The architecture for the ASIC is shown in Fig. 1. 1. This work has been suppolted by the C.I.C.Y.T., Spain under Grant 1FD97-1611(TIC), and by the Spanish Ministry of Science and Technology (with support from the European Regional Development Fund) under contract TIC200 1-0929. 2. The larger the speed, the wider the channel required. II-29 0-7803-7761-3/031$17.00 02003 IEEE Figure 2. Example of communication hierarchy between modules contact the HFM (thus, HFM and HFCM should be disconnected). At low frequencies, their functionality is as any MMM. .Slave Modules (SM) that share information using a single channel with only one MM, assigned during the configuration of the system. Thus, HFM, HFCM and one LFM will .be disconnected. They will only respond (but necessarily) upon their master requirement. The two components of the identification code will be defined by a serial communication interface, that will be stored in an EEPROM. This information will be used during the initialization of the system. 3. Description of the Circuit The already reported HFM, [6], has been shown to demodulate signals down to 283pVrms under nominal operating conditions, and obtain a worst case sensitivity of 3 I6~Vrms within the whole industrial temperature range, and under 5% variations of the supply voltage. TransmissioniReception (Tx/Rx) is done within temporal windows located around the zero crossing of the SOHd 60Hz power-line voltage, using two frequency channels located at 375kHz and 450kHz, where clean frequency windows have been encountered in field evaluations. Fig. 3 shows a functional ,scheme of one Transmission- Reception Low Frequencies Module (TRLFM). When it is operating as a demodulator, the signals enter by the input amplifier and are filtered to eliminate the noise and select the desirable frequency. The tuning channel is selected by a digital control and the required frequency is captured using a phase locked loop (PLL).The filtered signal is demodulated and the result is processed by the digital control, that makes it available for the customer or sends it to the Communication Centre. In the modulation stage, the digital control is used not only to choose the channel in which the message is going to be transmitted, but also to generate it. Figure 3. Conceptual TRLF Module operation: transmissionlreception sections. Fig.4 (a) shows the schematic of the bandpass filter used in the TRLFM [7]. This architecture has been chosen because of three reasons: the first one is that this circuit has a very high quality factor, ideally infinite ifmismatching is not taken into account; the second one is that the tuning frequency is independent of the quality factor and, finally, this structure has the same parasitic that the voltage controlled oscillator, which has been designed with the same structure', so it is expected that both have the same frequency dependence behaviour. Expression (I) shows the dependence for the tuning frequency when the analysis of the filter in Fig. 4 (a) is done taking into account the output resistance of the OTA's. In our approach, the tuning is performed in two steps: first, a frequency range containing the desired frequency value is delimited by the selection of Cl and C,, then, to select the correct frequency value, the transconductances gml and gm2 are vaned using a tuning voltage, Vtuning, that is generated by the PLL structwe shown in Fig.4 (b). If only one pair of capacitors C, and C2 is used to cover all the frequency range, the value of the transconductance must increase by a factor five which is carried out augmenting the Vtuning value. This rise in Vhming implies a variation in the transconductances linearity which is undesirable. This problem is solved using four pairs of capacitors to cover all the frequency range, the desired frequency value is delimited by the proper selection between one of the four different values of C, and C2, (this commutation of capacitors is achieved by the digital control). 1. Where, to achieve the oscillation, the input node must be connected to the reference voltage in Fig.4 (a). (a) bB vm - CM3 va L GM2 (b) (Cf - - - - Figure 4. (a) Passband Filter Stage, (b) PLL configuration. (c) Core of Filter OTAs; (d) Output stage of Filter OTAs, II-30 Table I shows the different tuning frequency ranges corresponding to the diverse values of the capacitors and the limiting values for the ranges ofgml and gmz transconductances and the tuning voltage. As can be seen there, an overlapping behueen the frequency channels has heen forced to ensure the availability of the whole range in case of errors caused by imperfections in the final design. Table 1: Tuning frequency ranges 126.6-218.6 0.66 295.1-501.3 Fig.5 shows the linearity of the OTA transconductance (expressed in percentage) which has been calculated performing a DC sweep to get the transconductance for different tuning parameters and then calculating the relative error respect to the transconductance value in the common mode. With this result it is checked that the error in the transconductance linearity is under 5.5% for a voltage range of 0.4V around the common mode. I. / h*Vd Figure 5. Gm's Linearity error (96). Another problem is associated with the output resistance; as shown in (I), the second term depends on the OTA's output resistance, which is undesirable because tuning degradations appear in the filter and in the voltage controlled oscillator due to the output resistance dependence on the frequency. To avoid this problem, a regulated folded cascode architecture, shown in Fig. 4 (d), has been selected for the output stage which provides an high and stable, in the tuning frequency range, output resistance. The amplifiers settle on the point of operation so the cascode transistors maintain their values and provide a high output resistance for the complete range of variation of the transconductance value. Another purpose of the amplifiers is to disconnect the nodes at their outputs and the gates of the cascode transistors, so the parasitic of these nodes is reduced, resulting in an increased output resistance value. The values of the transconductances are in the vicinity of I.5pAIV to keep the capacitor values small enough to be integrated. Due to this fact an output resistance larger than 30MClisneededinthedesignoftheOTA's. Fig. 6showsthatan output resistance larger than 8OMOhm is achieved within the frequency range of interest, that is, between 90 kHz and 350 kHz. This is enough to ensure that the tuning frequency is accurately modelled keeping only the first term in (1). One of the more important circuits ofthe LFM analog part is Figure 6. OTAs output resistance the PLL. The objective of the PLL, shown in Fig.4 (b), is to tune the filter and the voltage control oscillator (VCO) by changing the Vtuning voltage value. Tlis tuning is performed by comparing the reference frequency, obtained digitally by dividing the master clock frequency, with the frequency generated by the VCO. The reference frequency defines the channel selected to transmit information and this frequency is included in the protocol of the message which alerts the Slave Modules to change the transmission channel if the communication is detected to be defective. The RC filter block, shown in Fig.4 (h), senles the variation of Vtnning; since, to obtain a good precision in the tuning frequency it is necessary a very large value of the capacitor, this capacitor has been implemented off chip. The value for the passive filter has been selected to assure stability, senlinp time and loop bandwidth requirements. As it has been said before, the bandpass filterand the voltage controlled oscillator have the same frequency dependence when the tuning voltage is changed. Fig. 7 shows the tuning frequency of the filter and the spectrum obtained with the VCO for three different values of the tuning voltage. It is shown there how the frequency behaviour in bath cases is nearly the same, with a deviation that is always under 2 kHz between each other. ij ,_; j ,' .: i .. -: , Figure 7. Filter and VCO Frequency simulations Using the OTAs proposed before, the compensation of the VCO needed for the ASIC has been performed as illustrated in 11-3 1 Figure 8. (a) Compensation circuitry for the VCO, (b) System level structure of the AGC, (c) AGC schematic. Fig.8 (a). The degradation of the transconductance linearity generates start-up problems; to avoid these problems, an AGC circuit has been considered. Fig.8 (b) shows how the approach has been followed at a system level, then, in Fig.8 (c) it is shown the transistor level schematic used for the implementation. The rectifier circuit of Fig. 8 (b), provides a positive current, that induces small voltage variations in the input node of the comparator, thus provoking a shifting in its output voltage. This is how variations in the OTA currents are convetted into an adjustable tuning voltage to accomplish the negative feedback in the oscillator. Notice that due to the fact that the feedback in the oscillator depends on the transconductances of the feedback OTA's (gm3 and gm4) if gm) value is fixed (settling its control voltage by using an external reference), modifying the feedback coefficient is naturally performed by changing gmq value. As can be shown in fig.B(c), the rectifier in Fig.8 (b) has been implemented using two half-wave rectifiers, [9], and a differential input has been proposed. To have the comparator working properly the transistors MI and M2 in fig.B(c) have been located in the limit between cut-off and conduction. Finally, three inverters have been added to scale the voltage shifting in the output node of the comparator and to centre it around the desired value.Thus, the circuit's output is a voltage changing according to the variation of the OTA current in a range of0.93V to 0.99V. An important verification is to check that the PLL operates properly. To guarantee this, the PLL is simulated with different signals of the digital clock at its input. To know if the PLL is performing well it is required to verify that the frequency of the VCO is the same that the reference one. Fig. 9 shows the signals UP and DOWN obtained when the reference's frequency and the VCO frequency are compared in the digital phase detector, the tuning voltage and the comparator's output. 4. Conclusions The LFM of a mixed-signal ASIC to control the in-house communications with extemal control units has been presented. This module occupies an area of 2.5mm2, with a maximum power consumption of 9.3mW. The quality of the design has been settled by several experimental results that confirm the capabilities of the circuit. Adding, the functionality of the presented module to the misting HfM allows the creation of a cheap network to control in-house appliances. - .- " ..* ..- ".-,..I '* i "-- _. ,- - I -,./ -...-L---, Flgure 9. PLL's behaviour References A. Dum-Roy, "Networks for Homes" IEEE Specrrum. Vol. 16, pp. 26-33, December 1999. J.B. O'Nea Jr., "The residential power circuits as a communication medium", IEEE Trans. on Consumer Elecrronics, Vol. CE-36, No. 3, pp. 567-577, Aug. 1986. Wacks, K. P., "Utility load management using home automation", IEEE Trans. on Consumer Elecfronics, Vol. CE- 37,No.2,pp. 168-174,May 1991. J. E. Newbury. "Communications Services using the Low Power Distribution Network". IEEE Int. Con/ on Trends in Communicotions. Vol. 2, pp. 432-441,ZOOl R. Cappelletti and A. Baschirotto."A Power Line FSK Transceiver with reduced power consumption". IEEE Tronsaclions on Consumer Electronics, Vol. 47, No. 2, pp. 207-213, May 2001 A. Rodriguez-Vizquer et al., "A mixed-Signal CMOS MODEM ASIC for Data Transmission on the Low-Volt- age Power-Line with Sensitivity of 283kVrms at IOkbps", Pruc. U/ 261h European Solid Stale Circuit ConJ, Stockholm, Sweeden, Scptember 2000. B. Linares-Barranco, "Design of High frequency Tmnsconductance mode CMOS voltage controlled oscillators" Ph. D. dissettation, Univ. of Seville, Sevilla, Spain, May 1990. F. Krummenacher and N. Joehl, "A 4-MHz CMOS Continuous-Time filter with On-Chip Automatic Tuning" IEEE J. Solid-Store Circuits, Vol. 23, pp. 750.758, 1988. J. Ramirez-Angulo, "High frequency Low Voltage CMOS Diode" IEE Electronic Lerrers, Vol. 28, No. 3, pp 298-300, January 1992. 11-32