Compact low-power calibration mini-DACs for neural arrays with programmable weights

IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 1207 Compact Low-Power Calibration Mini-DACs for Neural Arrays With Programmable Weights Bernabé Linares-Barranco, Member, IEEE, Teresa Serrano-Gotarredona, Associate Member, IEEE, and Rafael Serrano-Gotarredona, Student Member, IEEE Abstract—Thispaperconsiderstheviabilityofcompactlow-res- olution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by afactor of10 (4.8% or4.4 bits),which makestheseDACs viablefor low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated throughexamples,toobtaincalibratedmini-DACsofagiventarget precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons. Index Terms—Analog design, calibration, current splitters, digital-to-analog converters, fuzzy circuits, neural networks, subthreshold, weak inversion. I. INTRODUCTION HARDWARE very large-scale integration (VLSI) implementations of neural and fuzzy systems usually have an array type structure: the same cell is repeated in a large two dimensional array for massive parallel processing, and some additional circuitry is available at the periphery for additional processing and/or out-of- chip communications. For optimum area efficiency it is desired to simplify the cell as much as possible at the expense of complicating the periphery. However, many times one would like to improve the precision in the cells even if this requires some extra cell area. One simple way to provide such precision would be using some very compact and low power mini digital-to-analog converters (mini-DACs). In this paper, we describe a way to exploit this alternative. We propose a mini-DAC scheme that not only provides a way to improve system precision through calibration, but also allows to have a precise programmable weight value at each cell. This is a many times required feature in massive arrays neural-type processing systems. The mini-DACs described in this paper are Manuscript received September 15, 2002. This work was supported in part by Spanish Grants TIC1999-0446-C02-02, TIC2000-0406-P4-05 (VICTOR), FIT-07000/2002/921 (ARQUIMEDES), TIC2002-10878-E,and EU Grant IST- 2001-34124 (CAVIAR). The authors are with the Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC), 41012 Sevilla, Spain (e-mail: [email protected]). Digital Object Identifier 10.1109/TNN.2003.816370 (a) (b) Fig. 1. Current splitter using (a) a resistor ladder or (b) an NMOS ladder. based on the linear MOS transistor current splitting technique [1] with some extra calibration circuitry to compensate for inter-DAC mismatch. This mini-DAC-based calibration technique differs substantially from floating gate tunneling techniques [2], [3]. These require the use of a high voltage node, which imposes very conservative layout rules [4], thus sacrificing compactness. As a comparison, the cells developed by Hasler et al. [3] consume an area comparable to the mini-DACs in this paper (after normalizing with respect to minimum feature sizes), although achieving better precision. Reliability is also an important issue in analog tunneling techniques (at least for standard CMOS), which is why those techniques are only used by a few very expert groups world-wide. The paper is structured as follows. Section II describes the conventional MOS ladder structure and it is found that it suffers from huge inter-DAC mismatch, although each individual DAC behaves reasonably well. Section III proposes an alternative bias arrangement that improves precision by a factor of ten, although the circuit is not practical. In Section IV, practical implementations, based on calibration, that yield similar 1045-9227/03$17.00 © 2003 IEEE 1208 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 Fig. 2. Current splitting principle used in such a way that output transistors operate as current sources. improvement factors are shown and verified. Section V establishes a parallel behavior between MOS ladders and resistor ladders, resulting in some interesting conclusions. Section VI discusses about achievable precision and layout compactness, and gives design examples for different precisions. Finally, Section VII describes an application example where an array of integrate-and-fire neurons is calibrated. II. VOLTAGE BIASED CURRENT DAC In1992,BultandGeelenintroducedasignificantcontribution in current mode MOS circuit design [1]. They discovered an inherentlylineartechniqueforsplittingcurrentsina similar way thatdothetraditionalresistorladders.Consider,forexample,the resistorladderinFig.1(a).Bydoingparallel-seriesgroupingsof resistorsitis easy to seethat the reference current seestwo resistors in parallel, so that . The same happens for current , so that . Similarly, ,,. Consequently, the resistor ladder in Fig. 1(a) provides five binary weighted currents . Fig. 1(b) shows the original current splitter proposed by Bult and Geelen using MOS transistors. The currents are split in the same way as by the resistor ladder: . Bult and Geelen showed that the currents are split in the same way independently of the bias conditions of the transistors. Transistors can be in weak or strong inversion, in saturation or ohmic region (obviously, they cannot be off), and the splitting principle still works the same way. Intuitively, one can understand the circuit in Fig. 1(b) by noting that two transistors in series are equivalent to one transistor. Also, two transistors in parallel are equivalent to one transistor, and they would split the current equally (independently of bias conditions). Bult and Geelen used the binary weighted current splitter of Fig. 1(b) to build a DAC [1]. In order to select the currents and combine them, it was necessary to provide a virtual ground node for the transistors with grounded sources, which implies the use of some high gain amplifier that consumes an important power and area. Consequently, this approach would not be very efficient for large arrays. Enz and Vittoz proposed an alternative way of using the current splitting technique which yields more efficient DACs [5]. ThisalternativeisshowninFig.2.Inthis circuit,ifthe drainsare Fig. 3. (Top) Measured output currents for the 50 fabricated DACs. (Bottom) Corresponding standard deviations. connected to sufficiently high voltage nodes, the output currents are . The drain voltages are not critical as long as they exceed a certain minimum so that the output transistors work as current sources, i.e., they are biased in saturation. We have fabricated a linear array of 50 DACs, like the 5-bit one in Fig. 2, with . It was fabricated in the LINARES-BARRANCO et al.: COMPACT LOW-POWER CALIBRATION 1209 Fig. 4. Measured DAC staircases for a few DAC samples. Fig. 5. (Top) DACs output currents normalized to their maximum value ( w =31 ). (Bottom) Standard deviation of the DAC normalized output currents. AMS 0.35- m CMOS process. All transistors of the 50 DACs have the gate voltage connected together and to the gate of tran- Fig. 6. Current biased DAC. (a) (b) Fig. 7. Digitally controlled MOS (digi-MOS). (a) Symbol. (b) Circuit schematic. sistor , which is biased by the reference current .We call this type of arrangement voltage biased DAC, because the gate voltage is fixed and equal for all DACs. The DAC 5-bit digital control word can be changed from to . For each DAC we measured the output current while sweeping from 0 to 31. Fig. 3 (top) shows the measured currents superimposed for all 50 DACs. As can be seen, there is an important mismatch between the different DACs. Specifically, for the maximum current ( ) the standard deviation is , which means that 99.7% of the samples are within an interval of (assuming a normal distribution). Fig. 3 (bottom) shows the corresponding inter-DAC error (1) in percent. To express this precision in bits, just note that (2) where is the equivalent number of bits. A variation interval of corresponds to a precision of . Obviously, this circuit cannot be used as a 5-bit DAC but rather as a 1-bit DAC. The reason for this misbehavior is the mismatch of the MOS transistors, which produces very high inter-DAC mismatch. In what follows we will present different alternatives for lowering this inter-DAC mismatch. These techniques can be used to calibrate arrays of DACs within a single chip, or even among different chips. 1210 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 (a) (b) Fig. 8. (a) Array of uncalibrated DACs of Fig. 2. (b) Calibrated version. III. CURRENT BIASED DAC Although the measurements in Fig. 3 reveal a very high inter-DAC mismatch, it is interesting to note that for each DAC we obtain a well-behaved stair-case. This is, for each DAC the stairs progress monotonically increasing, without showing eventual down steps, as is shown in Fig. 4 for a few samples. This phenomenon can be further visualized by plotting the data in Fig. 3, but where each DAC is normalized to its maximum value. This is shown in Fig. 5 (top). Here we can see that the maximum error is produced in the central part of the range. Fig. 5 (bottom) shows the deviation in percent as a function of the DAC digital control word . The maximum is obtained in the center for with . This corresponds to a precision in bits of . As we can see, by normalizingthe output current of the DACs with respect to their individual total current we can improve the mismatch from (1.1 bits) to (4.8 bits). One way of achieving in practice such normalization would be by forcing their total currents to be constant, as is shown in the circuit of Fig. 6. In this circuit the gate voltages of the MOS transistors in each DAC is self-adjusted to set the maximum current constant and equal to the reference current .We call this bias arrangement the current biased DAC. IV. CALIBRATED DAC The problem with the circuit in Fig. 6 is that all currents need to be added permanently and be forced to add . Consequently, we cannot select/deselect any of them arbitrarily to form any combination of them, i.e., to form a DAC. One way to overcome this problem and to force the sum of all currents to be constant is through calibration. Consider the part of the circuit in Fig. 2 comprised by broken lines. Note that this circuit behaves equivalently to a MOS transistor of size whose source is connected to ground and whose Drain to node , but from which we are taking just a fraction of its drain current. This fraction is controlled digitally by control word . Let us use the symbol in Fig. 7(a) to represent this circuit, shown in Fig. 7(b), and let us call it the digitally controlled MOS or digi- MOS. Using this symbolconvention,thecircuitinFig. 2canberedrawnas shown in Fig. 8(a), where we represent an array of DACs (instead of just one as in Fig. 2). This circuit (a voltage biased DAC array) presented an important mismatch behavior. In order to force the output current to be constant for (the maximum value), we can use the circuit in Fig. 8(b) where global transistor has been substituted by many digi-MOS, one for each cell. For this circuit is used to set (calibrate) , while is maximum. Decreasing increases the gain of the mirror. Consequently, all values of the DACs need to be set to the original uncalibrated maximum value. The finalerrorat willbeoftheorderoftheleastsignificantbitof the DAC (in this case ). We used this approach with our linear array of 50 DACs (or digi-MOS), by grouping them two by two, and using the first one for calibration through . This way, we end up with 25 calibrated DACs. Fig. 9 (top) shows the output currents of these 25 calibrated DACs as a function of the digital control word . Fig. 9 (bottom) shows the precision obtained with this approach. As can be seen, a maximum error of is obtained for , which is equivalent to . At this point it is interesting to have a look at the resulting 25 calibration words . It turns out that the required calibration words range from a maximum of (no calibration) to a minimum of . Consequently, the two most significant bits are not being used in the calibrations (for this particular mismatch distribution). Note that the available precision without calibration was 1.1 bit. Consequently, it is reasonable to expect that at least the most significant calibration bit might not be required. On the other hand, it would be nice to take advantage of this unused bit to further improve the calibration: note that we have been able to calibrate to 3.8 bits instead of the ideal 4.8 limit observed in Section III. The circuit in Fig. 10 intends to pursue this objective. Here, the maximum correction is instead of , but in steps of instead of . Fig. 11 shows the results for this calibration strategy. Fig. 11 (top) shows the absolute output currents in terms of the digital control word for all 25 calibrated DACs, while Fig. 11 (bottom) shows the resulting standard deviations in percent. The maximum standard deviation is obtained for , which is equivalent to . In this situation the calibration words range from a minimum of (no calibration) to a maximum of , hence using all five control bits (for this particular mismatch distribution). V. COMPARISON WITH RESISTOR LADDERS Although resistor ladders and MOS ladders are not exactly the same, their behavior in current splitting is identical [1]. Regarding their behavior with respect to mismatch, they are qualitativelyandquantitativelyverysimilar.Thelinear natureof the resistors allows us, on the other hand, to study its mismatch LINARES-BARRANCO et al.: COMPACT LOW-POWER CALIBRATION 1211 Fig. 9. Measured results for the calibrated DAC. (top) Output current versus digital control word w and (bottom) resulting standard deviations. Fig. 10. Alternative calibration arrangement for improved precision. behavior using relatively simple mathematical models. In order to compare our MOS measurements to eventual resistor ladder numerical (MATLAB) simulations, we need to characterize the standard deviation of our individual MOS devices. In our MOS ladder measurements, we have access only to the output currents [see Figs. 1(b) and 2 or Fig. 6]. Note that the mismatch of these currents is a function of the mismatch Fig. 11. Measurement results for the calibration arrangement of Fig. 10. (Top) Output current versus digital control word w . (Bottom) Resulting standard deviations. Fig. 12. Measured current at transistor M for the 50 DACs over a distance of 2.6 mm. 1212 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 Fig. 13. Current mismatch measurements (in percent) for arrays of transistors of 30 different sizes, as a function of their nominal operation currents. These measurements correspond to a different 0.35-  m CMOS process. of all MOS transistors in the circuit, except for current and transistor in the voltage biased configuration. For this configuration the mismatch at depends only on the mismatch of transistor of size . Consequently, the standard deviation measured for the currents is equal to the standard deviation of the drain- to-source current of one transistor . By looking at the output current for we are observing the current produced by transistors only. Fig. 12 shows this current for all 50 fabricated DACs as a function of DAC position. The overall standard deviation for this current is equal to . The 50 DACs are arranged in a linear array of total length equal to 2.6 mm. As can be seen in Fig. 12, there is a gradient component plus a random component. Fitting the measured data to a third-order polynomial yields the continuous curve shown in Fig. 12. Subtracting this curve from the measured data results in the pure random component. The standard deviation for this pure random component is . Let us assume that this mismatch is approximately the same for all transistors in the ladder, independently of their operating currents.This assumptionisapproximatelytrue,ifalltransistors operate within subthreshold [6], [7]. Fig. 13 shows measured standard deviations of the drain-to-source currents for arrays of NMOS transistors of 30 different sizes: m, m, by extending a systematic procedure published elsewhere [8] to subthreshold region. These measurements correspond to a different 0.35- m CMOS process than the one used for the fabricated mini-DACs. Horizontal axes are nominal currents and vertical axes are standard deviations at the drain-to-source currents in percent. For high currents, the transistors operate in strong inversion and reaches minimum values. For lower currents tend to stay at maximum current independent values. By looking at the subframe m and curve m (crosses) for nominal current 1 A, the measured current mismatch standard deviation was actually very close to 3.8% (the gradient-less mismatch observed for the data in Fig. 12). Let us now use this value as the standard deviation contributed by each resistor of the current biased resistor ladder shown in Fig. 14.1Resistors of value are implemented with two resistors in series. Fig. 15 (top) shows the MATLAB simulated currents obtained statistically for all digital combinations of currents { } in terms of the digital control word . Fig. 15 (bottom) shows the corresponding 1For MOS ladders, since the current decreases for each branch, transistor mismatch increases slightly, as can be seen in Fig. 13. However, for weak inversion the mismatch tends to stabilize as current decreases. For example, for W = L =5  m,  changes from about 3% for 1  A to about 5% for 1 nA (three decades). Consequently, it is reasonable to assume  approximately constant for all branches because the maximum current ratio is 16. LINARES-BARRANCO et al.: COMPACT LOW-POWER CALIBRATION 1213 Fig. 14. Current biased resistor ladder. Fig. 15. Current biased resistor DAC numerical MATLAB results. (top) Output currents. (bottom) Resulting standard deviations. standard deviation in percent. Comparing Fig. 15 for resistors with Fig. 5 for MOS transistors, we can see that both ladder structures provide similar DAC precision. Consequently, we have reasons to believe that the mismatch behavior of resistor ladders and MOS ladders might be similar. Fig. 16. Current biased resistor DAC effective precisions as function of resistor mismatch  ( R ) and DAC resolution, expressed (top) as max(6  ( I )) and (bottom) as effective bits. Taking advantage of this conjecture, let us now study, for the resistor current biased DAC structure of Fig. 14, how the DAC precision (3) depends on the standard deviation of the individual resistors. The results of this study are shown in Fig. 16 (top), where has been swept from 0.1% to 10%. Each line corresponds to a different DAC resolution (i.e, the number of output branches), which has been changed from three to nine bits. As can be seen, the following relationship: (4) is satisfied approximately for the whole range, independently of DAC resolution. Consequently, we can state that “for a current biasedresistor DAC the worst-case output current standard 1214 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 deviation is approximately 1/3 that of its individual resistor components .” Using (2), we can express the DAC precision in bits as well (5) which is shown in Fig. 16 (bottom). Since we have reasons to believe there is a similar mismatch behavior between resistor ladders and MOS ladders, Fig. 16 might be extensible to MOS current biased DACs as well. VI. ACHIEVABLE PRECISION AND LAYOUT FOR MOS LOW-POWER MINI-DACS Fig. 16 and (5) provide hints on how the effective precision of currentbiasedDACs depend on the mismatchof their individual components. On the other hand, Fig. 13 showed the mismatch of individual MOS devices as functions of current operating level and transistor sizes. Combining both Figs. 13 and 16, one can select the optimum transistor size for a given DAC precision to achieve. For example, Fig. 13 reveals that for and currents between 1 and the current mismatch standard deviation is between 2.5% and 5%. Using this in Fig. 16 (bottom) yields an effective DAC precision around 4 bits, as we obtained experimentally in Sections III and IV. If we would need a 6-bit DAC, Fig. 16 (bottom) reveals that we need components with a mismatch of about . From Fig. 13 we can see that the transistor size achieving with minimum current is , at 6 . If on the other hand we need an 8-bit DAC, then according to Fig. 16 (bottom) we require components with a mismatch of about 0.22%. Then looking at Fig. 13 we can see that for transistors of size m and m operating at or above 1 mA we would be able to obtain an 8-bit DAC. In the ladder structures seen so far, one can see that the mismatch of the output currents depends on the mismatch of all devices in the structure, except for current and the transistors in the first branch of the ladder. Consequently, there will be an importantcorrelationin the resulting mismatches. Thismightbe oneofthereasonswhythestandarddeviationoftheladderstructure improves a factor of three that of the individual devices. If this is the case, building the ladder structure as shown in Fig. 17 would improve the overall precision, since now all output currents will be correlated. In order to verify this postulate we have used our 5-bit DACs data to emulate 4-bit calibrated DACs. One of them using currents { } as outputs, and the other using currents { } as outputs. It is found that there is a slight improvement in precision (from 5.2% to 4.8%), but not very significant: about a 10% of improvement only. The layout for these DACs can be made very compact. As an illustrative example, Fig. 18 shows the layout for a MOS ladder structure corresponding to 5-bit resolution, including the selection switches. The unit transistor size is , and the resulting total area is 22 18 . This layout correspondstothedesign rulesfortheAMS0.35- 3-metal,double poly design rules. One calibrated DAC would use two of these structures, as was shown in Fig. 8(b) or Fig. 10. Fig. 17. Alternative ladder arrangementto makethe mismatch of allthe output currents to be intercorrelated. Fig.18. Examplelayoutof a5-bitNMOSmini-DACladderstructurefor W = L =3  m . Size is 22  m 2 18  m . Fig. 19. Circuit schematic of current-driven I&F neuron. VII. EXAMPLE APPLICATION TO NEURAL SYSTEMS The calibrated mini-DACs described so far havepotential application in many low-moderate precision massive array VLSI structures, such as neural and fuzzy systems. In our particular case, we intend to exploit them in arrays of integrate-and-fire (I&F) neurons [9]. Fig. 19 shows the circuit of an I&F neuron that transforms input current into an output frequency . Current could be produced by photo detectors [10] or analog current-mode signal processing circuits [11]. The dependence between and is fairly linear, although the slope suffers from important mismatch between neurons and also between different chips. Using the mismatch characterization results LINARES-BARRANCO et al.: COMPACT LOW-POWER CALIBRATION 1215 Fig. 20. Monte Carlo simulation results for an array of I&F neurons. (Top) Neurons frequency versus weight for uncalibrated neurons. (Bottom) Corresponding standard deviation in percent. shown in Fig. 13 we have performed Monte Carlo simulations to estimate the variations in the slopes . These results are shown in Fig. 20 (top). Current is set to be proportional to a , such that . Fig. 20 (bottom) shows the corresponding standard deviation in percent. The maximum value is , which corresponds to a precision of 2.02 bits. By introducing a mini-DAC calibration scheme, the versus curves change to those shown in Fig. 21 (top), with the mismatch standard deviation depicted in Fig. 21 (bottom). The maximum value is ,or equivalently, 4.82 bits. VIII. CONCLUSION In this paper, we have studied, and validated with experimentalresults,thepossibilityofexploitingsmallsizelow-power low-resolution DACs for VLSIneuralmassivearrays.TheMOS structure studied is a ladder structure, which scales linearly with the number of resolution bits. Because of low-power requirements, transistors are biased in weak inversion, which yields important mismatch behavior. A calibration scheme is proposed andverifiedexperimentallyforcompensatingmismatchandimprove precision by a factor of ten. The MOS ladder structure has been compared against the conventional resistor ladder structure, and it is found that the mismatch behavior is very similar. Fig. 21. Monte Carlo simulation results for an array of I&F neurons. (Top) Neurons frequency versus weight for calibrated neurons. (Bottom) Corresponding standard deviation in percent. It is found that the standard deviation of the ladder structure is about one third of that of the single devices used. It is shown how to use the provided experimental data to design calibration mini-DACs for a target precision. As an application, the use of mini-DACs to calibrate an array of I&F neurons is described. REFERENCES [1] K. Bult and J. G. M. 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