Some design trade-offs for large CNN chips using small-size transistors

1997 IEEE International Symposium on Circuits and Systems, June 9-12,1997, Hong Kong Some Design Trade-offs for Large CNN Transis tors Chips using Small - Size A. Rodriguez-Vhzquez, G. LiAhn, R. Dominguez-Castro, J.L. Huertas and S. Espejo Instituto de Microelectrdnica de Sevilla-Universidad de Sevilla Edificio CICA, C/Tarfia s/n, 41012-Sevilla, SPAIN FAX:: 34 5 4231832; Phone:: 34 5 4239923 email: angel @cnm.us.es ABSTRACT Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in severe accuracy degradation. Also, because of the down scaling of supply voltages with the technology feature size, noise and distortion produce large additional errors in submicron technologies. To reduce the influence of all these errors requires to properly choose the interconnection synapse circuitry, to perform intensive parametric optimization, and to use large enough transistor sizes. Consequently, the cell density and the operation speed cannot be scaled up to their limits because they have to be traded-off for accuracy. This trade-off is illustrated by the evaluation of the composed Power/ (Precision x Speed) figure, which results independent on the sizes. In addition to the parametric errors, catastrophic faults impose a limit on the maximum chip size for given yield, and open the issues of fast goho-go testing, fault-driven reconfiguration and/or multi-chip architectures. 1. Introduction The potentials of CNNs and other vision-oriented systems are only fully realized chips [1][2]. Basic system-level targets in the design of these chips are to increase the cell density (number of processing cells per unit area), and the cell operation speed. As the technology scales down to submicron all the lateral dimensions decrease by the scaling factor A, and the vertical dimensions scale as Awa, where a is typically around 1/2 [3]. Consequently, the MOS gate capacitance per unit area increases as A', and the small-signal transconductance per unit channel-ratio increases also as ha for fixed bias. As a result one could ideally expect, cell density = h2 time constant = a-2 (1) with constant current and, hence, with no penalty on the power consumption, provided that the voltage ranges remain constants *. However, the actual scaling scenario is more pessimistic because of the increased influence of second-order phenomena on small-size MOSTs. Some recently reported submicron CNN CMOS chips [5][6] feature smaller cell density and operation speed, and larger power consumption, than 1. This corresponds to the constant voltage (CV) scaling law[3] -largely used because it keeps the digital noise margin [4]. expected from these formulae. Particularly, [6] obtains 27.5cells/mm2, a time constant of 0.4ps, and 7bit analog accuracy in a 0.8pm 5V technology. Obviously, there is still room to improve these chips through structural and parametric optimization. However, if precision is a design goal, the cell density and operation speed will be inevitably constrained by mismatch and noise. And these constraints are expected to become harder as the signal dynamic ranges decrease because of the down scaling of supply voltages in deep submicron technologies. Out of the circuitry of a CNN cell, the interconnection synapse consume much of the area and is the critical part in terms of precision and speed. This paper addresses the influence of mnsmatch and noise on the operation of the strong-inversion MOST synapse, and outlines some practical trade-offs and issues induced by these errors. 2. MOST Synapse We will describe the non-ideal synapsis behavior by, 2 2 (w-W,,) (x-Xu,) +D x +D w w2 (2) x2 2 2 3 3 +D xw+D xw +D x +D w +...= kwx x2w xwz 13 w3 where w and x are the weight and input signals. In the ideal case, k is an error-free coefficient; all the remaining coefficients above are null in this ideal scenario. Practical synapse circuits may have offset, error gain and distortion even with ideal MOSTs. The simplest synapse consist of one transistor (Fig. l), ohmic 13) \- I x> sat. y=E(w-V,) 2 +p(w-V,)x{l+ 1 2 2(W-V,) where p may include the effect of mobility degradation [7]. Their large non-linearities result into small values of the maximum input and weight signals, x,,,,, and wmm, thus decreasing the maximum output signal ymm and increasing the influence of mismatch and noise. Linearization is needed to enhance these ranges in practical circuits. 2. In [6], 45% of the area is occupied by the synapse, 8% is for an integrator and a non-linear block, 15% is devoted to analog memories, 25% to the digital and control circuitry, and 7% to the optical interface. 0-7803-3583-XI97 $10.00 01997 IEEE 741 ;! (a) '- ' (b) w+x- Fig. 2 Single MOST S\napse (a) ohmic region. (h) sarrrrurion region Fig. 2 shows two common linearized synapse: Fig. 2(a) [8] operates in ohmic region, while Fig. 2(b) (a MOST version of the Gilbert multiplier [9]) operates in saturation. Assuming matched transistors and neglecting mobility degradation both circuits obtain null second-order nonlinear errors and zero offset, and, hence, qualify a priori for practical CNN chips. W+ - - . (b) Fig. 1 Linearized ohmic-MOST and saturation-MOST sxnapse where signal ranges are determined from linearity issues. Fig. 3(a) illustrates the dependency of this error with the channel area WL (log. scale) and the aspect ratio WIL (log. scale), for (x-VT),,,=lV in a 0.8pm technology. Each curve corresponds to a different percentage of error (%). With these data, to obtain around 7 equivalent-bits requires a channel area of about 50pm2 for square transistors and larger for rectangular transistors. On the other hand, if the signal range is decreased by a-l (a > l), the area might has to be increased by up to a2 to keep the precision. Similar qualitative relations are observed for Fig. l(b) and the linearized synapse of Fig. 2. 2- ,0.5 1.8. 1.6- - I - 3. Errors due to Matching and Noise Mismatch The precision of CNN analog synapses, and any other analog circuit, is constrained by mismatch [lo]. Its formulation as a function of the sizes is cornerstone for parametric yield optimization and design centering [ 111. These models show that the variance of the fluctuations in the threshold voltage (V,) and the transconductance factor (p) show an inverse dependence with transistor sizes, which for small-size transistors can be approximated as [101[121[131 4> 2 2 2 222 2 o A Bp Cp 0 2 =-+T+- AV, Bv cv, --P=P+-+- (4) v, wL w2L WL2 p2 wL w2L WL2 The coefficients are technology-dependent and are reasonably expected to become smaller as the technology scales down. However, despite this reduction, mismatch will always limit the scaling of silicon area for given accuracy. Mismatch errors are smaller for ohmic than for saturation region; it will be illustrated through the comparison of the two synapse of Fig. 2, in Section 5. The current error for the single MOST in ohmic region is, 3. It does not preclude to obtain INL values smaller than 0.4% and THD values below 0.2% for up to 2V input range in a 5V technology [6]. 4. This model is somewhat controversial. Much more modelling effort is required to accurately capture the mismatch of small-size transistors. Channel Aspecf Rafio (Log ) Channel A~peci Ratio (Log.) Fig. 3 Full-Scale Percentage Errors (a)Mismatch, (hi Norse Noise The noise-induced errors are due to the thermal and the flicker fluctuations of the channel current [7]. Since the latter depends inversely on the channel area, it dominates across a large frequency band for small-size transistors. However, the flicker component becomes less signicant for non-minimum area transistors, as those required to keep the accuracy, and the thermal contribution cannot be discarded. The equivalent noise current is [7][13], where h and A, vary between 1 and 2, and Gch = p ( VGS - VT) in ohmic and 213 of this quantity in saturation. The errors in the former region are given by, Fig. 3(b) shows the integrated noise error as a function of WL and WIL; the regions dominated by the thermal and the flicker contributions are clearly discernible. As for Fig. 3(a), we have assumed (x-V~)~~~=W,~~= 1V in a 0.8pm technology. The noise has been integrated from 1mHz to 1MHz. For these data, the noise error is much smaller than the mismatch error - a positive consequence of the relatively large time constant needed to guarantee correct dynamic operation of the system '. Assuming square transistors of 50p.m2 and keeping the inte- 5. The processing advantages of CNNs are not tied to the speed of the cells, but to the parallel operation of the system. 742 gration band, mismatch and noise become comparable only for (X-V~),,,,~=W,,,,~ <400mV. Because these tiny dynamic ranges will only appear for about 2.5V supply (for the linearized synapsis of Fig. 2(a) in the 0.8pm technology) noise can be expected to become a serious drawback for deep submicron technologies. Otherwise, mismatch can be expected to constitute the major problem for accuracy. 4. Mismatch-Induced Trade-offs Let us assume for siniplicity that the border effects are negligible in (4); i.e. that Bvr = C = Bp = Cp = 0. The following expressions are found for the performance aspects related to the ohmic region synapse, v, where Prec. stands for precision and we assume equal range s,,, for x and w. The top expressions highlight a constraint on the cell density, / (9) If precision must be kept constant, the density might not be scaled up with the technology resolution. Quite on the contrary, because of the inverse dependency with smax, and the reduction of smaX in deep submicron (due to supply voltage lowering) the density might even decrease as the feature size decreases. The only way to increase the cell density without degrading the precision is by decreasing the technology-dependent coefficients of the fluctuations in V, and p. 2 A similar constraint can be found on the speed, where we have assumed W=L. This equation highlights also a trade-off between the speed and the cell density. Similar trade-offs are found among the other performance aspects. In general, they cannot be all improved simultaneously. As the sizes change, each index changes in a different manner so that the following composed figure is found, -2 22 Power x Prec. x Speed-' = pC,,( smaxAp + AvT2) (1 1) Because the vertical dimensions scale as (l<a<2), this figure can be expected to scale up as ha; further improvement can be expected due to the reduction of AvT with tax. 5. Mismatch Errors in the Linearized Synapse Because of the trade-offs above, proper design of the CNN synapse requires parametric optimization. Structural 2 7 Channel Aspect Ratm Channel Asped Ratm Fig. 4 Mismatch Errors in the Linearized Synapse: (a) Fig.Z(a); (b) Fig.Z(b). optimization is also required to improve the overall circuit performance. Structural optimization comprise two different levels: model optimization [ 141 and topology selection. The importance of the latter is illustrated below by comparing the two linearized synapse of Fig. 2. Both synapse have zero offset and second-order distortion under nominal conditions. However, mismatch render these errors different from zero. The first six rows in Table 1 shows simplified expressions for these errors under the design conditions in the last three rows. From this table, we conclude that Fig. 2(b) requires larger area occupation and/or power consumption to obtain the same levels of accuracy than Fig. 2(a). Fig. 4 illustrates this by showing the mismatch-induced errors for the two synapse under the assumption of equal power consumption and area occupation. Differences in precision are dramatic, supporting our statement about the necessity of structural optimization for CNN design. For submicron design the capability of the different synapse to operate with low-voltage supply has also to be explored. To this regard, Fig. 2(a) exhibit also excellent performance. In the 0.8pm technology it obtains about 500mV signal range for 0.5% precision (including distortion) with 3.3V supply, and about 360mV for the same precision with 2.2V supply. Above this voltage level, the influence of noise is less significant than that of mismatch. Below this level, noise beclomes also important and forces using larger transistors to keep the precision. 6. Testing Issues Although next generation technologies will have lower defect densities, the envisaged complexity levels of CNN chips will make test and yield-oriented design capital issues. Because the careful electrical and physical design of the cell, defects translated into non-catastrophic failures are expected to have an effect mainly on the interconnects. Then, techniques for fast verification of wiring may deserve attention rather than a system-level test methodology - reserved as the final test step for those chips passing the previous one. Concerning spot defects causing catastrophic failures, they can affect to both the active and the interconnection parts. Probably these defects will dominate, provided that the design has been optimized on the basis of a thorough formulation of parametric errors, and a second test step has to be devoted to detect them. It would be interesting to 743 develop procedures that can be simultaneously applied to all the cells and collectively interpreted, in order to speed-up the whole production test. In any case, for an industrial application of CNN chips, it might be pertinent to accompany the test procedure with reconfiguration schemes. To that purpose, the cells have to be modified to accommodate some kind of rerouting allowing to disconnect those that are not working correctly. As an alternative, or a complement, multi-chip configurations have to be devised as a way to conciliate large cell counts with large production yield. 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