Compact CMOS active quenching/recharge circuit for SPAD arrays

Compact CMOS active quenching/recharge circuit for SPAD arrays Ion Vornicu* ,† , Ricardo Carmona-Galán, Belén Pérez-Verdú and Ángel Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla-CNM (CSIC-Universidad de Sevilla), Avenida Americo Vespucio s/n, Parque Científico y Tecnológico de la Cartuja, 41092 Sevilla, Spain SUMMARY Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540nm wavelength is about 5% at an excess voltage of 900mV. The break-down voltage is 10.3V. A dark count rate of 19kHz is measured at room temperature. Worst case post-layout simulations show a 117ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500ns. The pulse-width jitter is below 1.8ns when dead time is set to 40ns. Copyright © 2015 John Wiley & Sons, Ltd. Received 28 October 2014; Revised 18 May 2015; Accepted 1 June 2015 KEY WORDS: active quenching/recharge (AQR) circuit; tunable dead time; single-photon avalanche diode (SPAD); Geiger mode; afterpulsing reduction 1. INTRODUCTION Single-photon avalanche diodes (SPAD) are capable of detecting very weak light signals [1]. Owing to their ability of responding to single photon events, they are employed in applications like fluorescencelifetime imaging microscopy [2] and positron emission tomography (PET) [3]. In the first case, a high temporal resolution is crucial in the visualization of the exponential decay of fluorescence in the sample. Time-correlated single-photon counting is employed to realize a histogram of detection times in order to accurately depict this decay [4]. In the case of PET-time of flight imaging, better time resolution is required to reduce the uncertainty of positioning the positron annihilation along the line of response while the detector spatial resolution counts in the accurate evaluation of the depth of interaction. Both parameters are crucial to enhance the quality of PET images [5]. Usually, SPADs are organized into arrays in order to perform some type of 2D or 3D imaging of very low light scenes. *Correspondence to: I. Vornicu, Instituto de Microelectrónica de Sevilla-CNM (CSIC-Universidad de Sevilla) Avenida Americo Vespucio s/n, Parque Científico y Tecnológico de la Cartuja, 41092 Sevilla, Spain. † E-mail: [email protected] Copyright © 2015 John Wiley & Sons, Ltd. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2016; 44:917–928 Published online 7 July 2015 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2113 To implement SPAD arrays of practical size, the basic detector cell must be compact. This cell is composed of the avalanche photodiode, the quenching/recharge circuit, and the readout circuitry. Any reduction of the area occupation and power consumption of the basic detector cell results in a larger number of pixels in the same chip, which means larger image size and resolution. Also, reducing the area of the circuits around the SPAD enhances the fill factor, that is, the amount of area of the basic detector cell that is sensitive to the incoming photons. Different quenching/recharge techniques have been reported in literature [6]. The simplest employs just a ballast resistor [7]—known as a passive quenching circuit. The major drawbacks of this approach are (i) the lack of a well-defined quenching time (as it is statistically defined by the avalanche process), (ii) a very slow recharge, and (iii) the lack of control on afterpulsing. In order to speed-up the recharge phase and to introduce afterpulsing countermeasures, like an adjustable hold-off time, active quenching circuits (AQCs) were introduced [8]. In this approach, the avalanche onset is detected, and additional circuitry acts on the diode bias, actually lowering it below breakdown. Quenching time does not depend now on the statistical nature of the avalanche, but on the delay of the reacting circuit. Also, the duration of the voltage pulses can be adjusted, as well as the hold-off time. One of the disadvantages of this approach is the complexity of the circuit, in terms of number of transistors and feedback loops, and consequently the larger area occupation. Regarding the avalanche detection mechanism, the circuit reported in [8] contains an integrated large ballast resistor that biases the sensing node to a voltage that situates the SPAD above the breakdown voltage. The triggering of the avalanche starts a passive-quenching action, rapidly followed by an active-quenching action accelerated by a positive feedback loop. After a pulse of an adjustable duration, a recharge transistor brings the SPAD back to the quiescent condition. The same architecture is implemented in [9] in which timing control is implemented with two monostables, based on a current-starved inverter. One of the monostables is employed for adjusting the quenching time, while the other determines the hold-off. A similar circuit [10] employs a high-speed voltage comparator in order to detect the drop at the ballast resistor. A different circuit [11] eliminates the ballast resistor and employs a variable load implemented by a metal-oxide-semiconductor (MOS) transistor. Hold-off time is controlled by the RC load of the NMOS inverter employed to detect the avalanche. When a MOS transistor is employed for passive quenching purposes, usually it must be a high-voltage (HV) device because it needs to support the complete swing of the avalanche photodiode (APD). A HV PMOS transistor for quenching Geiger-mode APDs has been reported in [12, 13], built in a 0.18μm-1.8V CMOS process. A lightly doped deep triple well module is employed. An additional proposal is a circuit that employs a monostable whose delay is fixed by design [14]. The latest developments report a miniature actively recharged, passively quenched single-photon detector [15]. The design is implemented in a HV-CMOS 0.18μm technology and employs an innovative dual-threshold quenching and recharge scheme. The dead time is defined by discharging the parasitic capacitance of the sensing node. The outstanding low-noise features of this process, which has extremely low-defect density, are used to obtain a single-photon detector with very low dark-count rate and free of afterpulsing effects. The circuit utilizes 16 transistors and consumes 15μA of quiescent current. In our proposal integrated in a standard UMC 0.18 μm CMOS technology, we make use of a positive feedback loop to speed-up quenching without using a ballast resistor. Thus, both afterpulsing probability and power consumption decrease by limiting the magnitude and the duration of the avalanche [11]. Several design strategies are combined to be able to operate a SPAD detector in harsh conditions such as high dark-count rate (DCR). Small area and power consumption make the proposed AQC a good candidate to build large array. The detector ensemble is aimed for ToF and photon counting. The ensemble of SPAD detector and AQC is fully integrated. Instead of using an RC delay circuit for the single-shot generator [16], we have implemented the control of the holdoff time by a current-starved inverter. By reducing the delay of the quenching action, which is a principle that is employed even with the finest technologies [17], afterpulsing probability is certainly reduced. Afterpulsing is theoretically smaller than the one that can be observed in passively quenched SPADs, because of the reduction in the tail of the avalanche current and the introduction of a dead time where the SPAD is off [11, 18]. Moreover, actively quenched SPADs can allow 918 I. VORNICU ET AL. Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta higher count rates, as high as 185MHz [19] for high illumination conditions. A high dynamic range as 139dB is therefore reachable by using active quenching. 2. ACTIVE QUENCHING AND RECHARGE CIRCUIT The active quenching and recharge circuit has been tailored to requirements posed by the use of CMOS standard technologies. SPAD detectors in these technologies exhibit larger DCR and lower PDE figures than customized technologies [15] and motivate the search for control circuits capable of dealing with these limitations and to mitigate as much as possible afterpulsing effects. Besides this, the proposed circuitry is intended to minimize power consumption and area and to operate in time-of-flight and photon counting scenarios when configured into an array structure. Results in this paper confirm these advantages as compared with previous AQCs. The AQC presented here (Figure 1(a)) operates in two different phases: quenching and recharge. Prior to the avalanche and the quenching phase, the complete circuit is reset by a transition to 0 of the reset signal, RST. If V A was not already 0, this negative pulse in RST makes V reset high. As V reset drives the gate of M4, V A is pulled down to 0. Therefore, prior to any avalanche being triggered, V A is at its lowest possible value. The excess voltage, V e , that is, the extent to which the diode is pushed beyond breakdown voltage V BD , is given by VSPADþVA¼VBD þVe(1) thus, operation starts with the diode biased beyond V BD to an extent indicated by V SPAD+ . This state is maintained as long as no avalanche is triggered. A low V A makes V sense high and, because V sense drives the gate of n-type transistor M2, node V A is pulled down to ground, as long as no significant amount of current passes through the SPAD. In parallel with that, V sense also drives the gate of p-type transistor M3. It will have later the mission of pulling up node V A , but right now it is off, letting V A at ground level. Given that the circuit has been at rest for enough time, V 2 is high, RST is up again, and therefore M4 is off. When the avalanche starts, V A rises because of the avalanche current building a voltage across M1, which is connected as a diode. Then two positive feedback mechanisms are provided to ensure the extinction of the avalanche. First, rising V A makes V sense to go down to 0. As V sense drives the gate of n-type transistor M2, its pull is stopped, therefore allowing V A to grow higher, thus reducing the excess voltage. At the same time, V sense drives the gate of M3, which is p-type; therefore, V sense going down to 0 allows M3 to pull up node V A , another positive feedback action, until VA¼VSPADþVBD (2) At this point, V e =0, and the avalanche is quenched. During this phase, M4 has been kept off. Because of the delay introduced by the current starved inverted M5-M6-M7 and Inv 3 , the changes in V sense are not noticed at V 2 until later on. In fact, it is the bias voltage V hold_off that determined the magnitude of this delay—apart from the delays introduced by Inv 3 and Nand 1 —resulting in a first approximation as follows: TDEAD ≈CM8ln2 μpCox WM5 LM5 VDD Vhold_off VTH;M5     (3) where c M8 ,μ p ,c ox ,W M5 ,L M5 , and V TH,M5 are the equivalent capacitance of the transistor M8, holes mobility, gate oxide capacitance, width, length, and threshold voltage of the transistor M5. Once the change in V sense , which went to 0 because of the voltage built up at V A by the avalanche current, is propagated to V 2 ,V reset rises. This allows M4 to bring node V A back to zero, V sense up again, M2 turns on, and M3 turns off. After a delay of the magnitude already described, V 2 goes up and V reset COMPACT CMOS AQR CIRCUIT FOR SPAD ARRAYS 919 Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta goes back to zero, leaving the circuit ready for the detection of a new avalanche. This circuit acts as a monostable; a rising edge in V A is seen as a pulse in V SPAD of a controlled duration. The benefits of this scheme are several. In the first place, quenching of the avalanche occurs at a much higher pace. This limits the maximum current, thus reducing power consumption and the probability of carriers getting trapped and triggering afterpulses later. Concerning the recharge phase, active recharge is much faster than passive recharge, usually through the same large ballast resistor employed for quenching. In addition to this, duration of the output pulse is relatively stable, and controlled by the user. This allows for a fine control of the dead-time and its influence in reducing pile-up and afterpulsing. Concerning the sizing of the transistors, M1 and M2 need to be large enough to sense small current peaks. The sizing of the transistors in this design is summarized in Table I. Keeping the avalanche current as small as possible avoids unwanted effects like the increase of afterpulsing, overheating, and crosstalk. Post-layout simulations have been performed using an accurate model of the SPAD (a) (b) Figure 1. Single-photon avalanche diode (SPAD) and active quenching circuits: (a) schematic and (b) layout. 920 I. VORNICU ET AL. Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta that merges a statistical model [20] with the device characteristic [21] (Figure 2). The hold-off time is dynamically switched between 3.3ns and 30ns. Owing to its simplicity, this scheme can be easily incorporated to every pixel in a SPAD sensor array. We have included this AQC in a prototype chip targeted for time-of-flight measurements and focal-plane calculation of light-spot statistics. The sensor has been fabricated in a standard 0.18μm CMOS technology. It does not support the HV option. Also it is not compliant with low-noise design which requires very low-defect density by high-quality material and low-doped epilayer [15]. The transistors M1, M3, and M4 and inverter Inv 1 are not high voltage. This can be performed thanks to the fast active quenching scheme that limits the swing in node A to 1.8V. Figure 1(b) depicts the compact layout of a single detector. The pixel pitch is 32μm, and the fill factor is around 11%. The SPAD has a quasi-circular shape with a 12μm-diameter active area. The structure of the device can be seen in Figure 3. The TWELL implant is a p-type guard ring meant to uniformly distribute the electrical field across the edges of p+ implant, in order to avoid undesired avalanches below the defined breakdown voltage. This guard-ring structure has the drawback of increasing the jitter because of electron–hole pairs generated by photon absorption in areas with low field. Further optimization of this structure with a technology-CAD tool leads to an improvement of the SPAD jitter. An alternative that can reduce the jitter even more is replacing the p-type structure with a SiO 2 shallow-trench-isolation guard-ring [22]. This greatly reduces the diffusion tail of the instrument response function. 3. MEASUREMENTS 3.1. Dark-count rate, afterpulsing and dead-time The first magnitude to be evaluated, in order to characterize the operation of the SPAD and the proposed AQC, is the influence of dark counts (DC), which are current avalanches that are not Table I. Transistor sizes (in μm)—W/L. M1, M2 M3, M4 M5 M6 M7 M8 Inv1-PMOS; NMOS Inv2-PMOS; NMOS Inv3-PMOS; NMOS Nand1-PMOS; NMOS 5/0.18 2/0.18 0.33/3 3/0.25 1/1.54 4/2 1/0.18; 5/0.18 12.56/0.18; 5/0.18 2.5/0.18; 0.5/0.18 1.25/0.18; 0.5/0.18 Figure 2. Post layout simulation of the quenching and recharge times—signals chronogram. COMPACT CMOS AQR CIRCUIT FOR SPAD ARRAYS 921 Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta ignited by a triggering photon. These DC are considered noise in the operation of the SPAD. They are usually caused by thermal noise. A different type of phenomenon, also resulting in false photon count, is afterpulsing. It is due to nonzero lifetime of the carriers trapped in the silicon imperfections. SPAD noise becomes more important when dealing with lower illumination rates, what means low signal-to- noise ratio (SNR). The number of dark counts can be optimized for a specific application by tuning the active area of the SPAD (at the design phase), the excess voltage (V e ), and the operating temperature. Notice that minimizing the DCR by playing with the aforementioned parameters, the PDE lowers as well. Therefore, a trade-off needs to be made between PDE and DCR (Section 3.2). Afterpulsing is also strongly dependent on the temperature, excess voltage, and the quality of the material used in the process. For a certain density of defects, afterpulsing can be reduced by limiting the magnitude and duration of the avalanche current. This is why the speed of the quenching action is very important. Besides, an appropriate dead-time allows lowering the probability of spurious triggering after an avalanche has been ignited by light or thermal noise. Figure 4 depicts the output of the SPAD detector exposed to a pulsed light source of 2.5MHz. The hold-off time of the SPAD is set to 3ns (middle subset) and 80ns (bottom subset). The output voltage of the detector, V SPAD , has been routed to a digital output pad and measured with an oscilloscope or driven into one of the channels of a time tagging instrument (PicoHarp 300 from PicoQuant). In which case, the other channel of the instrument is connected to the synchronization signal of a pulsed laser. Usually the dark-count rate can be measured by counting the pulses over a certain time window. Another way to infer the contribution of this noise is to measure the distribution of time intervals between consecutive noisy pulses (Figure 5), which is called the interavalanche time method. This alternative relies on the exponential nature of the occurrence probability of uncorrelated noise [23]. Thus the DCR is inferred from the slope of the best fit curve of the histogram plotted in logarithmic scale. At the same time, this approach is effective to evaluate Figure 3. Schematic cross section of the integrated single-photon avalanche diode—notice that depths of the implants are not drawn to scale. Figure 4. Measured active quenching circuit output when the detector is exposed to a pulsed laser, at two different hold-off time configurations: 3 and 80ns. PC, photon count; DC, dark count. 922 I. VORNICU ET AL. Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta afterpulsing. It consists in extracting correlation between the time instants in which the leading edges of the avalanche pulses occur. Afterpulsing happens at time scales of hundreds of nanoseconds at room temperature. This means that the histogram of the inter-avalanche arrival time must show multiexponential behavior up to 1μs, as explained in [24]. The afterpulsing probability for a specific value of the dead-time can be found by taking the inter-avalanche time histogram, fitting an exponential to the uncorrelated noise source, and then finding the fraction of events above the fit but below the experimental curve. The afterpulsing probability is the area between two curves, divided by the area under the experimentally acquired curve. Figure 5 shows the inter-avalanche time histogram for an excess voltage of 1V, at room temperature and with a dead-time set to 40ns. DCR is 26kHz at 1 V excess voltage. Using V e close to V BD , DCR could be drastically decreased [25]. However, in order to have a reliable estimation, DCR needs to be reported together with the PDE achieved at the same excess voltage and temperature. This implementation proved to have a DCR of 19 kcps at room temperature and 0.9V excess voltage while the maximum value of the PDE in these conditions is 2% at 447nm illumination source wavelength. The inset zooms in the histogram up to 5μs. Because no multiexponential behavior appears, we can claim that the proposed AQC provides negligible afterpulsing. Thanks to the fast quenching mechanism, the avalanche current does not take long enough to fill the traps of the silicon surface [26]. The maximum excess voltage of this detector is 1V. This excess voltage is kept when the temperature varies from 10°C to 80°C. For higher excess voltages, the anode of the SPAD is stuck to 1.8V because of the mechanism described in the succeeding discussions and found also reported in [9]. Let us assume the SPAD junction is recharged, that is, the SPAD is turned on. When the first avalanche current rises, the anode is pulled-up to VDD. At this point, the SPAD should be quenched, and the avalanche current brought back to zero. But if the excess voltage goes beyond 1V, the behavior observed is different. What happens is that the current through the SPAD does not decrease to zero. This explains the increase of the current consumption measured at the power supply source. In these conditions, the recharge transistor M4 is not strong enough to fight against the resistance of the SPAD. As a result, the anode is stuck to VDD and the SPAD cannot be recharged. We have employed transistors supplied at 1.8V in order to lower the power consumption and to improve the quenching/recharging time. A magnitude that displays the robustness of the implementation of the dead time is the jitter of the output pulse width. It is lower than 1.8ns for dead time up to 40ns (Figure 6(a)). Moreover, the variability of the hold-off time across multiple SPAD detectors needs to be evaluated. The measurements for an array of 8×8 SPADs are depicted in Figure 6(b). The hold-off time is tuned Figure 5. Dark-count rate and afterpulsing measurements. COMPACT CMOS AQR CIRCUIT FOR SPAD ARRAYS 923 Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta from 3ns to less than 600ns. Notice that a hold-off time of 30ns has a maximum deviation of less than ±300ps. 3.2. Photon detection efficiency In order to properly evaluate the operation of the proposed AQC, the PDE must be measured. The PDE is the photon-count rate minus the dark-count rate, divided by the expected arrival rate of incoming photons. If the proper illumination conditions are applied, the measured PDE should be independent on the optical power of the source. In order to realize these measurements, we need to comply with the conditions for single photon detection. To prove this, we have tuned the irradiance to the range of nW/mm 2 , as explained in [27]. In a first measurement, in which we try to confirm the independence of the measured PDE on the optical power, we have employed a continuous light source of 447nm wavelength. The integration time is 500ms. The excess voltage is 0.9V and the breakdown voltage being 10.3V. The DCR for this excess voltage is about 19kHz. The measurements have been performed at room temperature. The experimental results confirm that the measured PDE do not present any dependence on the illumination. In addition, the PDE have been measured for different wavelengths. These measurements have been performed at room temperature, with an excess voltage of 0.55, 0.7, and 1V (Figure 7). In order to make a fair comparison with other detectors, DCR and PDE should be measured in the same conditions, that is, excess voltage and temperature. We have tuned the bias voltage of the SPAD 0100 200 300 400 500 0 10 20 30 40 Dead time [ns] Pulse width jitter [ns] (b) (a) Figure 6. (a) Hold-off time stability represented by the jitter of the output pulse-width and (b) hold-off time variability across 8 × 8 array of single photon avalanche diodes. 924 I. VORNICU ET AL. Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta from 10.8V to 11.3V at room temperature and measured both DCR and PDE for 447nm wavelength (Figure 8). The irradiance employed for PDE is about 3.6nW/mm 2 . The best PDE of 2% for this λis achieved at 0.95–1V excess voltage. Therefore, the optimum excess voltage that gives the best PDE at minimum DCR is 0.95V. 3.3. Time resolution An important parameter of a SPAD detector is the time resolution, which is the minimum time slot that can be resolved. The purpose of the proposed detector is to be incorporated in arrays of sensors for PET applications [3]. Therefore, a time bin of less than 200ps is enough for this kind of measurement. For the experimental determination of the time resolution of the SPAD detector, we have employed a PicoHarp 300 from PicoQuant. The instrument response function can be collected at maximum 4ps resolution. Because of the limitation imposed by the input channels and also to avoid possible interpulse pile-up effects, a 2.5MHz laser repetition rate is used in this setup. The power of the laser spot has been set to 6nW which means an irradiance of 1.46nW/mm 2 . Considering the laser repetition rate, the active area of the SPAD, and the energy of each photon with 447nm wavelength, the estimated number of photons per pulse is 0.148 photons/pulse. The total number of counts is then 2.4% of the repetition rate. This will be enough to ensure that the time measurement is not affected by the pile-up. Last but not least, special caution is needed to attenuate the laser reflections. They can distort significantly the instrument response function. The experiment has been conducted 400 450 500 550 600 650 700 750 800 0 1 2 3 4 5 6 7 8 λ PDE [%] Ve = 0.55V Ve = 0.7V Ve = 1V Figure 7. PDE versus wavelength of the incident light. 0.5 0.6 0.7 0.8 0.9 1 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 PDE [%] PDE DCR DCR [kHz] Figure 8. PDE and dark-count rate (DCR) versus V e at 447 nm wavelength. COMPACT CMOS AQR CIRCUIT FOR SPAD ARRAYS 925 Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016; 44:917–928 DOI: 10.1002/cta