A New Strong Inversion 5-Parameter Transistor Mismatch Model

ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland A New Strong Inversion 5-Parameter Transistor Mismatch Model Teresa Serrano-Gotarredona and BernabC Linares-Barranco National Microelectronics Center Ed. CICA AV. Reina Mercedes s/n, 41012 Sevilla Spain E-mail: bemabe@ imse.cnm.es Abstract A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors. I. Introduction Characterization and simulation of MOS transistor mismatch is crucial for precision analog design. Usually, statistical characterization parameters are extracted independently for different regions of operation [1],[2]. This works satisfactorily for square and long channel transistors, but when aspect ratios differ significantly or very small transistor lengths are used, the traditional mismatch models provide poor fit between measured and predicted values. In this contribution we report on an extended mismatch model whose statistical parameters are extracted simultaneously from curves measured in the ohmic and saturation regions. As a result an extraordinary fit between measured and predicted mismatch is obtained, for both regions of operation, and for a very wide range of transistor sizes, including minimum channel length transistors. I 11. The New Mismatch Model An acceptable strong inversion large signal transistor model for mismatch is [ 11-[2], 1 'GS - 'T( 'SR) - 5 vDScfl IDS = 0 1 +e(v,,- vr(vsR)) (1) vT(v.S8) = vTO+Y[&%-&l (2) where vDseff = vD, for ohmic region (VDs< Vcs-.vT) or VDSc,/ = V,, - V,( vsB) for saturation ( v,, 2 V,, - V, ), p = pC,,W/L is the current gain factor, V,, IS the zero-bias threshold voltage, y is the bulk threshold parameter, and 8 is the mobility degradation parameter. Assuming Ap , AVro, Ay and AI3 are the dominant transistor mismatch parameters [I]-[2], differentiating eq. (1) yields the following current mismatch model for a given transistor pair where the set of four mismatch parameters {Ap/p, AV,,, Ay, Ae} would characterize this transistor pair mismatch for any bias point. However, for short channel transistors the effect of source and drain series resistance as well as carriers velocity saturation are important for mismatch, but are not modeled in eq. (1). The effect of drain and source series resistances can be included in eq. (1) by replacing V,, by V,, - lD,R, and V,, by V,, - !D~(Rs + RD) . After neglecting high order terms an equation similar to eq. (I) results in which 8 has been substituted by e.,,, with (5) Carriers velocity saturation v, can be introduced by dividing the right hand side of eq. (4) by 1 + VDseffp/(2vsL) [31-[41, where, and both effects, series resistances and carriers velocity saturation, are included. Eq. (7) yields the following mismatch for A@-,, where AOo is the A@?,, mismatch in ohmic region for V,, = 0 and Ae0 + AeP is the mismatch in saturation, with In order to characterize the five mismatch parameters {Ap/p, AV,,, Ay, AB,, Ae,} , eq. (3) needs to be measured in ohmic (with VI,, = 0 ) while extracting mismatch parameters 0-7803-5482-6/99/$10.00 02000 IEEE IV-381 of eq. (3) with AB = AB,, , and in saturation while extracting mismatch parameters of eq. (3) with AB = Aeo + AB,. 111. Mismatch Parameter Extraction A mismatch characterization chip including 30 different NMOS and PMOS transistor arrays of different sizes was fabricated in the ES2 I .Opm CMOS process [6]-[7]. Transistor widthswere W = 40pm, 20pm, loprn, 5pm, 2.5pn1, 1.25pm whilelengths were L = 40pm, IOpm, 4pm, 2pm, lpm .Each array contained 30 transistor pairs. For each pair four I-V curves were measured: Curve 1 (ohmic): V,,=O. 1 V, V,,=OV, V,, E [ 1.5,s VI Curve 2 (ohmic): vDS=o.1 V, VG,=3V, Vs~ E [O, 2V1 Curve 3 (saturation): VDs=4V, V,,=OV, V,, E [ 1.5, 5VJ Curve4 (saturation): VDs=4V, V,,=3V, VGS E [O, 2V] (10) First, using eqs. (1)-(2) the large signal parameters p, V,,, y, 0 and @ were extracted from these curves for each transistor pair using nonlinear multi-parameters curve fitting techniques, such as the Levenberg-Marquadt method [SI. These parameters were used to compute the partial derivatives in eq. (3) for each of the four measured curves. Afterwards, four versions of eq. (3) were obtained, one for each of the curves in eqs. (IO), and were fitted simultaneously to the measured data AiDs/IDs resulting in a unique set of mismatch parameters for each transistor pair [ APlp, AV,,,, Ay, ABo, A€le 1 valid for saturation and ohmic regions. The precision with which the mismatch parameters are extracted depends on the number of data points measured for each curve, and on the precision with which each data point is measured. We noticed that using a large number of data points does not improve much the precision of the extracted parameters, and observed that a reasonable compromise between measurement-time and precision was obtained for 1 I data points. On the contrary, it was very important to measure each data point with as much precision as possible, i.e. with as little measurement noise as possible. Instruments eliminate noise by repeating the measurement several times and providing the average as the result. In our case, we set the instrument to average 256 meaurements. This way, when computing AIDs/IDs , we did not obtain pure noise. Regarding the large signal model, note that eqs. (6) and (2) describe a very simplistic MOS transistor model. This means that we cannot expect to obtain for all transistor sizes the same large signal parameters. Furthermore, for the same transistor, we should not expect to obtain the same large signal parameters when it is biased in ohmic or in saturation. Consequently, for each transistor, the large signal parameters should be extracted independently for Curves 1-2 and Curves 3-4. For each transistor pair, the measurementlextraction procedure is as follows. I. Measure Curve 1 for both transistors. Extract the large signal parameters I P, Vm e<jjXe,,,,< . 2. Measure Curve 2 for both transistors. Compute (by eq. (6) in ohmic), (using for p and e.,, the values extracted from Curve 1) and fit it to eq. (2) (using for v,,, the value extracted from 3. Measure Curve 3 for both transistors. Extract the large signal parameters { P, V7,, e?,, } ,,,, . Curve 11, obtaining {Y, $}oi,,,,,, . 4. Measure Curve 4 for both transistors. Compute (by eq. (6) in saturation), (using for p and B,, the values extracted from Curve 3) and fit it to eq. (2) (using for V,, the value extracted from Curve 3), obtaining {y, $},,, . At this point we have the large signal parameters for ohmic {P, Vrn, gPfj, Y, @XI,,,,,, and saturation {P7 VTO, %,Y, @lo,. To obtain , now the five mismatch parameters {APIP, AV,,, Ae0, A9,, Ay} for the transistor pair, the procedure continues as follows, 5. For the current mismatch of Curve I (see eq. (3)) (13) 'IDs = fll! + X,,,AV,, + X2,Ae, -I IDS I compute the coefficients x36 = Xlb[m-&l using {e<,,, @h ,,,,, c, where V,,, = 3.0V and V,(Vm) is obtained from eq. (1 I). 7. For the current mismatch AI~JI~, of Curve 3 (see eq. (3)) = !f!+X,,AV,,+X,,(AB,+AB,) (17) IDS p compute the coefficients using { Vro, e.,, k,,, 8. For the current mismatch AIDs/iDs of Curve 4 (see eq. (3)) IV-382 '21 = $! + X,(,AVr0 + X2,,(Ae0 + AB<) + X,,,Ay compute the coefficients (19) 4 x,, = Xldrm-41 using {eeJ,, @la,, where V,,, = 3.0V and Vr( VsB) is obtained from eq. (12). 9. Fit simultaneously eqs. (13), (15), (17) and (19) using the Least Squares Minimum (LSM) algorithm, obtaining the optimum five mismatch parameters { Ap@, AV,,, Ago, AB,, Ay} for each transistor pair This measurementlextraction procedure is repeated for the 30 transistor pairs of equal size. For each extracted mismatch parameter AP (AD@, AVTo, AOo, AB,, Ay) its standard deviation cr(Ap) is computed, as well as all correlations between pairs of mismatch parameters r(bP Ap ). For each fabricated chio, standard deviations and dorrklations are obtained for kach transistor size and type (NMOS and PMOS). IV. Mismatch Characterization Results Statistical characterization of these five parameters results in five standard deviations up, by , U,, ue , and 10 correlation coefficients for each tra&stor size: which can be used to predict the current mismatch standard deviation Fig. I compares the measured values of u(AIDs/IDs) (shown with symbols) with those predicted by eq. (21) for the two first measured curves of eqs. (lo), for all 30 transistor sizes. As can be seen the agreement between measured and predicted mismatch is excellent. To our knowledge, such agreement has never been reported before using other mismatch models for such a wide range of transistor sizes, including short channel ( Ipm ) transistors. In order to compare with other models, Fig. 2 shows u(AIDs/IDs) for NMOS transistors of size W = 40pm, L = 2pm , for all four measured curves. Circles are measured values. Continuous lines are predicted values using the model proposed in this paper, including all correlation coefficients. Dashed lines are predicted with the same model, cut considering only the three most relevant Correlation coefficients (r(b,ecl, r(b,ecl, rCB,,,) . Dotted lines correspond to extracting only (A$/p, AV,,,,Ay) for ohmic region, and use theresulting { o0. 0 uu} (without correlation coefficients) to predict u(AIDs/IDs;% both ohmic and saturation regions. This is the method used by Pelgrom [l]. Dashed-dotted lines correspond to extracting {AB@, AV,,, Ay} for both regions, and use the resulting {q, uyTo, UT} (without correlation coefficients) to predict u(AIDs/IDs) in both regions. Lines with little squares correspond to extracting {@/B. AV,,, Ay, AO} in saturation, and use the resulting {up, uvTo, U,, ue} (and correlation coefficients) to predict u(AIDJIDs) in both regions [2]. Lines with little triangles are the same but extracting { Ap/p, AV,,, Ay, AB} in ohmic region. And finally, lines with diamonds are the same but extracting {Ap/p, AV,,, Ay, Ae} for both regions. ., Fig. 1: Measured vs. Predicted Current Mismatch ~(AZD~ZDS) (in %) for all transistor sizes for (a) Curve 1, (b) Curve 2. Symbols denote different transistor lengths: circles L=40pm, crosses L=lOpm, stars L=4p, diamonds L=Zptn, triangles L=lp. Fig. 3 shows the values of the extracted standard deviations u(Ap/$), u(AV,,), u(Ay) , u(AB,), u(AB,) as a function of transistor size. For each transistor size, 8 diamonds are shown, one for each of the 8 non-faulty measured chips. For simulation purposes, it is very convenient to have a dependence for the mismatch standard deviations as functions of transistors width W and length L. Many such dependencies have been ~~~ 0 1 2 I 2345 Fig. 2: Comparison of U(AI~JI,~~) for all four measured curves using different msmatch models, for NMOS transistors of size W = 40pm , L = 2pm IV-383 proposed in the specialized literature [I], [2], [8]. In the present study we just intend to obtain amathematical function able to fit the measured data. We do not intend to provide a physical interpretation to the resulting fitting coefficients. Consequently, we selected a very general mathematical function and let the fitting routines select the best coefficients for our data. The chosen mathematical function is 4.7e-7 3.5e-7 where parameters C,,,,, , E,, and E, are computed for each mismatch parameter Af. Using the 30x 8 data points available for each standard deviation, the surfaces in Fig. 3 were obtained using standard least square fitting procedures. The resulting coefficients for eq. (22) are shown in Table 1. for each standard deviation for NMOS transistors. 1.k-3 2.k-4 1.6e-4 -2.0e-3 22-3 7.8e-4 0.14 -9.3e-1 1.9e-4 1.le-5 1.2e-6 2.5e-4 -1.8e-5-1.8e-5 -1.1 7.9e-I Table 1.: Resulting Fitted Parameters for Surfaces defined bv ea. (22) for NMOS Transistors. Units for W.L are um. .(Ae,) .(Ae,) 4.94 -5.9e-6-5.2e-7 2.k-5 2.k-4 -5.9e-4 4.7e-3 -5.7 -5.le-2 53-8 -4.8e-6 25-6 1.0e-6 8.3e-5 3.k-5 -7.0e-5 -2.1 8.3e-1 1.5e-7 3.2e-5 1.7e-5 1.7e-6 2.0e-4 -2.k-7-5.&-5 -1.1 5.5.~-1 , ., I 1 I I I I I1 I [71 V. References M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-state Circuits, vol. 24, No. 5, pp. 1433-1440, October 1989. J. Bastos, M. Steyaert, A. Pergoot, and W. E. Sansen, “Mismatch Characterization of Submicron MOS Transistors,” Analog Integrated Circuits and Signal Processing, 12, pp. 95-106, Kluwer Academics, February 1997. Y. Tsividis, Operation and Modeling of the MOS Transistor: New York: McGraw--Hill, 1988. U. Cilingiroglu, Systematic Analysis of Bipolar and MOS Transistors. Boston: Artech House, 1993. W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C. The Art of Computing. Cambridge University Press, 1988 . T. Serrano-Gotarredona and B. Linares-Barranco, “Cheap and Easy Systematic CMOS Transistor Mismatch Characterization,” Proceedings of the 1998 IEEE Int. Symp. on Circuits and Systems (ISCAS’98), Monterrey, June 1998. T. Serrano-Gotarredona and B. Linares-Barranco, “Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation,” Analog Integrated Circuits and Signal Processing, to be published. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transitors for Precision Analog Design,” IEEE Journal of Solid-state Circuits, vol. SC-21, No. 6, pp. 1057-1066. December 1986. (e) ,L,lil, I*/ *”, Fig. 3: Measured and fitted mismatch parameters for NMOS transistors. Diamonds are measured parameters for each transistor size and die. Surfaces correspond to fitted mathematical functions for (a) o(AB/B), (b) ~(AVTO), (c) o(Ae,), (f) o(Ae,), (e) AY). Units for 1/W and 1/L axes are pn . IV-384