A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

A 0.35 µm CMOS 17-bit@40-kS/s cascade 2-1 Σ∆ modulator with programmable gain and programmable chopper stabilization. Oscar Guerra, Sara Escalera, José M. de la Rosa, Rocío del Río, Fernando Medeiro and Ángel Rodríguez-Vázquez1. Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC) Av. Reina Mercedes, 41012-Sevilla, SPAIN. ABSTRACT This paper describes a 0.35µm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Σ∆ modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40ºC, 175ºC). The modulator architecture has been selected after an exhaustive comparison among multiple Σ∆M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography. Keyword list: Σ∆ modulator, chopper stabilization, gain programmability 1. INTRODUCTION In last years has been increased the use of sensors for many applications at different parts in the vehicles, such as the engine, powertrain and braking 1. Therefore, the number of applications is increasingly growing with the combined use of MicroElectroMechanical (MEM) sensors and Digital Signal Processors (DSPs) on a single chip or within the same package 2. These “smart” sensors must operate under very adverse environmental conditions with extreme temperatures ( ), mechanical shocks, electromagnetic interferences, etc. Therefore, the A/D interface driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC) as illustrated in Fig. 1, must be very robust in order to handle the typically weak sensor output signals (ranging from µVs to hundreds of mVs) in very hostile environments 3,4. This is aggravated in most applications as a consequence of the offset voltage due to the excitation voltage (vexc) supplying most transducers. In practice, that offset voltage is subject to temperature and manufacturing process variations, thus causing a shift in the signal range provided by the sensor. Hence, the sensor A/D interface must accommodate the complete range of possible offsets and real signals. In such devices, a programmable gain preamplifier is normally used to boost the sensor signal to a workable level where the ADC digitizes it and the rest of processing is carried out in the digital domain 3. 1.E-mails: (guerra,escalera,jrosa,angel)@imse.cnm.es; 40°C,175°C–[] Fig.1: Conceptual block diagram of a “smart” sensor chip. + -+ - Preamplifier Digital Signal Processor v exc ADC MEM Transducer Control Signals VLSI Circuits and Systems II, edited by José Fco. López, Francisco V. Fernández, José María López-Villegas, José M. de la Rosa, Proceedings of SPIE Vol. 5837 (SPIE, Bellingham, WA, 2005) 0277-786X/05/$15 · doi: 10.1117/12.608304 71 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use In this scenario, the use of ADCs based on Sigma-Delta Modulators (Σ∆Ms) is advisable for several reasons. On the one hand, the noise-shaping performed by Σ∆Ms allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs 6. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of Σ∆Ms with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation 4. This feature allows to accommodate the complete range of possible transducer offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes a programmable-gain, chopper-stabilized, third-order cascade (2-1) Σ∆M in a 3.3V, 0.35µm CMOS technology. The design of the circuit is made by using an advanced top-down methodology that combines simulation and statistical optimization at different levels of the hierarchy. Experimental results show correct operation in the 20kHz BandWidth (Bw) with 110dB overall Dynamic Range (DR) and 113dB DR within Bw=10kHz. These figures locate this circuit instance at the edge of the state-of-the-art, with the added value of being one of the few high-resolution Σ∆M-based ADCs with embedded programmable-gain reported to date. 2. ARCHITECTURE SELECTION AND BLOCK SIZING The technology used in the design of a 40-kS/s Σ∆M for an automotive sensor interface requiring within a temperature range of ([-40ºC,175ºC]) is a 3.3V, 0.35µm CMOS, with Metal-insulator-Metal (M-i-M) capacitors available. In order to obtain the best Σ∆M that fulfils these specifications with the minimum power consumption, a large number of architectures have been compared in terms of the estimated power consumption and silicon area, considering the impact of main circuit error mechanisms and technology parasitics. This comparison is summarize in Table 1 for Σ∆Ms with 1-bit quantization. Note that the third-order 2-1 cascade Σ∆M shown in Fig. 2, with M=128 obtains the best result except for . In this case the lowest power consumption is obtained by a 2nd-order single-loop Σ∆M with M=512, but this arquitecture has been discarded for several practical reasons: a less relaxed design of building blocks and switching noise coming from the digital part. DR 110dB≥ Table 1: Outcome of the Σ∆M architecture selection Σ∆M Gain, Order ( )a a. All Σ∆Ms in this table are cascade architectures except for L = 2. Oversampling Ratio ( ) Estimated Power Consumption (mW) 0.5 3 128 6.77 3 256 8.12 4 128 8.27 1 3 128 8.48 3 256 9.77 4 128 10.32 2 3 128 12.69 3 256 13.85 2 512 13.88 4 2 512 23.24 3 128 24.21 3 256 25.02 ξLM in g2 - g2' - g1' DAC g3 g3' g3'' - - DAC g1 OPA OPB OPB Y1Y1 , Y2Y2 , ξ g1ξg1'⋅= g1'0.25= g21= g2'0.5= g31= g3'g3''=0.5= + + 2 out H 2 ( z ) Cancellation Logic H 1 ( z ) H1z() z1– = H2z() 1z1– –() 2 = Fig.2: Conceptual block diagram of the programmable-gain 2-1 cascade SC Σ∆M. ξ4= 72 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use Fig. 3 shows the fully differential SC schematic of the selected Σ∆M architecture. The first stage of the modulator includes two SC integrators − both of them with two differential input branches −, and switches controlled by the comparator output are employed to feed the quantized signal back. Note that in the first integrator one of input branches is for the input signal, in which double sampling is used to achieve an extra signal gain of 2, without increasing circuit noise 5. The second branch receives the Digital-to-Analog Converter (DAC) outputs. Making use of the spare connection of the second branch, an external DC signal (Voff) can be applied during to center the sensor signal in the modulator full-scale range, doing unnecessary a third branch for offset compensation with the subsequent thermal noise saving. The second stage of the modulator incorporates an integrator with only two input branches, although three different weights are implemented − (see Fig. 2). This can be done because the selection of weights in the designed modulator allows the distribution of weight between the two integrator branches and . The modulator operation is controlled by two non-overlapped clock-phases. The integrators input signals are sampled during phase . During phase the algebraic operations are performed and results are accumulated in the feedback capacitor of each integrator. In order to attenuate the signal-dependent clock-feedthrough, delayed versions of the two phases − and − are also provided. As illustrated in Fig. 3, this delay is incorporated only to the falling edges of the clock-phases − i.e., to the turn-off of the switches −, while the rising edges are synchronized in order to increase the effective time-slot for the modulator operations 7. The comparators are activated at the end of phase − using as a strobe signal − to avoid any possible interference due to the transient response of the integrators outputs in the beginning of the sampling phase. This timing guarantees a single delay per clock-cycle. In addition to the master clock phases, and , additional phases are required to control the chopper switches used in the first integrator to attenuate flicker noise. These chopper phases are controled by a master clock with a programmable frequency. - + + - - + + - 2 C u + - X φ 1d φ 1 φ 1 φ 2 φ 1d φ 2 φ 2d φ 1d - + + - C u 2 C u φ 1d φ 1 φ 1 φ 2 φ 1d φ 1 φ 2d φ 2 φ 1d φ 1 φ 2 φ 1d φ 1 φ 2 φ 1 φ 2d φ 1d φ 1 φ 2 φ 2d φ 2d C u 2 C u C u C u 2 C u C u C u C u Y 1 Y 1 φ 1 φ 2 C u Y 2 Y 2 V ref - V ref + V ref + B 1 A 1 B 1 A 1 B 2 A 2 B 2 A 2 B 1 A 1 B 1 A 1 B 1 A 1 B 1 A 1 B 1 A 1 B 2 A 2 OPA OPB OPB φ 1dch φ 1dch φ 2ch φ 1ch φ 1ch + - V off φ 1d φ 1 φ 1 φ 2 φ 1d φ 2 ξ ξ ξ ξ ξ ξ 4 C s2 4 C s2 C s2 C s2 C s1 C s1 φ 2d φ 2d φ 2dch φ 2d Chopper switches Fig.3: SC fully differential schematic of the 2-1cascade SC Σ∆M in this paper. t φ 1 φ 1d φ 2 φ 2d V ref + V ref - V ref - V ref - V ref + V ref - V ref + V ref + V ref - V ref - V ref + V ref + V ref - φ 1 g3g3′and g3″,, g31= g 3′0.5=g3″0.5= φ1φ2 φ1d φ2d φ2φ2d φ1 φ2 Proc. of SPIE Vol. 5837 73 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use The programmable gain ( ) has been mapped onto switchable capacitor arrays, each of them formed by a variable number of unitary capacitors (C11=1.5pF) as shown in Fig. 4. Such numbers are selected for minimum power dissipation, bearing in mind the circuit noise limitation and the highest temperature required for this sensor interface (+175ºC). In order to keep the amplifier dynamic requirements as relaxed as possible for all cases of the modulator gain, we propose to switch the number of unitary capacitors forming all the capacitances involved − not only the ones forming the sampling capacitors. The Σ∆M in Fig. 3 has been high-level sized, i.e, the modulator specifications have been mapped onto building-block specifications using statistical optimization for design parameter selection, and compiled equations (capturing non-ideal building block behavior) for evaluation. This process is fine-tuned by behavioral simulation using an updated version of ASIDES, an advanced behavioral simulator of SC Σ∆Ms 8. At this step, non-idealities are covered more accurately than in the case of using compiled equations. Also, worst cases for speed (the largest capacitor values) and for thermal noise (the highest temperature and the lowest capacitor values) are contemplated. The outcome of this sizing process is summarized in Table 2, where OPA denotes the opamp used at the first integrator in the chain and OPB refers to the opamps used at the second- and thirdintegrator in the modulator chain (see Fig. 3). The data in Table 2 define the specifications of the building blocks, which are the starting point for block sizing described in Section 3. ξ0.5, 1, 2 and 4= Fig.4: Programmable capacitors in the first integrator. (a) Capacitor arrays. (b) Cs1 implementation. G a G b G c G d 0.5 1000 1 0100 2 0110 4 0111 ξCs1 Cs2 Co Cu4Cu16Cu 2Cu4Cu16Cu 6Cu6Cu24Cu 16Cu8Cu32Cu ξ Gain Selection Logic G a G b G c G d ξ Cu (a) (b) 2Cu 4Cu 10Cu Table 2: High-level sizing of the programmable-gain 2-1 Σ∆M SPECS: 110-dB@40kS/s@2VpValue Unit INTEGRATORS Integration capacitor Gain 0.5 24 pF Gain 1 24 pF Gain 2 36 pF Gain 4 48 pF Unitary capacitor 1.5 pF Sigma 0.1 % Capacitor non-linearity 25 ppm/V2 Bottom parasitic capacitor 5 % Switch ON-resistance <650 Ω OPAMPS DC-gain OPA 68 dB OPB 63 dB DC-gain non-linearity 15% V-2 GBW OPA (44.2pF load) 17 MHz OPB (8.9pF load) 15 MHz Slew-rate OPA (44.2pF load) 17 V/µs OPB (8.9pF load) 28 V/µs Output swing ±2.5 V COMPARATORS (Hysteresis + Offset) (max.) 30 mV Resolution time 50 ns 74 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use 3. DESIGN OF THE BUILDING BLOCKS The modulator building blocks, namely, amplifiers, comparators, switches and capacitors have been conveniently selected and sized according to the requirements given in Table 2. Design considerations on each of these blocks as well as their electrical performance using HSPICE are detailed in this section. 3.1 Amplifiers The key features for the design of the amplifiers are their open-loop DC-gain, dynamic requirements and output swing, where the last one becomes especially critical in a low voltage implementation. Nevertheless, the set of integrator weight used for the Σ∆M in Fig. 3 allow us to relax the output swing requirements to be slightly larger than the reference voltages − 2V in this case −, which is feasible when operating with 3.3V supply in differential mode. Table 2 shows that the OPA has more demanding requirements than the OPB, the reason being that the contribution of the latter to the total in-band error power is attenuated by increasing powers of the oversampling ratio. Thus, to reduce power consumption, they should be considered as different items to design purposes. To achieve this goal an improved version of the transistor-level sizing tool FRIDGE 8 was used to explore the potentials of a wide catalog of fully differential OTA topologies. At the outcome, a single-stage folded-cascode architecture, shown in Fig. 5, was selected as the optimum choice for both amplifiers. N-channel input transistors were employed to take advantage of the twin-well technology feature in removing the body effect of NMOS transistors. The Common-Mode Feed-Back (CMFB) net has been implemented using a SC circuit, which provides fast, linear operation with small power dissipation. Table 3 shows the full sizing and biasing of OPA and OPB, by indicating the multiplicity factor for each transistor. Table 4 summarizes the electrical performance of both amplifiers regarding the target values imposed during the FRIDGE optimization procedure. Parameter values in this table, obtained by electrical simulations using HSPICE, are shown for typical conditions (typical process parameters, nominal supply voltage and room temperature) as well as for worst-cases Fig.5: Fully differential folded-cascode amplifier used in the Σ∆ modulator. vbn vcmfb v+ v–vo– vo+ M 1 M 2 M 5 M 3 M 4 M 6 M 7 M 8 M 9 M 10 M 11 M bn1 M bn0 M bn1c M bn0c M bp3c M bp2c M bp1c M bp0c M bp3 M bp2 M bp1 M bp0 vbp V cm V cm φ 2 φ 1 φ 1 φ 1 φ 1 φ 2 C C C C vbn vbn vcmfb vo– vo+ φ 2 φ 2 Ibias Ibias Table 4: Electrical performance of the opamps (HSPICE) OPA (45pF load) OPB(9pF load) Model Typical Worst-Case Typical Worst-Case DC-gain (dB) 74.0 71.09 68.3 68.3 GB (MHz) 22.6 15.8 34.4 23.8 Phase Margin (º) 86.4 85.5 83.5 81.4 Slew-Rate (V/µs) 22.1 21.1 38.1 35.7 Output Swing (V) ±2.75 ±2.5 ±2.75 ±2.5 Transc. (mA/V) 6.3 4.5 1.95 1.35 Power consumption (mW) 7.1 7.2 2.3 2.4 Proc. of SPIE Vol. 5837 75 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use in a corner analysis − considering fast and slow device models, variation in the 3.3V supply, and temperatures in the range ([-40ºC,+175ºC]). The amplifier nonlinear features (mainly nonlinear DC gain and dynamics) deserve special attention in a high-linear implementation. When the amplifier output swings, the drain-to-source voltage of the output transistors changes, and so does the output impedance. This effect, illustrated in Fig. 6 for the OPA and OPB in the nominal conditions, translates into a dependence of the open-loop DC gain on the output voltage, so that the DC gain reaches its maximum at the central point and decreases as the output approaches the rails. Such a non-linearity is traditionally modeled by second-order polynomial dependence of the gain of the output voltage 6, but this is only valid for small voltage excursions around the central point. On the contrary, in the proposed 3.3-V implementation, it is expected that small-gain regions of the DC curve (shadowed areas in Fig. 6) are often visited during normal operation of the modulator. In order to accurately account for this nonlinearity in behavioral simulations, we have resorted to table look-up procedure from amplifier DC curves obtained by electrical simulation. A similar approach has been employed for validating the actual transient response of the front-end integrator. 3.2 Comparators The specifications for the single-bit quantizers − comparators − at the end of the first and second stages of the modulator are given in Table 2. Among them, a low resolution time around 50ns and a hysteresis lower than 30mV can be pointed up. In order to cope with these specifications, a regenerative latch including a pre-amplifying stage was selected for the comparator 9. Fig. 7 shows the selected topology of the comparator. It consists of a NMOS differential input pair (M1-2), a CMOS regenerative latch circuit and a RS flip-flop. The latch circuit is composed of a NMOS flip-flop (M3-4) with a pair of Table 3 : Si z i ng and b i as i ng o f the opamps SIZES Transistor OPA (µm/µm) OPB (µm/µm) M1,2 5x(40/0.5) 2x(25/0.5) M3,4 8x(65.6/0.5) 8x(25.5/0.5) M58x(42.5/0.5) 8x(10.7/0.5) M6,7 5x(32/0.5) 5x(8/05) M8,9 8x(31.05/0.6) 8x(5.65/0.45) M10,11 8x(64/0.5) 8x(30.20/0.45) Mbp0 8.85/0.5 4/0.5 Mbp1,2,3 65.6/0.5 25.5/0.5 Mbpc0,1,2,3 64/0.5 30.20/0.45 Mbn0 4.45/0.5 1.9/0.5 Mbn1 42.5/0.5 10.7/0.5 Mbnc1,2 31.05/0.6 5.65/0.45 Biasing Ibias (µA) 110 36.7 10%± Fig.6: DC-gain non-linearity for: (a) OPA, (b) OPB. (a) (b) -4.0 -2.0 0.0 2.0 4.0 0.0 1000 2000 3000 4000 5000 Effective DC-gain Differential output voltage (V) -4.0 -2.0 0.0 2.0 4.0 0 1000 2000 3000 Differential output voltage (V) Effective DC-gain 76 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use NMOS switches (M9-10) for strobing and a NMOS switch (M17) for resetting, and a PMOS flip-flop (M5-6) with a pair of PMOS precharge switches (M7-8). The comparator is activated at the end of the integration phase, solving the difference of the integrators outputs. At the beginning of the next integration phase, the outputs of the latch are forced to the low state and the RS flip-flop maintains the comparator output until the next strobbing of the latch. As shown in Fig. 7, different voltage supplies have been used for the pre-amplifier and for the regenerative latch − VDDAA and VDDAD, respectively. This has been done in order to reduce the comparator sensitivity to injected digital switching noise and supply bounce effects. The circuit in Fig. 7 has been designed according to the required high-level specifications, while the input capacitance and the power consumption should be kept as low as possible. Table 5 shows the sizes of the transistors and the value of the bias current. Multiple MonteCarlo simulations and corner analysis have been done for characterizing the comparator performance during its full sizing. Table 6 summarizes the electrical performance, showing the worst-cases for hysteresis, offset and resolution time together with the power dissipation. As expected, the resolution is dominated by mismatching, the offset being the dominant limitation factor with a worst-case value of 9.92mV − according to the specifications given in Table 2. 3.3 Switches The main design issue of switches is their finite switch on-resistance, Ron, which is mainly constricted by dynamic considerations. Incomplete settling originated by transmission gates is traditionally reduced by making . In our design, it was previously evaluated (see Table 2) that Ron in the range of 650Ω can be tolerated with no degradation of Fig.7: Schematic of the comparator. a) Preamplifier + latch. b) RS flip-flop. φ2dφ2d φ2dφ2d R v+v– Ibias o o R S A BAB+ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 M 9 M 10 M 17 M 16 M 11 M 12 M 14 M 18 M 19 M 20 M 21 S M 13 M 15 (a) (b) V DDAD V SSAD V DDAD V DDAD V SSAD V SSAD V DDAA V SSAA V SSAA V DDAD V SSAD Table 6: Electrical performance of the comparators (HSPICE) Parameter Typical Worst-case Offset (mV) 0.75 9.92 Hysteresis (mV) 0.03 0.12 Resol. time, (ns) 4.1 8.6 Resol. time, (ns) 3.9 6.15 Power Consumption (mW) 0.43 TRLH TRHL Table 5: Sizing and biasing of the comparators MOST W/L (µm/µm) M1,2 20/0.5 M3,4 4/2 M5,6 16/2 M7-10,12-15,17 1.5/0.35 M11,16 8/1 M18 6.3/0.35 M19 4.2/0.35 M20,21 11.9/0.35 Ibias 55µA RonCs1fS1« Proc. of SPIE Vol. 5837 77 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use the modulator performance. In our technology process, this value can be obtained using CMOS switches with aspect ratios of 6.5/0.35 for the NMOS transistor and 23.5/0.35 for the PMOS, operating with the nominal 3.3-V supply. However, in low-voltage technologies, given that the threshold voltage of the MOS transistors is not scaled down in the same amount as the supply voltage, the voltage range in which Ron keeps a nearly constant value decreases. This is illustrated in Fig. 8 by showing the Ron of several CMOS switches as a function of the signal level. The sampling process with such an on-resistance causes dynamic distortion 10 − the more evident the larger the sampling capacitor and the signal frequency. In sensor interfaces, high-linearity is a must. Therefore, the non-linear sampling effect in the first integrator (which is the block that samples the signal in our system) has to be carefully taken into account, especially in the case of , in which Cs1=24pF. In this case the CMOS switch size given above causes harmonic distortion which can severally degrade the performance of the sensor interface. However, resorting to larger aspect ratios to solve this problem increases parasitics and power dissipation, whereas including clock-bootstrapping strategies 11 increases complexity and leads to a less robust design. For this reason, the sampling process in the first SC integrator in Fig. 9(a), has been extensively studied using the sampling circuit in Fig. 9(b). Electrical simulations have been done using corner analysis for a 0dBV@20kHz sine-wave input signal, obtaining that the worst value of the Total Harmonic Distortion (THD) generated by the analog switches is - 100dB, which agrees with required specifications. This implies that the sizing used for the CMOS switches −aspect ratios of 29.1/0.35 for the NMOS transistor and 105.9/0.35 for the PMOS− ensures a distortion low enough for the present application, and suggest that clock-boosting or similar techniques are not required in the technology used. 3.4 Capacitor arrays Capacitors have been implemented using the M-i-M structures available in our technology process. Using this topology, the 1.5-pF unitary capacitor is required to make the integrator weights is approximately 31.6 µm x 31.6 µm size. The estimated mismatch for this capacitor is . As mismatch error is one of the most important limiting Fig.8: DC characteristic of several analog CMOS switches. Voltage level (V) R on ( Ω ) -2 -1 0 1 2 40 60 80 100 120 Ron 60Ω= Ron 90Ω= NMOS: 29.1/0.35; PMOS:105.9/0.35 NMOS: 19.4/0.35; PMOS:70.6/0.35 ξ4= (a) (b) Fig.9: Analog switches: (a) fully differential SC integrator, (b) Circuit under evaluation. C s 1 + - V in φ 1 φ 1 φ 2 φ 1 φ 2 C o φ 2 C o C l C l φ 1 φ 2 C p C p C s 1 - + + - C s 1 + - C s 1 V SS V SS V DD V DD V DD V DD V SS V SS V Cip + - V Cin + - V in σ∆CC⁄()0.1%= 78 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use factors in cascade architectures, common centroid structures have been used in the layout. In the case of the first integrator, all the capacitors (Cs1, Cs2 and CO in Fig. 3) are made up of unitary capacitors which are connected or disconnected depending on the case of the modulator gain (see Fig. 4). In this case a programmable common-centroid structure, symbolically shown in Fig. 10, has been used while the matching of weights , , , is just based on closely placed capacitors. 3.5 Auxiliary blocks In addition to the building blocks described in previous subsections, there are other on-chip auxiliary blocks required in practice for the implementation of the programmable-gain Σ∆ modulator, namely: clock-phase generator, master-bias current generator and gain-selection logic. These blocks will not describe in this paper. 4. EXPERIMENTAL RESULTS The modulator has been designed and fabricated in a single-poly, five-metal, 0.35µm CMOS technology. The complete modulator occupies an area of 5.7mm2 (pads included) and dissipates 14.7mW from a single 3.3-V supply. The chip is encapsulated in 64-pin plastic quad flat package. Double-bonding techniques and multiple pins are used for the power supplies in order to reduce supply bounce. The circuit has been tested using a PCB that includes intensive filtering and decoupling strategies, as well as proper impedance termination to avoid reflections of high-frequency signals. The performance of the modulator was evaluated using a high-resolution (-100dB THD) sinusoidal source to generate the input signal and a digital data acquisition unit to generate the clock signal and to acquire the bit streams of the first and second stages of the Σ∆M. The same unit controlled the supply and reference voltages. After the acquisition, performed automatically by controlling the test set-up through proprietary C routines, data were transferred to a workstation to perform the digital postprocessing using MATLAB. The digital filtering was performed with a Sinc filter, implemented by software. Fig. 11 shows a measured 65536-point Kaiser-windowed fast Fourier transform (FFT) of the modulator output, clocked at 5MHz and considering a -12dBV, 5kHz input sinewave, a modulator gain of ( ) and a chopper frequency equal to fch=fs/2. The effect of varying the chopper frequency is illustrated in Fig. 12(a) by showing several output spectra corresponding to fch = fs/16, fs/4, fs/2. Note that, the lower fch the more flicker noise appears in the signal bandwidth, thus degrading the modulator performance. This is better illustrated in Fig. 12(b) where the Signal-to-(Noise+Distortion) Ratio (SNDR) vs. signal amplitude is represented for and different cases of fch. It can be noted that the best performance is achieved when fch=fs/2. For that reason, in the following, all measurements will be given for this value of fch. Fig.10: Conceptual layout of programmable capacitor array of the fiont-end integrator. C s 1 / C 0 =1/16 C s 1 / C 0 =2/16 C s 1 / C 0 =6/24 C s 1 / C 0 =16/32 C s 2 / C 0 =4/16 C s 2 / C 0 =6/24 C s 2 / C 0 =8/32 Dummy C s 1 C s 2 C 0 C s 2 / C 0 =4/16 Gain 0.5x Gain 1x Gain 2x Gain 4x g2′g3′g3″ ξ1= ξ1= Proc. of SPIE Vol. 5837 79 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 27 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use