Class AB output stages for low voltage CMOS opamps with accurate quiescent current control by means of dynamic biasing

Class AB output stages for low voltage CMOS opamps with accurate quiescent current control by means of dynamic biasing. A. Torralba 1, R. G. Carvajal 1, J. Ramírez-Angulo 2, J.Martínez-Heredia 1 and A. P. Vegaleal 1 1Dpto. de Ing. Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain 2Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM. Abstract Two new class AB output stages for CMOS opamps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Simulation results are provided that are in good agreement with expected values. I. Introduction The market of portable electronic equipment has pushed industry to produce circuit designs with very low supply voltage. Although two oxides are presently available in some analogue technologies, digital compatibility forces analogue circuits to operate with supply voltages close to a transistor threshold voltage. Several low-voltage (VDD < 1.5V) class- AB op-amp schemes have been recently reported [1]-[4]. The Monticelli´s scheme [1] for quiescent currrent control (figure 1a) uses two complementary head-to-tail connected transistors and two matched current sources to implement a floating voltage source (figure 1b). This scheme achieves an accurate quiescent current control by means of a translinear loop at the expense of a high supply voltage (larger than two VGS). In [2] the (negative) floating voltage source of figure 1b was implemented with one current source and one transistor (figure 1c), although a complex control loop was required for quiescent current control. In [3], diode connected transistors acting as loads of simple common source amplifiers were used to bias the output transistors (figure 1d). Although the proposed stage is very simple, no a good class AB behavior was achieved and dependence on process variations was not fully eliminated. In [4] a folded version of the Monticelli’s output stage was proposed to achieve operation with low supply voltage (figure 1e). Other output stages using a feedback loop for quiescent current control can also be found in the literature, but they have a slower speed and may have stability problems because of the feedback loop. Moutn Moutp Vout Ib Vx+ - VAB a) b) c) Moutn Moutp X VAB Vout + - Moutp Vout Moutn Iin Ib Ib I1 I1 X Moutp Vout Moutn Ib Vbp Vbn X d) e) Moutp Vout Moutn Ib I1 Ib I1 X Figure 1: Low-voltage class-AB output stages: a) [1], b) basic circuit, c) [2], d) [3], e) [4]. II. Proposed class AB output stages and quiescent current control In this paper two new CMOS class AB output stages for continuous-time operation are presented with simple and accurate quiescent current control (figures 2a and 3). a) First output stage (figure 2a). Figure 2a shows the first proposed output stage and figure 2b its biasing circuit for quiescent current control. The proposed stage uses resistor R and current sources Ir to implement the floating voltage source VAB of figure 1b. The input and output terminal voltages are VX and Vout .Cross connecting terminals X and Y to the gates of transistors Moutp and Moutn, respectively, allows the supply voltage to be close to a transistor threshold voltage. For larger supply voltages a straight connection of these terminal should be done. In figure 2b, transistor M1 and current source I1 determine V1=VXQ (upper index Q means quiescent value), while transistor M2 and current source I2 = I1 determine V2=VYQ. The resistor R' and the differential amplifier DA driving two matched current sources Ir' constitute a voltage-to-current converter [6], so that Ir' = - VAB / R' = ( VYQ – VXQ ) / R' . This floating voltage source VAB is replicated in figure 2a, by means of matched resistor R and current sources Ir. In a real implementation, to reduce power consumption, M1 (M2) and I1 = I2 would be a scaled version of Moutp (Moutn) and IMoutpQ = IMoutnQ , respectively.. Figure 2c shows a practical implementation of the whole output stage, where the amplifier DA of figure 2b has been implemented by means of a simple pMOS differential amplifier. Bottom current sources Ir and Ir’ have been implemented by means of a low voltage current mirror, allowing operation with less than 1V supply voltage. Note that the circuit in figure 2c maintains its operation independent on the supply voltage, as long as VAB remains negative (which approximately means VDD < 2 V in our technology). For larger supply voltages, the polarity of the floating voltage sources can be reversed by changing the role of nodes X-Y. Moutn Moutp Vout R Ir Ir X + - VAB Y R' Ir ' + - VAB +- Ir ' I1 I2I1 = V2 M2 M1V1DA R' I1 I2I1 = M2 M1 Moutn Moutp Vout R X + - VAB Y Ic 2 Ic V1V X Q = (b) (a) (c) Figure2: First proposed class-AB output stage: a) Basic idea, b) dynamic biasing circuitry, c) practical implementation. b) Second output stage (figure 3) The second proposed output stage is shown in figure 3. In this figure, the bias current Io in the low voltage differential pairs M1p-M3p and M1n-M3n [5] accurately determines the quiescent output current IoutQ = IMoutnQ = IMoutpQ =2αIo. Furthermore, the minimum current in the output transistors is given by IoutMIN = IMoutnMIN = IMoutpMIN =αIo . Note that IoutQ and IoutMIN do not depend on the value of the floating voltage sources VAB, which is selected to allow an accurate copy of currents IM3p and IM3n to transistors Moutp and Moutn, respectively. Under quiescent conditions, if |VAB| was too large, transistors M3p and M3n would not be in saturation. On the other hand, if |VAB| was too small, transistors M1p-M2p and M1n-M2n would operate in linear region. Appropriate values for VXQ and VYQ are: VXQ = VDD - VSGM1pQ - VDSsat - ∆VXMAX / 2, and VYQ = VGSM1nQ + VDSsat + ∆VXMAX / 2 , where ∆VXMAX is the maximum expected variation for the input node voltage VX . As a result, an appropriate value for VAB= VXQ – VYQ = VDD - VGSM1nQ - VSGM1pQ - 2VDSsat - ∆VXMAX . If the input node VX in figure 3 is the first stage output of an op-amp, negative feedback reduces ∆VXMAX to only a few mV so that, for a 0.8 µm CMOS technology with 0.8 V of transistor threshold voltages, VDD - VAB is in the order of 1.8 to 3 V depending on transistor sizes and biasing currents. According to this reasoning, this stage can be operated with less than 1 V supply voltage and VAB = - 0.8 V . Note that this stage can be also operated with a high supply voltage if VAB is positive. The same dynamic biasing scheme of figure 2b can be used to generate the floating voltage sources VAB between nodes X-Y and W-Z by means of two matched (and, normally scaled) replicas of current sources Ir' and resistor R'. Moutp Vout Moutn Io X Io + - + - Y W Z M1p M1n M2n M2p "" : 1 "" : 1 VAB VAB Moutn I Moutp I M3p M3n Figure 3: Second proposed class-AB output stage III. Simulation results The proposed output stages have been simulated with HSPICE and the parameters of a standard 0.8 µm CMOS technology whose transistor threshold voltages are in the order of 0.85 V. Design parameters for the first output stage (figure 2) are resumed in Table I. Figure 5a presents the transistor currents IMoutp and IMoutn for VX in the range [0.45V, 0.9V], with VDD=1.5V showing a typical class AB behavior. The quiescent output current IoutQ of 103.9 µA is in good agreement with the expected value (100 µA). Figure 5b shows the output stage transistor currents IMoutp and IMoutn and voltage –VAB = VY – VX for a supply voltage that follows a 1 KHz, 20mV peak-to-peak triangular signal showing an excellent PSRR. RcCc Min2 Min1 Idp Idp 2 + Output Stage (figure 2a or 3) - VCM-ADJ Vout CL Vin X Figure 4: Simple op-amp in voltage follower configuration for testing output stages performances. An op-amp was built using the proposed output stage with a simple pMOS differential pair as input stage. This opamp can be used for very low voltage switched op-amp applications using the scheme proposed in [7] or in sampleddata and continuous-time applications with the dc level shift in the input stage provided by the circuit proposed in [2]. For the sake of simplicity, the op-amp was simulated in a voltage follower configuration (figure 4) with 0.15 V of quiescent input voltage, allowing up to 0.4 V peak input signal with 1.5 V supply. Figure 5c shows the transient response with a 0.3 V peak, 1.67 MHz square input signal. Note that a slew rate of 12 V/µs was achieved. Intermediate column in Table II resumes simulated op-amp performances. Moutn I Moutp I V X (a) Moutn I Moutp I VYVX (b) V out (c) Figure 5: Simulation results for the first proposed output stage: a) Class AB behaviour, b) Output stage transistor currents and -VAB for a 1kHz triangular signal superimposed on supply voltage, c) transient response. The same simulations were repeated for the second proposed output stage (figure 3). Figure 6a shows the transistor currents IMoutp and IMoutn for VX in the range [0.1V, 0.7V], with VDD=1.5V. In this case, not only IoutQ but also IoutMIN are accurately determined by the biasing circuitry. Figure 6b shows the output stage transistor currents IMoutp and IMoutn and voltages VY – VX and VZ – VW for a supply voltage that follows a 1 KHz, 20mV peak-to-peak triangular signal. An op-amp was also built with a pMOS differential input stage and simulated in a voltage follower configuration(figure 4). Figure 6c shows the transient response with a 0.3 V peak, 1.67 MHz square input signal. Last column in Table II resumes simulated op-amp performances. Moutn I Moutp I V X (a) Moutn I Moutp I VYVX VZVW (b) Vout (c) Figure 6: Simulation results for the second proposed output stage: a) Class AB behaviour, b) Output stage transistor currents and –VAB for a 1kHz triangular signal superimposed on supply voltage, c) transient response. IV. Conclusions Two new low voltage output stages have been proposed for class-AB CMOS opamps. A new dynamic biasing technique allows an accurate quiescent current control and provides good PSRR. The second proposed stage also allows to set the minimum current through output transistors, which is a very convenient property for class-AB output stages. Simulation results show the class-AB behavior of proposed stages. References [1]MONTICELLI, D.M.: "A quad CMOS singlesupply op amp with rail-to-rail output swing". IEEE J. of Solid-State Circuits, 1986, SC-21, (6), pp. 1026-1034. [2]RAMÍREZ-ANGULO, J., CARVAJAL, R.G:, TOMBS, J., and TORRALBA, A.: “A simple technique for opamp continuous-time 1 V supply operation”, Electron. Lett., 1999, 35, (4), pp. 263-264. [3]YOU, F., EMBABI, S.H.K., and SÁNCHEZSINENCIO, E.: “Low-voltage class AB buffers with quiescent current control”, IEEE J. of Solid- State Circuits, 1998, SC-33, (6), pp. 915-920. [4]DE LANGEN, and HUISING, H.J.: “Compact low-voltage power-efficient operational amplifier cells for VLSI”, IEEE J. of Solid-State Circuits, 1998, SC-33, (10), pp. 1482-1496. [5]PELUSO, V., VANCORELAND, P., MARQUES, A.M., STEYAERT, M.S.J., and SANSEN, W.: “A 900-mV low-power ∆Σ A/D converter with 77-dB dynamic range”, IEEE J. Solid-State Circuits, 1998, SC-33, (12), pp. 1887-1897. [6]RAMÍREZ-ANGULO,J., TORRALBA, A., and CARVAJAL, R.G.: “Low-voltage CMOS amplifiers with wide input-output voltage swing based on a novel scheme”, to be published in IEEE Trans.on CAS-II, 2000, CASI-47 (5). [7] BASCHIROTTO, A., CASTELLO, R., and MONTAGNA, G.P: “Active series switch for switched opamp circuits”, Electron. Lett., 1999, 35, (4), pp. 263-264. Units Output Stage of figure 2c Output Stage of figure 3 Moutn W/L 500/1 500/1 Moutp W/L 165/1 165/1 R,R’ kΩ25 25 M1W/L 50/1 20/1 M2W/L 16.5/1 6/1 I1= I2µA 10/1 10/1 Min1, Min2 W/L 500/1 500/1 Idp µA 200 200 M1p, M2p W/L -25/1 M3p W/L -50/1 M1n, M2n W/L -8/1 M3nW/L -16.5/1 IoµA -5 Table I. Op-amp design parameters. Units Output Stage of figure 2c Output Stage of figure 3 DC Gain dB 67 60 Phase Margin o70o60º Unity Gain fequency MHz 18 20 Quiescent output current (µA) 104 117 Minimum output current (µA) 0 52 Supply current (µA) 332 387 PSRR dB 40 38 CMRR dB 45 45 THD (1kHz) dB 65 60 Input referred noise (100kHz) nV2/Hz 17 21 Slew Rate * V/µs 12 14 Peak output Current * µA 600 500 Table II. Simulated performances (CL=10pF, VDD=1.5, CC=10pF, RC=500Ω, VCM-ADJ=600mV) (*) Transient response, 0.3V peak square input signal