In vivo measurements with a 64-channel extracellular neural recording integrated circuit

In i o measu emen s wi h a 64-channel ex acellula neu al eco ding in eg a ed ci cui Manuel Delgado-Res i u o, Albe o Rod íguez-Pé ez, Angela A. Da ie and Ángel Rod íguez-Vázquez Ins i u e o Mic oelec onics o Se ille (IMSE-CNM) CSIC, Uni e si y o Se ille Email: {mandel, albe o, angela, angel}@imse-cnm.csic.es C is ina So o-Sánchez and Edua do Fe nández-Jo e Bioenginee ing Ins i u e, Uni e si y Miguel He nandez Email: {cso o, e. e nandez}@goumh.umh.es Abs ac —This pape p esen s in i o measu emen s ob ained om an implan able 64-channel neu al eco ding Applica ion Specific In eg a ed Ci cui (ASIC) de eloped a IMSE and gi es de ails o he compu e in e ace used o eal- ime da a acquisi ion. This in e ace connec s he ASIC o a con en ional 2.0 USB po by means o a Field P og ammable Ga e A ay (FPGA). Communica ions a e bidi ec ional and employ cus om p o ocols bo h o deli e ing commands o he ASIC and o eco ding neu al in o ma ion unde di e en channel selec ion and ope a ion modes. The link is con olled by a use - iendly p og amming in e ace w i en in C++ which includes a buil -in ou ine o e ficien ly index and s o e he cap u ed da a. Mesu e- men s demons a e he sui abili y o he ASIC o cap u ing local field and ac ion po en ials wi h wo di e en mic oelec ode a ay pla o ms. I. INTRODUCTION In ecen yea s, ad ances in echnology ha e made i possible o moni o bioelec ic b ain ac i i y using de ices physically implan ed in he pa ien [1]–[3]. Thanks o he use o elec ode a ays wi h in e -elec ode sepa a ion in he o de o ens o mic ons and bandwid hs in he kH ange, such de ices o e much highe le els o spa io- empo al de ail han hose achie able wi h elec oencephalog aphy (EEG). This inc ease in esolu ion is allowing specialis s o p esc ibe mo e a ea-specific ea men and e en de elop new he apeu ic p o- cedu es. Implan ed closed loop neu omodula ion sys ems, o example, can alle ia e he ad e se e ec s o ce ain illnesses, such as he mo o dys unc ion caused by Pa kinson’s disease, o p edic and coun e ac epilep ic seizu es [4]. Fu he , e fi- cien moni o ing o b ain signals om implan ed de ices is a key ac o in he de elopmen o b ain-machine in e aces in which app op ia ely ins umen ed objec s can be con olled exclusi ely by a pe son’s hough s, hus imp o ing he quali y o li e o pa ien s wi h se e e mobili y impai men s [5]. In his pape , in i o measu emen s ob ained om an im- plan able 64-channel neu al eco ding sys em p o o ype de el- oped a IMSE a e p esen ed. The mos salien ea u es o his p o o ype, as well as i s implemen a ion de ails, we e b iefly desc ibed in [6]. He ein, a en ion is paid on he bidi ec ional wi e line in e ace used o communica e he p o o ype wi h a compu e in o de o configu e he eco ding sys em and s o e he acqui ed neu al in o ma ion. Al hough he p o o ype also includes modules o wi eless da a and powe ans e , Figu e 1. Mic opho og aph o he mul ichannel neu al eco ding a ay p o o ype. in he p esen ed expe imen s, we ha e conside ed a wi eline app oach as a fi s s ep owa ds assessing he ull unc ionali y o he p o o ype. Such wi eline in e ace has been implemen ed by means o a Field P og ammable Ga e A ay (FPGA) and uses a con en ional 2.0 USB po o communica e wi h he hos compu e . Fo he sake o comple eness, a sho e iew o he ab- ica ed 64-channel neu al eco ding sys em is p esen ed in Sec ion II and, a e wa d, a desc ip ion o he expe imen al se up o he in i o measu emen s is gi en in Sec ion III. Then, he FPGA-based in e ace is desc ibed in Sec ion IV including de ails o he ASIC p og amming ha dwa e and he da a eco ding module. Sec ion V p esen s some o he in i o neu al eco ding measu emen s using animal models ob ained in he Ins i u e o Bioenginee ing in Elche (Spain). They consis o local field po en ials (LFPs) cap u ed wi h a sub-du al mic oelec ode a ay and ac ion po en ials (APs) eco ded wi h an in aco ical U ah a ay. Finally, Sec ion VI ends he pape wi h some conclusions. II. NEURAL RECORDING SYSTEM Fig. 1 shows a mic opho og aph o he 64-channel neu- al eco ding sys em, ab ica ed in a 1.2-V 130nm (6M2P) s anda d CMOS echnology. Each channel comp ises an ana- log on -end wi h p og ammable gain and unable bandpass cha ac e is ics o he acquisi ion and condi ioning o neu al signals; a local SAR-based analog- o-digi al con e e (ADC); 978-1-4799-4242-8/14/$31.00 c 2014 IEEE 486 a digi al module o he de ec ion and comp ession o ac ion po en ials; and means o empo a ily s o ing he a o emen- ioned in o ma ion. All hese in-channel unc ions, oge he wi h an in e nal pad o flip-chip connec ion, a e in eg a ed in an a ea o 0.16mm2. A dedica ed digi al p ocesso collec s and classifies he in o ma ion ga he ed by he channels be o e sending i ou ei he h ough an induc i e link o by means o a wi eline connec ion, as p esen ed in his pape . Addi ionally, he p ocesso ans e s pa ame e s o he channels, checks o digi al consis ency and p o ides in e nal iming e e ences om a single 4MHz mas e clock. This clock can be ex ac ed om he ca ie o he induc i e link o , as done in he p esen ed expe imen s, in oduced h ough a dedica ed pin. Besides a configu a ion phase in which he di e en chan- nels a e pa ame ized, he eco ding sys em o e s h ee op- e a ion modes. In one case, deno ed as calib a ion mode, he sys em sel -calib a es so ha he eco ding bandwid h o e e y selec ed channel is uned o he desi ed equency ange and he gain o hei on -ends is adjus ed o maximally co e he inpu dynamic ange o he local ADC. The second ope a ion mode, deno ed as signal acking mode, is in ended o s eam ou uncomp essed aw da a om he selec ed channels. Finally, in he las mode, deno ed as ea u e ex ac ion mode, he digi al comp ession modules o he selec ed channels a e ac i a ed and he de ec ed APs a e on- he-fly app oxima ed by piecewise-linea (PWL) ep esen a ions. Fo each selec ed channel, he AP de ec ion h eshold is adap i ely upda ed acco ding o he noise floo o he cap u ed signal. In his mode, a channel emains idle and, hence, i does no ansmi any in o ma ion, as long as no ac ion po en ial is de ec ed. The e o e, ac i i y in his mode is e en -d i en hus a o ing he educ ion o he sys em powe consump ion. The inpu /ou pu da a ames used o he configu a ion o he channels and he eco ding o in o ma ion o he di e en ope a ion modes we e p esen ed in [6]. In his pape , we ha e ocused on he signal acking mode, unde wo possible eco ding configu a ions: 1) T acking o he whole a ay (64 channels) a a h ough- pu a e pe channel o 4kS/s. Al hough his configu a- ion can be also used o de ec he p esence o spikes, i is mainly used o he eco ding o LFPs a which he high-pass and low-pass co ne s o he bandpass cha ac e is ic in e e y channel a e se o he lowes equencies possible (15Hz and 5.2kHz, espec i ely, in his p o o ype). I equi ed, he low-pass co ne o he bandpass cha ac e is ics can be digi ally mo e o -chip o lowe equencies a e downsampling and FIR fil e - ing he eco ded s eams. In he epo ed expe imen s, no ex a fil e ing is applied. 2) T acking pe ow/column (8 channels) a a h oughpu a e pe channel o 30kS/s. This is he de aul sampling a e in he AP ea u e ex ac ion mode (bandpass cha ac- e is ics se be ween 200Hz and 7kHz), bu i can also be used in acking mode o ully app ecia e he wa e o m de ails o he eco ded signals. No addi ional o -chip fil e ing is equi ed. FPGA USB Po Mic oelec ode a ay Communica ion module Dedica ed p ocesso Reco ding channels 64-channel neu al eco ding ASIC Figu e 2. Measu emen se up III. MEASUREMENT SETUP Fig. 2 shows he schema ic diag am o he measu emen se up used o in i o neu al eco ding. Two di e en ypes o mic oelec ode a ays (MEAs) o neu al eco ding we e used. In one case, a flexible sub-du al mic oelec ode a ay (Mul i Channel Sys ems MCS GmbH) wi h TiN elec odes sepa a ed by 300μm (diame e 30μm) placed on a polymide subs a e was used. The signals cap u ed by he mic oelec odes we e ans e ed o he 64-channel neu al eco ding sys em by means o fla ibbon cables connec ed be ween he MEA adap e (ADPT-FM-36, MCS GmbH) and he ASIC h ough ow p ecision socke s om Sam ec. In he second case, he MEA was a U ah a ay wi h an ICS-96 connec o (Black ock Mic osys ems LLC). A cus om adap e was designed o a anging he pin dis ibu ions o he ICS-96 connec o (only, banks A and C) so ha he same connec ion s a egy employed wi h he flexible MEA could be eused. A Field P og ammable Ga e A ay (Nexys™2 Spa an-3E FPGA Boa d by Digilen ) was used o communica e he 64- channel neu al eco ding ASIC wi h a hos compu e h ough a con en ional 2.0 USB po . A use in e ace de eloped in C++ was designed o con ol he whole measu emen se up. This in e ace compiles he Digilen DEPP Dynamic Link Lib a y [7] o access he USB d i e . The communica ions be ween he ASIC and he FPGA only need wo downwa d connec ions, o he command line and w i e enable signals, and one upwa d connec ion, o he ans e o he neu al in o ma ion eco ded and p ocessed by he ASIC. Addi ionally, a 4MHz mas e clock is ans e ed o iming pu poses. All expe imen al p ocedu es we e pe o med in con o - mance o he di ec i e 2010/63/EU o he Eu opean Pa liamen and o he Council, and he RD 53/2013 Spanish egula ion on he p o ec ion o animals use o scien ific pu poses and app o ed by he Miguel He nandez Uni e si y Commi ee o Animal use in Labo a o y. Animal models we e adul male Long E ans a s. IV. FPGA INTERFACE The pu pose o he FPGA boa d is o con ol and ans e he da a acqui ed by he 64-channel neu al eco ding ASIC. The FPGA boa d, p og ammed wi h he Xilinx ISE Design Sui e, implemen s wo majo blocks: (i) a con ol module in cha ge o sending configu a ion commands o he selec ed channels o he ASIC and (ii) a da a eco ding module which empo a ily s o es in in e nal RAMs he da a ecei ed om he ASIC and, a e wa d, deli e s he in o ma ion h ough he USB po . Bo h modules make use o a USB in e ace which implemen s he bidi ec ional communica ion be ween he FPGA boa d and he USB po . This in e ace consis s o a s a e machine wi h 8- 487 USB In e ace as b ds b db w w x_da a w _ eq x_da a x_ d USB PC Command Con olle ws en_pls din dou alid PISO 24 en DFF sync en_ Dou Din ASIC clk50M clk4M F eq. Di ide clk4M clk4M Dou Din En_ Figu e 3. Block and iming o he p oposed con olle uni . bi s bidi ec ional da a bus, fi e con ol signals and one clock signal (40MHz). A. Logic Con ol Module The logic con ol module, shown a he op o Fig. 3, enables he ex e nal ope a o o configu e he channels o he ASIC, h ough he Din se ial po , a ins ances o he con ol signal en_ . As desc ibed in [6], all configu a ion commands s a wi h a 5-bi s p eamble, ollowed by a payload o 14-bi s and a 5-bi s o Cyclic Redundancy Check (CRC). E e y ime he USB in e ace de ec s a w i e eques (w _ eq is ac i e) om he hos compu e i begins packing bi s in wo d ames. These ames a e hen ed in o a synch onous pa allel- inpu se ial-ou pu (PISO) egis e o se ializa ion. Signals inside he FPGA ha e o be ca e ully synch onized in o de o a oid ime ou e o s and/o incomple e command ans e s. To o e come hese issues, an in e nal con olle , clocked a 40MHz, igge s he con ol signal en_ only when he da a s o ed in he PISO egis e is alid. This con ol signal en_ , which defines he da a ans e window o he ASIC, emains ac i e as long as he con en o he PISO esis e is being dumped o he ASIC. The 4MHz mas e clock o he ASIC is de i ed by di iding he 50MHz FPGA clock. The ou pu s eam o he PISO egis e and he con ol signal en_ a e aligned o he mas e clock o he ASIC. The s a -up o he eco ding sys em in ol es h ee com- mands, as illus a ed in he bo om plo o Fig. 3. The fi s command is in ended o define he bandpass o he 64 channels included in he ASIC. Depending on he logic alue o a flag comp issed in he command s eam, his can be done ei he by di ec ly defining he p og amming wo ds o he highpass and lowpass co ne s o he channel’ fil e s o by unning a sel -calib a ion p ocess o e he whole a ay. In his la e case, aimed o coun e ac on-chip PVT a ia ions, a uning mechanism based on digi al equency syn hesis is enabled o au oma ically adjus ing he a o emen ioned p og amming wo ds o he desi ed fil e pole alues. The second command is in ended o calib a e he ol age gain o he channels o he la ges alue possible, a oiding he sa u a ion o he embedded da a con e e . Once comple ed his ope a ion, a hi d command selec s he channels o be eco ded and he acquisi ion commences. USB In e ace as b ds b db w w x_da a w _ eq x_da a x_ d USB PC D w _da a W i e Con ol clk50M clk4M 8 Mem slo #1 Mem slo #2 oggle d_en d_ F eq. Di ide DRead Con ol d_da a en_ Dou Din ASIC 8 FIFO RAM Figu e 4. Block diag am o he da a eco ding module. B. Da a Reco ding Module The da a eco ding module, shown in Fig. 4, enables o ans e he in o ma ion p o ided by he selec ed channels o he ASIC o a hos compu e . Fo he wo expe imen s unde signal acking mode desc ibed in Sec. II, ou pu da a ames coming om he ASIC ha e 85-bi s leng h. They consis o an 8-bi s p eamble, a 72-bi s in o ma ion packe , and a 5-bi s CRC checksum. Besides a code o he ope a ion mode (2- bi s), he in o ma ion packe con ains an iden ifie (6-bi s) o he column/ ow in he ASIC which is cu en ly ansmi ing in o ma ion and he digi ized sampled da a sen ou by he co esponding channels (8-bi s pe channel s eamed om MSB o LSB). Depending on whe he he iden ifie emains s a ic o uns cyclically o e he 8 columns/ ows o he a ay, he ASIC deli e s he eco dings om 8 cells a a h oughpu a e pe channel o 30kS/s o sweeps he whole a ay a a h oughpu a e pe channel o 4kS/s. A w i e con ol uni , synch onized o he 4MHz mas e clock, iden ifies and al e na i ely dumps he se ial ou pu ames o he ASIC in o wo memo y slo s which empo a ily s o e he neu al in o ma ion. E e y ime a new ame is ead and s o ed, he w i e con ol uni changes he s a e o he con ol signal, oggle. This same signal is used by a ead con ol uni , clocked a 50MHz, o e ie e he s o ed in o ma ion om ha memo y slo which is no unde ead ope a ion. Hence, while one o he memo ies is being w i en he o he is being ead, and ice e sa. Because o he di e en clocks used by he ead and w i e uni s, no in o ma ion is los . Addi ionally, he ead con ol uni ans e s he e ie ed in o ma ion o a fi s -inpu fi s -ou pu (FIFO) memo y in pa allel slo s o 8- bi s. Da a a e ans e ed om his memo y o he USB po du ing he ime in e als allowed by he p o ocol. V. IN VIVO RESULTS Fig. 5 shows 16 o he eco dings cap u ed by he ASIC when ope a ed in signal acking mode wi h he column scan- ning op ion enabled (64 channels acked a a h oughpu a e pe channel o 4kS/s). The flexible sub-du al mic oelec ode a ay desc ibed in Sec. III was used in his expe imen . Al hough he expe imen las ed o se e al hou s, only a 10s in e al is shown in Fig. 5; no subs an ial di e ences we e app ecia ed in he cou se o he measu emen , no among he channels. The a e age powe consump ion o he ASIC was 241μWwhich, acco ding o pos -layou simula ions, spli s in o some 194μW o he eco ding channels and abou 47μW o he embedded digi al p ocesso and he communica ion module oge he (see Fig. 2). 488 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 -500 0 500 0 1 2 3 4 5 6 7 8 9 10 -500 0 500 Time [s] 0 1 2 3 4 5 6 7 8 9 10 -500 0 500 Time [s] Figu e 5. LFP ac i i y eco ded om 16 channels in he in- i o es pe o med wi h he neu al eco ding a ay a ached o a flexible a ay o Mul iChannel Sys ems ( e ical axis in μV). Fig. 6 shows he 8 eco dings cap u ed by he ASIC when ope a ed in signal acking mode om a single column o he channel a ay (8 channels acked a a h oughpu a e pe channel o 30kS/s). In his case, he U ah a ay was employed in he in i o measu emen . As can be obse ed in Fig. 6, isola ed ac ion po en ials and bu s s o spikes a e clea ly no iceable in he 30ms eco ding. As in he p e ious case, no subs an ial di e ence om he shown pe o mance was obse ed along he expe imen . In his case, he a e age powe consump ion o he ASIC was 69μWwhich spli s in o some 24μW o he eco ding channels and abou 45μW o he digi al pe iphe y. I is wo h obse ing no majo di e ence on he powe consump ion o he digi al ci cui y was de ec ed as compa ed o he p e ious expe imen . This is because he lowe numbe o channels is coun e balanced by he highe da a a e. VI. CONCLUSIONS This pape p esen s in i o measu emen s ob ained om an implan able 64-channel neu al eco ding sys em p o o ype de eloped a IMSE. De ails a e gi en on he FPGA in e ace used o communica e he ASIC o a hos compu e . The implemen ed sys em is capable o acqui ing online da a om a ious channels o unlimi ed amoun o ime and i is ound sui able bo h o sub-du al and in aco ical eco dings. ACKNOWLEDGMENTS This wo k has been suppo ed by he Spanish Minis y o Economy and Compe i i eness unde g an TEC2012-33634 and he FEDER P og am. REFERENCES [1] X. Zou e al., “A 100-channel 1-mW implan able neu al eco ding IC,” IEEE T ansac ions on Ci cui s and Sys ems I: Regula Pape s, ol. 60, no. 10, pp. 2584–2596, Oc . 2013. [2] R. Mulle e al., “A minia u ized 64-channel 225 uW wi eless elec o- co icog aphic neu al senso ,” in Solid-S a e Ci cui s Con e ence Diges o Technical Pape s (ISSCC), 2014 IEEE In e na ional, Feb. 2014, pp. 412–413. -100 0 100 Ch #1 [μV] -100 0 100 Ch #2 [μV] -100 0 100 Ch #3 [μV] -100 0 100 Ch #4 [μV] -100 0 100 Ch #5 [μV] -100 0 100 Ch #6 [μV] -100 0 100 Ch #7 [μV] 0 5 10 15 20 25 30 -100 0 100 Ch #8 [μV] Time [ms] Figu e 6. Neu al spike ac i i y eco ded om 8 channels in he in- i o es pe o med wi h he neu al eco ding a ay a ached o a U ah a ay ( e ical axis in μV). [3] C. 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