Subsampling receivers with applications to software defined radio systems

TESIS DOCTORAL SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS José Ramón García Oya Sevilla, Noviembre de 2012 II SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS TESIS DOCTORAL SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS por José Ramón García Oya Ingeniero de Telecomunicaciones por la E.T.S. de Ingenieros de la Universidad de Sevilla Presentada en la Escuela Técnica Superior de Ingenieros de la Universidad de Sevilla Para la obtención del grado de Doctor por la Universidad de Sevilla Sevilla, Noviembre de 2012 IV SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS TESIS DOCTORAL SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Autor: José Ramón García Oya Director: Fernando Muñoz Chavero VI SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS VII ACKNOWLEDGMENTS Firstly, I would like to thank my supervisor Dr. Fernando Muñoz Chavero, for giving me the opportunity to research these interesting and challenging fields, as well as for his supervision, guidance, optimism and support to become an independent researcher. Also I am greatly grateful to Dr. Antonio Torralba Silgado, Dr. Ramón González Carvajal and the entire Electronics Engineer Group (GIE), for giving me the chance of requesting and being admitted for a public PhD scholarship in University Professor Training and Development, FPU (from the Spanish Formación de Profesorado Universitario), and for being able to develop my research in a friendly environment with high expertise. This PhD scholarship was founded by the Ministry of Education, Culture and Sports (previously named Ministry of Science and Innovation). I would like to thank the company AT4 Wireless, for the research works jointly carried out within the scopes of the Telmax Project (PI-0553/2007), and the Muphy Project (PI-0358/2009). The Telmax Project was partially funded by CDTI–Centro para el Desarrollo Tecnológico e Industrial–, of the Spanish Ministry of Science and Innovation, under the INGENIO 2010 Program/CENIT call. Moreover, the Muphy Project was partially funded by the Andalusian Regional Government (under the program entitled “Programa de Incentivos para el Fomento de la Innovación y el Desarrollo Empresarial de Andalucía”) and the Andalusian Technological Corporation (CTA). I wish to express my gratitude to Dr. David Hely and Dr. Fadhel M. Ghannouchi for accepting me to perform my international internships in the LCIS laboratories (INP, University of Grenoble) and iRadio Labs research group (Department of Electrical and Computer Engineering, University of Calgary), respectively. Specially, I would like to thank to Dr. Eduardo Mendes (Univeristy of Grenoble), Andrew Kwan and Dr. Seyed Aidin Bassam (University of Calgary) for their invaluable help to complete my thesis work. Finally, I want to thank all my friends and family, especially the people whom this work is dedicated, my parents and Stephanie. I have not enough words to thank you for everything, and much less in English. VIII Acknowledgments SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS IX RESUMEN DE LA TESIS La presente Tesis Doctoral propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de downconversion de los receptores de radio frecuencia empleados para aplicaciones multi-estándar y Software Defined Radio. Uno de los objetivos principales será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, se han seleccionado estas arquitecturas basadas en submuestreo, para las que es posible alcanzar un alto grado de reusabilidad de los componentes. De este modo, se reducirá el coste total del receptor de comunicación, así como de los equipos de test y certificación que emplean este tipo de arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como el objetivo del Software Defined Radio es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidor analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADCs no es posible implementar esta idea debido al alto ancho de banda que requieren, sin perder resolución, para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de receptores, debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando las arquitecturas propuestas, dicho componente procesará la señal a frecuencias intermedias con más altas prestaciones de resolución. Una vez se han introducido los conceptos principales del submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en este tipo de técnicas con la finalidad de ser implementada como receptor de test y certificación multi-estándar de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un sample & hold (S&H) de bajo jitter y de un ADC que trabaja a frecuencias intermedias. El prototipo es implementado usando dispositivos comerciales en una placa de circuito impreso, cuya caracterización experimental muestra una resolución de XVI Contents SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS XVII LIST OF TABLES Table 3.1 Valid sampling ranges and optimal sampling frequency for an input signal at 1070 MHz and signal bandwidth equal to 20 MHz .......................................................... 66 Table 4.1 System performance at COTS level ................................................................ 101 Table 4.2 System performance at PCB level .................................................................. 103 Table 4.3 System performance using multiple clocking at COTS level ......................... 108 Table 4.4 Standards specifications and results at COTS level ........................................ 110 Table 4.5 System performances using multiple clocking at PCB level .......................... 111 Table 4.6 Standard specifications and results ................................................................. 115 Table 5.1 The boundary constraints for the dual band case ............................................ 124 Table 5.2 Valid sampling frequencies below 2 GHz ...................................................... 126 Table 5.3 Dual band signal construction table ................................................................ 138 Table 5.4 Subsampling receiver’s architectures.............................................................. 140 Table 5.5 Comparative between expected and experimental SNR ................................. 143 Table 8.1 Designs rules ................................................................................................... 178 Table 8.2 Impedance calculation .................................................................................... 179 XVIII List of tables SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS XIX LIST OF FIGURES Figure 1.1 Classic SDR architecture ................................................................................. 28 Figure 2.1 SDR Evolution ................................................................................................. 38 Figure 2.2 Block diagram of Primary Signal Processing Tasks in a typical transmitter and receiver .............................................................................................................................. 39 Figure 2.3 Conceptual diagram of the two-stages down-conversion superheterodyne receiver .............................................................................................................................. 43 Figure 2.4 Conceptual diagram of the two-stages down-conversion superheterodyne receiver with the second IF equal to DC ........................................................................... 43 Figure 2.5 Conceptual diagram of the two-stages down-conversion superheterodyne receiver with the second IF translated to DC digitally ...................................................... 44 Figure 2.6 Hartley’s receiver architecture ......................................................................... 45 Figure 2.7 Weaver’s receiver architecture ........................................................................ 45 Figure 2.8 Conceptual diagram of the zero IF receiver architecture ................................. 47 Figure 2.9 Conceptual diagram of the low IF receiver architecture.................................. 48 Figure 2.10 Conceptual diagram of the low IF receiver architecture with polyphase filtering .............................................................................................................................. 49 Figure 2.11 Conceptual diagram of the double low IF receiver ....................................... 49 Figure 2.12 Conceptual diagram of the wideband IF receiver architecture with double conversion ......................................................................................................................... 50 Figure 2.13 Conceptual diagram of the subsampling receiver architecture ...................... 51 Figure 2.14 Conceptual diagram of the subsampling architecture with an intermediate down-conversion ............................................................................................................... 52 Figure 2.15 Conceptual diagram of the receiver based on interleaving architecture ........ 53 Figure 2.16 Multi-standard frequency spectrum ............................................................... 54 Figure 2.17 Multi-standard receiver architecture by zero IF ............................................ 55 Figure 2.18 Multi-standard receiver architecture by low IF ............................................. 56 Figure 3.1 A typical wireless link ..................................................................................... 61 Figure 3.2 Time domain representation of (a) 200 Hz continuous sine wave (b) sampled at 10 kHz and (c) sampled at 2 kHz ...................................................................................... 62 Figure 3.3 Sampling of a signal using (a) fs >> BW (b) fs = BW and (c) fs < BW .............. 64 Figure 3.4 Illustration of the concept of subsampling: (a) Frequency domain representation of the RF passband input signal along with the subsampling frequency and S&H harmonics and (b) signal replicas following subsampling process when selecting fs=(fc-fif)/k and fs>BW ........................................................................................................ 65 Figure 3.5 Output spectrum of the subsampler when the 1070 MHz RF signal is subsampled at a fs of (a) 475.56 MHz (modd=9 and fif=118.89 MHz) and (b) 480 MHz (modd=9 and fif=110 MHz) ................................................................................................. 67 XX List of figures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 3.6 Continuous signal spectrum where subsampling is not posible because fcBW<BW ............................................................................................................................ 67 Figure 3.7 Subsampling receiver scheme .......................................................................... 68 Figure 3.8 Concept of jitter ............................................................................................... 68 Figure 3.9 SNR requirements as a function of the jitter for different input frequencies ... 71 Figure 3.10 Phase noise for a clock frequency equal to 1.9 GHz ..................................... 72 Figure 3.11 Phase noise of an oscillator ............................................................................ 74 Figure 3.12 Block diagram of a PLL ................................................................................. 74 Figure 3.13 Phase noise of a PLL ..................................................................................... 75 Figure 3.14 (a) Model of the S&H, (b) thermal noise folded in the band of interest and (c) effective noise bandwidth.................................................................................................. 76 Figure 3.15 Thermal noise effect depending on the sampling frequency ......................... 77 Figure 3.16 Bandpass anti-aliasing filtering requirements in subsampling ...................... 78 Figure 3.17 IF subsampling receiver ................................................................................. 78 Figure 3.18 Block diagram of a continuous-time bandpass Σ∆ modulator ....................... 79 Figure 3.19 RF subsampling multi-standard Σ∆ receiver ................................................. 80 Figure 3.20 Subsampling based receiver for spectrum sensing ........................................ 81 Figure 3.21 Digital pre-distortion idea .............................................................................. 82 Figure 3.22 Dual-band digital predistortion with subsampled feedback loop ................... 83 Figure 4.1 Used coaxial components ................................................................................ 90 Figure 4.2 S&H THD for the input range 1.1-3.2 GHz ..................................................... 91 Figure 4.3 THD measured and provided by the manufacturer .......................................... 92 Figure 4.4 Block diagram of the implemented system ...................................................... 94 Figure 4.5 Implemented signal path at COTS level .......................................................... 94 Figure 4.6 ENOB vs. input amplitude for a input signal frequency of 1001 MHz and a sampling frequency of 445.3 MHz .................................................................................... 95 Figure 4.7 Measured SFDR vs. input signal amplitude .................................................... 96 Figure 4.8 Measured IM vs. input amplitude .................................................................... 97 Figure 4.9 Measurement of the overlapping thermal noise: ENOB obtained for different optimal sampling frequencies ............................................................................................ 98 Figure 4.10 Output spectrum of a 2001 MHz input signal subsampled at 470.8 MHz ..... 98 Figure 4.11 Output spectrum of a 2001 MHz input signal subsampled at 216.3 MHz ..... 99 Figure 4.12 Measurement of the jitter noise: ENOB obtained for different input frequencies ........................................................................................................................ 99 Figure 4.13 ENOB vs. input frequency ........................................................................... 100 Figure 4.14 Output spectrum for a 3 GHz input frequency ............................................. 101 Figure 4.15 Block diagram and designed PCB prototype ............................................... 102 Figure 4.16 Implemented stack-up .................................................................................. 103 Figure 4.17 ENOB vs. input frequency (20 MHz signal band, up to 20 GHz input carrier frequency) ....................................................................................................................... 104 Figure 4.18 Clocking schemes for: (a) a unique clock and (b) two different clocks....... 105 Figure 4.19 Implemented multiple clock system ............................................................ 107 Figure 4.20 ENOB obtained at COTS level for a multiple clocking architecture ........... 109 Figure 4.21 Measurement of the folded noise effect (ENOB vs. Optimal sampling frequencies) ..................................................................................................................... 109 Figure 4.22 Obtained ENOB in function of the input frequency .................................... 111 List of figures XXI SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.23 Multi-standard receiver architectures proposed in [4.38] (a) and [4.39] (b) 114 Figure 5.1 Subsampling receiver in multi-band nonlinear environment ......................... 122 Figure 5.2 (a) Frequency locations in the sampled output spectrum and (b) Spectrum of the dual band RF signal at the input of the S&H with ratio R1=f2/f1 ............................... 123 Figure 5.3 Power spectrum at the input (top) and the output (bottom) of a nonlinear system ............................................................................................................................. 125 Figure 5.4 Subsampled spectrum for 1.82 and 2.4 GHz input frequency ....................... 126 Figure 5.5 Subsampling applications for multi-band and nonlinear systems in the transmitter and receiver sides .......................................................................................... 127 Figure 5.6 (a) Subsampling based receiver for spectrum sensing in cognitive radio systems and (b) measurement setup for validating spectrum sensing concept using subsampling receiver ...................................................................................................... 128 Figure 5.7 Spectra of (a) the input RF signal to the receiver and (b) the subsampled RF signal for bands (698-752 MHz, 902-928 MHz) using a subsampling frequency of 255 MHz ................................................................................................................................ 129 Figure 5.8 Spectra of the input and filtered output baseband signals for the 698-752 MHz band (a) and 902-928 MHz band (b) ............................................................................... 129 Figure 5.9 The (a) predicted RF fundamental and harmonics up to 4 GHz and (b) subsampled result using a sampling frequency of 619.8 MHz ....................................... 131 Figure 5.10 (a) RF spectra at the output of the PA and (b) normalized spectra of the captured subsampled signal using an ADC operating at 619.8 MHz ............................. 132 Figure 5.11 Folded noise effects using single clock (a) and multiple clock (b) ............. 133 Figure 5.12 Folded effects for harmonics and intermodulation products using a single clock (a) and multiple clock (b) techniques .................................................................... 134 Figure 5.13 Optimized architecture based on multiple clocking and BP filters ............. 134 Figure 5.14 Algorithm flow diagram for computing optimal subsampling frequencies in the proposed architecture ................................................................................................ 136 Figure 5.15 Expected SNR (a) for single and multiple clock architectures and (b) for different architectures based on BP filters ...................................................................... 139 Figure 5.16 Experimental setup for dual band subsampling receiver ............................. 140 Figure 5.17 Simulated spectra after two-stage subsampling process, using a S&H subsampling frequency of 1900 MHz, ADC subsampling frequency of 400 MHz, and signal bands at 2.12 GHz and 2.4 GHz ........................................................................... 141 Figure 5.18 Experimental spectra after two-stage subsampling process, using a S&H subsampling frequency of 1900 MHz, ADC subsampling frequency of 400 MHz, and signal bands at 2.12 GHz and 2.4 GHz ........................................................................... 141 Figure 5.19 Theoretical SNR for the proposed architectures .......................................... 142 Figure 5.20 Experimental SNR for the proposed architectures (for design 2 and 4, no subsampling frequency could be found for scenarios 1, 2 and 3) ........................................ 142 Figure 7.1 Output spectrum of 2-interleaved ADCs (fc=6 GHz, fs=2.8 GHz) ................. 156 Figure 7.2 Output spectrum of 3-interleaved ADCs (fc=6 GHz, fs=2.3 GHz) ................. 156 Figure 7.3 Output spectrum of 4-interleaved ADCs (fc=4 GHz, fs=1.6 GHz) ................. 157 Figure 7.4 Output spectrum without implementing calibration ...................................... 158 Figure 7.5 Output spectrum after calibrating two couples of ADCs ............................... 159 Figure 7.6 Measured resolution for four interleaved ADCs ........................................... 159 XXII List of figures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 7.7 (a) Three ADCs (ABC) for three times sampling rate, (b) Three ADCs (ABC) for a double sampling rate ............................................................................................... 161 Figure 7.8 Example of a structure with extra ADCs ....................................................... 162 Figure 7.9 Random clock for 5 ADCs ............................................................................. 162 Figure 7.10 Functional diagram using digital filters blocks ............................................ 164 Figure 7.11 Architectures based on: (a) one S&H and (b) several sub-S&H .................. 166 Figure 7.12 Architecture based on double sampling ....................................................... 166 Figure 8.1 Block diagram of the proposed system .......................................................... 172 Figure 8.2 BGA dimensions for the Inphi 1821TH ......................................................... 172 Figure 8.3 Pinout of E2V AT84AS001 ........................................................................... 173 Figure 8.4 Proposed schematic: page 1 ........................................................................... 174 Figure 8.5 Thru-line loss calibration ............................................................................... 174 Figure 8.6 Proposed schematic: page 2 ........................................................................... 175 Figure 8.7 Proposed schematic: page 3 ........................................................................... 176 Figure 8.8 Proposed schematic: page 4 ........................................................................... 176 Figure 8.9 Proposed schematic: page 5 ........................................................................... 177 Figure 8.10 Proposed schematic: page 6 ......................................................................... 177 Figure 8.11 Proposed stack-up ........................................................................................ 181 Figure 8.12 Drill chart ..................................................................................................... 182 Figure 8.13 VIA with minimum size .............................................................................. 182 Figure 8.14 ADC fanout .................................................................................................. 183 Figure 8.15 VIAs array strcucture ................................................................................... 183 Figure 8.16 VIA employed in SMA connections ............................................................ 184 Figure 8.17 VIA employed in power supplies connections ............................................ 184 Figure 8.18 Top functionality .......................................................................................... 185 Figure 8.19 Top functionality (II) ................................................................................... 185 Figure 8.20 Bottom functionality .................................................................................... 186 Figure 8.21 Power supplies in layer VCC1 ..................................................................... 186 Figure 8.22 Power supplies in layer VCC2 ..................................................................... 187 Figure 8.23 Prototype dimensions ................................................................................... 187 XXIII LIST OF ACRONYMS ADC Analog to Digital Converter AGC Automatic Gain Control ASIC Application Specific Integrated Circuit AWGN Additive White Gaussian Noise BER Bit Error Rate BGA Ball Grid Array BoM Bill of Materials BP Band Pass BPS Band Pass Sampling BW Bandwidth CMOS Complementary Metal-Oxide Semiconductor COTS Commercial Off The Shelf CPLD Complex Programmable Logic Device CR Cognitive Radio DAC Digital-to-Analog Converter DDC Digital Down Converter DDS Direct Digital Synthesizer DPD Digital Pre-Distorter DSP Digital Signal Processing EMI Electromagnetic Interference ENOB Effective Number Of Bits FFT Fast Fourier Transform FPGA Field Programmable Gate Array XXIV List of acronyms SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS FR4 Flame Retardant 4 GP General Purpose IC Integrated Circuit IF Intermediate Frequency IMD3 3rd order Intermodulation Distortion I-Q In-phase and Quadrature IRF Image Rejection Filter LNA Low Noise Amplifier LO Local Oscillator LP Low Pass LPS Low Pass Sampling LSB Least Significant Bit LVDS Low-Voltage Differential Signaling MOS Metal-Oxide Semiconductor NF Noise Figure PA Power Amplifier PCB Printed Circuit Board PLL Phase-Locked Loop PSD Power Signal Density RD Receiver Design RF Radio Frequency SAW Surface Acoustic Wave SDR Software Defined Radio SFDR Signal Free Dynamic Range SMA Subminiature version A SMD Surface Mount Device SNDR Signal-to-Noise and Distortion Radio List of acronyms XXV SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS SNR Signal-to-Noise Ratio S&H Sample & Hold THD Total Harmonic Distortion UWB Ultra Wideband VCO Voltage Control Oscillator VCXO Voltage Control Crystal Oscillator VIA Vertical Interconnect Access VLSI Very-Large Scale Integration WPAN Wireless Personal Area Network 32 Chapter 1: Introduction SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 1.4 References [1.1] R. Bagheri et al., “An 800 MHz-6 GHz Software-Defined Wireless Receiver in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, j.41, no.12, pp. 2860-2876, Dec. 2006. [1.2] F. Agnelli et al., “Wireless Multi-Standard Terminals: System Analysis and Design of a Reconfigurable RF Front-End,” IEEE Circuits and Systems Magazine, vol. 6, no.1, pp. 38-59, Jan. 2006. [1.3] F. Svelto, M. B. Vahidfar, M. Brandolini, “Reconfigurable Si RF Receiver Front-Ends for Multistandard Radios”, 1st European Conference on Wireless Technology, (EuWiT 2008), pp.33-36, 2008. [1.4] M. Brandolini, P. Rossi, D. Manstretta, F. Svelto, “Toward Multistandard Mobile Terminals-Fully Integrated Receivers Requeriments and Architectures”, IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, March 2005. [1.5] M. Vidojkovic, M. A. T. Sanduleanu, V. Vidojkovic, J. van der Tang, P. Baltus, A. H. M. van Roermund, “A 1.2V Receiver Front-End for Multi-Standard Wireless applications in 65nm CMOS LP”, 34th European Solid-State Circuit Conference (ESSCIRC 2008), pp. 414417, 2008. [1.6] R. Barrak, A. Ghazel, F. Ghannouchi, “Optimized Multistandard RF Subsampling Receiver Architecture,” IEEE Transactions on Wireless Communications, vol. 8, no. 6, pp. 2901-2909, Jun. 2009. [1.7] J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado, A. J. Garrido, J. Baños, “Data Acquisition System Based on Subsampling for Testing Wideband Multistandard Receivers," IEEE Transactions on Instrumentation and Measurements, vol. 60, no. 9, pp. 3234-3237, Sep. 2011. [1.8] J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado, F. Márquez, E. López-Morillo, “Data Acquisition System Base on Subsampling using Multiple Clocking Techniques,” IEEE Instrumentation and Measurements, vol. 61, no. 8, pp. 2333-2335, Aug. 2012. [1.9] J. Mitola, “The Software Radio Architecture” IEEE Communications Magazine, vol. 33, no. 5, pp. 26-38, May 1995. [1.10] F. Harris, R.W. Lowdermilk, “Software Defined Radio: Part 22 in a Series of Tutorials on Instrumentation and Measurement,” IEEE Instrumentation & Measurement, vol. 13, no. 1, pp. 23-32, Feb. 2010. Chapter 1: Introduction 33 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [1.11] S. Haykin, “Cognitive Radio: Brain Empowered Wireless Communications”, IEEE Journal on Selected Areas in Communication, j. 48, no. 2, pp. 201-220, 2005. [1.12] F. K. Jondral, “Software-defined radio: basics and evolution to cognitive radio,” IEEE EURASIP, vol.3, pp. 275–283, Aug. 2005. [1.13] N. Vun, A. B. Premkumar, “ADC Systems for SDR Digital FrontEnd,” Proceedings of the Ninth International Symposium on Consumer Electronics (ISCE 2005), pp. 359-363, 2005. [1.14] C. R. Anderson, S. Venkatesh, J. E. Ibrahim, R. M. Buehrer, J. H. Reed, “Analysis and Implementation of a Time-Interleaved ADC Array for a Software-Defined UWB Receiver,” IEEE Transactions on Vehicular Technology, vol. 58, no. 8, pp. 4046-4063, Oct. 2009. [1.15] M. B. Romdhane, P. Loumeau, “Analog to Digital Conversion specifications for Ultra Wide Band reception,” Proceedings of the Fourth IEEE International Symposium on signal Processing and Information Technology, pp. 157-160, 2004. [1.16] A.A. Abidi, “Direct-conversion radio transceivers for digital communications," IEEE Journal of Solid-State Circuits, vol. 30, no. 12, Dec. 1995. [1.17] J. Crols, M. Steyaert, “Low-IF topologies for high-performance analog front-ends for fully integrated receivers," IEEE Journal of Solid-State Circuits, vol. 45, no. 3, Mar. 1998. [1.18] D. Grace, S. P. Pitt, “Quadrature sampling of high frequency waveforms," Journal of the Acoustical Society of America, vol. 44, pp. 1432-1436, 1968. [1.19] R. Vaughan, N. Scott, D. White, “The Theory of Bandpass Sampling,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 19731984, Sep. 1991. [1.20] A. Kwan, S. A. Bassam, F. M. Ghannouchi, “Sub-sampling Technique for Spectrum Sensing in Cognitive Radio,” IEEE Radio and Wireless Symposium (RWS’2012), pp. 347-350, 2012. [1.21] S. A. Bassam, A. Kwan, W. Chen, M. Helaoui, F. Ghannouchi, “Subsampling Feedback Loop Applicable to Concurrent Dual-Band Linearization Architecture,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no.6, part 2, pp. 1990-1999, 2012. 34 Chapter 1: Introduction SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 35 CHAPTER 2 OVERVIEW OF SOFTWARE DEFINED RADIO AND MULTISTANDARD RECEIVER ARCHITECTURES CHAPTER CONTENTS 2.1 Software defined radio systems ...................................................................... 37 2.1.1 Software defined radio idea and evolution ............................................................. 37 2.1.2 Software defined radio architecture ........................................................................ 38 2.1.3 Benefits and inconveniences of the software defined radio .................................... 40 2.1.4 Introduction to cognitive radio ............................................................................... 41 2.2 Receiver architectures .................................................................................... 42 2.2.1 Superheterodyne receiver ....................................................................................... 42 2.2.2 Zero-IF receiver ...................................................................................................... 46 2.2.3 IF receivers ............................................................................................................. 47 2.2.3.1 Low IF receivers ................................................................................................ 47 2.2.3.2 Doble low IF receivers ...................................................................................... 49 2.2.3.3 Wideband IF receivers with double conversion ................................................ 50 2.2.4 Subsampling receiver.............................................................................................. 50 2.2.5 Receivers based on interleaving ............................................................................. 53 36 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 2.2.6 Multi-standard receivers ......................................................................................... 54 2.2.6.1 Multi-standard zero IF receiver ......................................................................... 54 2.2.6.2 Multi-standard low IF receiver .......................................................................... 55 2.3 References ....................................................................................................... 56 This chapter is dedicated to describing the context and the applicability of this thesis. A first section reviews the main concepts about SDR, describing its evolution and detailing its benefits and the current problems that avoid getting this paradigm. This section presents an introduction to cognitive radio as well. A second section reviews the main receiver architectures, focusing on their main advantages and disadvantages when implemented as multi-standard receivers. This section concludes with the convenience of using subsampling architectures. The chapter finalizes describing several published multi-standard receiver architectures. Chapter 2: Overview of software defined radio and receiver architectures 37 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 2.1 Software defined radio systems 2.1.1 Software defined radio idea and evolution A SDR radio is a communication system that performs most of its signal processing tasks in a programmable digital signal processing (DSP), being fully adaptable by real time downloadable software, and enabling the adjustment of various communications scenarios automatically, adapting to different regional interfaces as well [2.1]. In other words, SDR means a radio where functionality and signal processing are defined in software, and it supports multi-band multiuser radio communication. These systems will have a key role in future radio configurations because the emergence of new wireless technologies, and the necessity of integration of a larger number of communication standards in multi-standard and multiband radios in order to implement a universal handset that provides worldwide access. Some benefits at top level are, for subscribers, an easier international roaming, improved and more flexible services, and increased personalization. For mobile network operators, some top-level benefits are the potential to rapidly develop and introduce new, personalize, and customized services [2.2]. A SDR system uses a single hardware front end but can be reprogrammed by software its frequency of operation, occupied bandwidth, and adherence to several wireless standards by calling various software algorithms, allowing inexpensive, efficient interoperability, and increasing flexibility via increased programmability. At the same time, SDR architectures simplify hardware component tradeoffs and provide new ways of managing the complexity of the emerging standards. The SDR software reprograms the DSP segment in order to reconfigure the system and, thus, implement multiple radios. This segment performs the signal processing and conditions the signal to be modulated and demodulated, being the processing engine a combination of general purpose (GP) microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and specialized co-processors [2.3]. The DSP system is coupled to the air interface and antenna by analog-to-digital and digital-to-analog converters, as shown in Figure 1.1. Note that, although the SDR paradigm allows a single terminal to adapt to multiple radio interface standards by software converting directly to digital domain after the antenna, an evolution process is still active, which has been described and predicted. This evolution is illustrated in the receiver of Figure 2.1 and is referred to the part of the radio architecture that is covered by the software 38 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS processing tools [2.2]. Therefore, new data conversion techniques are currently researched in order to get this paradigm in the future. RF Frontend Analog IF A/D D/A Baseband Modem Processing Bitstream Processing Data Interface RF Frontend Analog IF A/D D/A Baseband Modem Processing Bitstream Processing Data Interface RF Frontend Digital IF Processing A/D D/A Baseband Modem Processing Bitstream Processing Data Interface Softaware processing Softaware processing Softaware processing Figure 2.1 SDR Evolution On the other hand, there are different download mechanisms [2.1]: static, pseudo-static and dynamic software download. Static download is the situation where SDR can support a variety of standards and is programmed in a static manner to address one of these possibilities. This means a first step about reconfigurability capabilities. Pseudo-static download refers to using the air interface to download and pre-configure a terminal to accommodate a defined set of applications, and protocols. This option increases the flexibility of the radio over the static option and, moreover, this upgrade can appear transparent to the user. Finally, the dynamic option offers a higher flexibility, due to allowing the reconfiguration during, for instance, a call, providing a concrete configuration on demand. 2.1.2 Software defined radio architecture In this section a general scheme of a SDR transceiver will be described, presenting the main functionalities implemented in both sides, i.e., transmitter and receiver. Since this work is orientated to the receiver implementation, in following Chapter 2: Overview of software defined radio and receiver architectures 39 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS sections the most convenient architectures for this part of the system will be described more concretely. A block diagram of the signal processing functionalities in a SDR transceiver is illustrated in Figure 2.2. This diagram ranks of tasks known as Primary Signal Processing Tasks [2.3], which includes frequency translation, filtering and data conversion. Two more signal processing groups are classified for a SDR system, one dedicated to synchronization and another one dedicated to improve the response to the dirty RF [2.4] (Secondary and Tertiary Signal Processing Tasks, respectively). Both of them are described briefly in the end of this section. S-PI-Q Table Digital Low Pass Digital Low Pass Digital Low Pass Digital Low Pass DAC IF Stage RF Stage PA Gain Control IF Stage ADC Digital Low Pass Digital Low Pass Digital Low Pass Digital Low Pass DDS Carrier PLL Detect S-P Timing PLL DDS LNA VGA Bits Modulator Demodulator Channel Shape & Upsample Interpollate IF Analog Analog RF Carrier RF Carrier Analog Carrier Waveform Decimate Matched Filter Bits Figure 2.2 Block diagram of Primary Signal Processing Tasks in a typical transmitter and receiver Centering the description in the receiver side (Figure 2.2), the received signal will be amplified and translated to suitable intermediate frequencies (IF) prior to being converted to digital domain. However, this architecture is only a first approximation because the SDR paradigm leads to implement this downconversion digitally, i.e., placing the ADC just after the antenna. The converted signal is sampled by the demodulator, which down-converts the IF-centered signal with a digital down-converter (DDC). The current baseband-centered signal has a sample rate above the required to satisfy the Nyquist criteria so it will be reduced by the decimating filter. Therefore, these two processes mirror and cancel the upconversion and the interpolation1, respectively, implemented in the transmitter side. Finally, the reduced sample-rate signal is used as input of the detector and is processed to maximize its output SNR. 1 Usually this output sample rate is fixed at some sufficiently high value that can be used for a large IF range. 40 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Although it is possible to observe from Figure 2.2 that the transmitter and the receiver side are almost complementary, the receiver also performs a number of tasks not present in the transmitter, such as to estimate unknown parameters of the received signal as amplitude, frequency offset, or timing offset. To implement these functionalities some elements as a channel equalizer, a digital automatic gain control (AGC), a DC canceller, and a SNR estimator are necessary in the receiver part, although they are omitted from the block diagram by simplicity. On the other hand, some of the Secondary Signal Processing Tasks in the receiver are the modulation carrier alignment, symbol clock alignment, and scaling the received signal with its SNR. In fact, when the alignment process is performed properly, the receiver is able to collect all the energy in the receive signal, estimating the transmitted waveform’s amplitude with maximum SNR. Consequently, SDR radios work over a large range of stressed signal levels. Finally, the Tertiary Signal Processing Tasks help to minimize the problems caused by the tolerance, and gain and phase imbalances from the analog world. Also, other non idealities contribute to the signal degradation. These effects include the non linearity in the power amplifier, ADC and mixers, DC offsets and coupled spectral lines, oscillator phase noise, sampling aperture jitter and clock jitter. Therefore, the receiver includes some compensating processing DSP blocks to reduce the effects from the analog components. These blocks are DC cancel, Phase and Gain Balance, and Channel Equalization. 2.1.3 Benefits and inconveniences of the software defined radio An SDR has advantages in cost and performance. Since almost all the functionalities are performed in the digital domain, these designs are less expensive to manufacture, due to the Moore’s Law, and offers a better general performance as well as reduced sensitivity to age, temperature and environmental influences. Analog components such as resistors or capacitors are manufactured with specific tolerances. Also circuits designed from analog components suffer from mismatch and imbalance effects, which limit the performance of the system. Moreover, note that, although an SDR design uses digital techniques, differs from a DSP radio (also called software-controlled digital radios [2.1]) in that its radio parameters are not fixed, i.e., they are reconfigurable. The main advantage of this reconfigurability is that an SDR system supports communications between a wide range of communication systems. This programmability includes programmable RF bands, channel access modes, and channel modulation. Moreover, as new waveforms, features and standards are developed and incorporated, the SDR can be reprogrammed, through software upgrades, to increase its capabilities and be a new radio. These benefits will reduce the costs delaying the obsolescence of the communication systems. Therefore, in applications where access to multiple bands with multiple radio Chapter 2: Overview of software defined radio and receiver architectures 41 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS access modes is a necessity, the SDR can reduce hardware size, complexity and power through fewer radio units. However, SDR is still a radio and, therefore, the rules to design a good radio must be applied as well. As this design requires a larger bandwidth and dynamic range, the DSP section will need reduced levels of dirty RF [2.4] in the analog air interface. The phase noise, the jitter, the level of the third order intercept will have to improve because DSP by itself cannot repair all these sources of signal degradation introduced by the analog components. Another RF problem in SDR is the necessity to avoid the introduction of processor clock harmonics into the analog RF and IF circuits. Also, when a multiple transmitter is implemented electromagnetic interference (EMI) problems will occur. Nevertheless, some of these inconveniences are present in multiple hardware radios as well. Moreover, it is difficult to engineer wideband, low loss antennas, and RF and data converters, so new techniques to implement the transceivers must be developed in order to cover most wireless communication standards placing the data converters (ADCs and DACs) as close to the antenna as possible. The present work will be focused in these objectives, about the optimal conversion techniques in the receiver side. An additional problem of an SDR system is that, due to its flexibility, it can be used to perform functions that are prohibited by legal restrictions, like to transmit in unlicensed frequency bands. This problem must be addressed as well. Finally, another known drawback is the difficulty to place the ADC right after the antenna, due to the current ADC specifications. This problem will be address throughout this thesis work. 2.1.4 Introduction to cognitive radio At this point it is necessary to introduce the cognitive radio idea. Due to another functionality of the SDR is its capability to adapt itself the transmission scenario in order to minimize the interference with other signals in the air interface, the system will require the ability to scan the spectrum from low to high frequency using software. With this objective in mind, the idea of CR [2.5] is to build on an SDR, where the radio adapts itself to the environment by optimizing the carrier frequency, modulation, and choice the radio standard to minimize interference and maintain communication in a given scenario. One of the most promising objectives of CR is to increase the spectrum occupancy, the radio utilizing spectrum that is not used by other radio at this moment. Another main objective will be to be able to implement a highly reliable communication whenever and wherever needed. The three fundamental cognitive tasks can be found described in [2.6]: 48 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS The next down conversion from low IF to baseband is implemented in the digital domain, avoiding the problems caused by the I-Q mismatches in the analog domain. BPF LNA LO1 Amplifier RF 90º LPF LPF Amplifier ADC ADC sin(ωLO2t) DSP cos(ωLO2t) cos(ωLO2t) Figure 2.9 Conceptual diagram of the low IF receiver architecture This structure is also simple and still allows a high level of integration and does not suffer from the zero-IF architecture problems (DC offsets or flicker noise) because the desired signal is not folded to DC. However, in this case, the image frequency disadvantage is reintroduced, due to being difficult to reject it, thus being the major drawback of this architecture. Both image and desired signal will be digitized by the ADC. Thus a digital filtering for channel-selection will be implemented by the DSP as well. An additional problem is about the ADC power consumption, which is increased because now a higher conversion rate is required. Another option to eliminate the image interferer is to use an IF polyphase after the down-conversion, as shown in Figure 2.10 [2.7]. This makes this architecture very suitable for multi-standard receivers, since this filter can be shared by different standards. Any changes in the RF frequencies can be solved by using corresponding LO frequencies and down-converting the RF signal to the same IF, filtering the corresponding image by the polyphase filter. Chapter 2: Overview of software defined radio and receiver architectures 49 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS BPF LNA Amplifier RF LPF LPF Amplifier ADC ADC sin(ωLO2t) DSP cos(ωLO2t) cos(ωLO2t) cos(ωLO1t) sin(ωLO1t) Polyphase Filter Figure 2.10 Conceptual diagram of the low IF receiver architecture with polyphase filtering 2.2.3.2 Doble low IF receivers The basic idea of these receivers, whose block diagram is illustrated in Figure 2.11, is to up convert the I-Q channels, generated previously at IF, to a high frequency using a fixed frequency synthesizer [2.15]. The signal then feeds to an IF filter, usually off chip, being its integration level lower than in the low IF case. The double low IF architecture is more immune to DC problems, like in the low IF case. Also similar to a low IF receiver, the close proximity of the image signal means its suppression is not possible by only the RF filter. Although, these receivers would be limited to standards with moderate adjacent channels or stringent requirements of the IRF, unlike the low IF receiver, the signal is up converted to a high IF, where a very high-Q discrete filter is employed to remove the image. This filter will contribute to the suppression of the image in conjunction with low pass filter at the first IF stage, providing a higher selectivity performance and a compromise between selectivity and integration level. BPF LNA LO1 RF 90º LPF LPF Amplifier ADC LO2 90º BPF Figure 2.11 Conceptual diagram of the double low IF receiver 50 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 2.2.3.3 Wideband IF receivers with double conversion A receiver which uses a RF channel-select frequency synthesizer and an IF or baseband channel-select filter is a narrowband receiver. An alternative architecture based on IF receiver structures to use for multi-standard applications is the wideband IF receiver (Figure 2.12), where the entire RF band containing the information is translated to IF by multiplying the LO output with a fixed frequency [2.15]. All the channels at IF are then translated to DC using a tunable, channel-select LO and, finally, the selected low pass channel feeds the ADC. Previously a variable gain has been provided. As in the case of zero IF receivers, channel filtering can be performed at baseband, where digital programmable filters can enable more multi-standard receiver features. This approach is similar to superheterodyne receivers in that the frequency translation is accomplished in multiple steps. However, unlike a conventional superheterodyne architecture, the first LO frequency translates the whole RF band, maintaining a large bandwidth at IF. Moreover, the wideband IF receiver has an additional advantage about a higher capability to facilitate the synthesizer integration than the rest of receivers described previously. Therefore, the integration of this architecture is also feasible, although the I-Q mismatches problems in the analog domain are reintroduced. Similar to the zero IF receivers, other inconvenience of wideband IF architectures is its susceptibility to flicker noise, DC offset and distortion due to second order intermodulation. BPF LNA LO1 RF 90º LPF LPF ADC sin(ωLO2t) cos(ωLO2t) cos(ωLO2t) Amplifier LPF LPF ADC Amplifier IF Figure 2.12 Conceptual diagram of the wideband IF receiver architecture with double conversion 2.2.4 Subsampling receiver A feasible alternative to the previous solutions is the receiver based on subsampling, which is illustrated in Figure 2.13. The received signal is filtered by a RF band pass filter that can be a tunable filter or a bank of filters. The incoming band pass signal is sampled under Nyquist criteria [2.16,2.17], using some Chapter 2: Overview of software defined radio and receiver architectures 51 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS sampling properties and avoiding aliasing, as is described in Chapter 2. This sampled signal is converted to digital using an ADC at intermediate sampling rate. The main advantage of this scheme is its simplicity, the number of components being reduced, and being possible to place the data conversion closer to the antenna. Therefore, lots of functions like filtering, frequency translation and demodulation can be implemented in digital domain, taking advantage of low cost digital VLSI solutions, leading to a high integration and eliminating problems such as DC offset, 1/f noise. In addition to system cost reduction, pushing these functions in digital domain eliminates the many of the sensitivities of analog solutions, such device matching, environmental sensitivity, and performance variation over time. The flexibility and reconfigurability required by SDR applications is also increased by moving the ADC into IF stage and, moreover, it is possible to use this architecture for wideband and multi-standard applications because of its large analog bandwidth. In this architecture, a single ADC can sample multiple signal channels, which are then separated and demodulated in parallel in digital domain. However, some critical requirements exist when this structure is employed, as the needed analog input bandwidth of the S&H. Since this bandwidth must include the RF carrier frequency, the bandwidth of the S&H inside the ADC cannot be large enough for the required dynamic range, resolution and sample rate using the current technologies. A common solution is to place a previous external S&H. BPF LNA S&H ADC BPF RF fs/2 Figure 2.13 Conceptual diagram of the subsampling receiver architecture An intermediate alternative, about simplicity and S&H requirements, is to do a previous translation to IF, as shown in Figure 2.14. This concept is called IFsampling [2.18], being this digital-IF architecture a step toward SDR idea where the last down-conversion stage in heterodyne receivers is replaced by an ADC stage. If the Nyquist theorem is met the sampling function is called Low Pass Sampling (LPS) and the IF signal is directly sampled and converted by the ADC, 52 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS avoiding the I-Q mismatches problems. However, since the IF signal have to be large, in order to avoid the filtering rejection problems, the ADC requirements will be very demanding. Therefore, for this architecture, to sample without meeting Nyquist theorem (only with a sampling frequency higher than twice the information banwidth) allows to obtain more relaxed ADC. This sampling function is called Band Pass Sampling (BPS) and it is equivalent to realize a down conversion mixing by spectral folding, as shown in Chapter 2. This scheme will avoid the I-Q mismatches problems as well. BPF LNA S&H ADC BPF RF fs/2 LO BPF IF Figure 2.14 Conceptual diagram of the subsampling architecture with an intermediate down-conversion Finally, subsampling receivers have additional problems as some noise sources, as the jitter and thermal noise folded in the interest band, finally these effects being minimized in this thesis work. Moreover, RF band pass filtering is required when avoiding overlap between folded signals is necessary. These BP filters, especially on-chip filters, are difficult to implement at high frequencies. Although external filters, such as SAW filters, can be used, they are only available at limited number of frequencies, so it is not a practical solution to design multi-standard receivers. Alternatively, higher sampling frequency is often used to reduce the required selectivity. However, this solution has some drawbacks as the high technology and high cost required by the ADC, whose resolution and dynamic range will be degraded as compared to lower sample rate ADC alternatives. Also power consumption is increased with sample rate. Therefore, the cost, performance, and power consumption of other devices (such as ADC clock sources, digital circuits after the ADC) also will be impacted by the ADC sample rate. In this thesis some novel techniques, about the sampling frequency plan, are addressed in order to avoid this overlapping between signals, reducing the complexity of the RF filtering. On the other hand, additional adjacent interferers not overlapped with the desired signal can be suppressed by additional channel filtering in digital domain. Chapter 2: Overview of software defined radio and receiver architectures 53 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 2.2.5 Receivers based on interleaving An alternative scheme to the subsampling techniques, in order to place the analog-to-digital conversion close to the antenna, is a time-interleaved ADC architecture. This scheme is an effective approach for achieving very high sampling rates [2.19,2.20]. A time-interleaved ADC operates M parallel ADCs at different sampling times, creating the image of a single ADC operating at a much higher sampling rate. The concept is illustrated in Figure 2.15 [2.20]. Ideally, the ith ADC, i = 0, ..., M – 1, samples periodically the input signal at time instants ti,ti+M,ti+2M, with sample rate fs/M, where tm=mTs and Ts=1/fs is the sampling period of the time-interleaved ADC. The final output is created by multiplexing all of the individual ADC outputs in the proper order (e.g. ADC0, ADC1, …, ADCM – 1, ADC0, ADC1, etc.). Thereby, the final effect is as if the input signal were sampled once every Ts seconds, i.e., with sample rate fs. This approach has been widely adopted in the industry, since the converters can be working at lower speeds without sacrificing the overall system performance. However, it should be noted that each individual ADC deals with the entire analog input signal, and, therefore, its S&H circuit must be able to preserve the full input signal bandwidth. This is the main inconvenient to use these architectures for multi-standard receivers, besides the mismatch between ADCs, being this thesis focused mainly in subsampling techniques. Nevertheless, an approach to receivers based on interleaving is addressed in Appendix A. Figure 2.15 Conceptual diagram of the receiver based on interleaving architecture 54 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 2.2.6 Multi-standard receivers Stacking several receivers for different standards into a single receiver, operating in parallel, is not a feasible option to implement a multi-standard receiver because the area and the power consumption would be extremely high. Therefore, a multi-standard receiver should share the available hardware resources as possible and make use of the tunable and programmable devices, increasing the level of integration. From the view of high level integration, the zero IF receiver, low IF receiver, wideband IF receiver and subsampling receiver are most suitable, while the double IF receiver presents a compromise between selectivity and integration level. From the view of placement of the ADC, both the zero IF receiver and the subsampling receiver are candidates for SDR implementation because the ADC directly has an interface to RF or higher IF signals. However, due to some inconveniences of zero IF receivers, as DC offset or LO leakage, this thesis will be addressed to subsampling receivers. Regarding the radio section, note that the different standards require different front-end performance. The most straightforward solution would be satisfying the most critical specifications for each one. Some of the more typical standards that need to be covered by multi-standard receivers are illustrated in Figure 2.16. GHz GSM 1 65432 GPS GSM UMTS/W-CDMA Bluetooth IEEE 802.11b/g WiMAX IEEE802.11a Figure 2.16 Multi-standard frequency spectrum In this section two examples of conventional multi-standards receivers are described. The multi-standard receiver based on subsampling, designed in this thesis work, is described in the following chapters and compared with other published subsampling receivers for multi-standard applications. 2.2.6.1 Multi-standard zero IF receiver Figure 2.17 [2.21] illustrates a single-chip multi-mode receiver for four standards (GSM900, DCS1800, PCS1900 and W-CDMA), which was designed in a zero IF scheme. An external digital controller selects the different standards and the hardware is shared as much as possible by different standards. These standards Chapter 2: Overview of software defined radio and receiver architectures 55 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS use two different channel selection filters, and the quadrature LO signals are obtained by using a divide-by-two-circuit for the mixers. Since the LO signal is generated on-chip, the LO leakage on the PCB to the RF input, which is a typical problem for homodyne receivers, is eliminated more efficiently. However, the level integration will be lower in this case. Multi-Band LNA 1ADC DCS/PCS/GSM WCDMA 1ADC DCS/PCS/GSM WCDMA /2 WCDMA GSM900 DCS1800 PCS1900 LO Figure 2.17 Multi-standard receiver architecture by zero IF 2.2.6.2 Multi-standard low IF receiver Figure 2.18 [2.22] illustrates another fully integrated multi-standard receiver designed in low IF, with several SAW BP filters and a multi-band LNA preceding this architecture. This design supports five wireless communication standards, Bluetooth, GSM (DCS1800 for Europe, or PCS1900 for USA), UMTS, 802.11b/g and 802.11a. It is possible to observe in the diagram block how the Bluetooth channel is active all the time, while the other four standards, which cover five different frequency bands, are activated by an RF switch before feeding the rest of the low IF receiver due to how they do not need to be covered at the same time, i.e., when an application is active, the others can be switched off or in idle mode, in order to save power and reuse hardware resources. Otherwise, Bluetooth needs to operate concurrently to other standards, allowing to have activated the wireless link during a phone call or data communication. 56 Chapter 2: Overview of software defined radio and receiver architectures SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 0º90ºLO ADC ADC Multi-Band LNA Bluetooth SAW Bluetooth Receiver Path GSM SAW UMTS SAW IEEE 802.11b/g SAW IEEE 802.11a SAW Figure 2.18 Multi-standard receiver architecture by low IF In this section a comparative of multi-standard receivers about digitalization techniques (i.e., mixing or subsampling based systems) have been introduced. There is a second research field about the band strategy (i.e., wideband or narrow band strategy). While the examples described in this section [2.21,2.22] are narrowband multi-standard receivers because of they employ dedicated channels, other published works [2.23-2.26] can be considered universal receivers, covering a large input frequency range. Although these wideband solutions are more flexible, their main inconvenience is the RF front-end must meet the requirements for each standard and they are not optimum for any standard. These alternative receivers will be studied more precisely when they are compared with the works described in Chapter 3. 2.3 References [2.1] J. Mitola, “The Software Radio Architecture” IEEE Communications Magazine, vol. 33, no. 5, pp. 26-38, May 1995. [2.2] W. H. W. Tuttlebee, “Software-Defined Radio: Facets of a Developing Technology,” IEEE Personal Communications, vol. 6, no. 2, pp. 38-44, 1999. [2.3] F. Harris, R.W. Lowdermilk, “Software Defined Radio: Part 22 in a Series of Tutorials on Instrumentation and Measurement,” IEEE Instrumentation & Measurement, vol. 13, no. 1, pp. 23-32, Feb. 2010. [2.4] G. Fettweis, M. Lohning, D. Petrovic, M. Windisch, P. Zillmann, and W. Rave, “Dirty RF: A new Paradigm,” International. Journal of Wireless Information Networks, vol. 14, no. 2, pp. 133-148, Jun. 2007. Chapter 2: Overview of software defined radio and receiver architectures 57 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [2.5] J. Mitola, G. Q. Maguire, “Cognitive radio: Making software radios more personal,” IEEE Personal Communications, vol. 6, no. 4, pp. 13–18, Aug. 1999. [2.6] S. Haykin, “Cognitive Radio: Brain Empowered Wireless Communications”, IEEE Journal on Selected Areas in Communication, j. 48, no. 2, pp. 201-220, 2005. [2.7] L. Zhang, “System and Circuit Design Techniques for WLANEnabled Multi-Standard Receiver,” Doctoral Dissertation, Ohio State University, USA, 2005. [2.8] Y. R. Sun, “Generalized Bandpass Sampling Receivers for Software defined Radio,” Doctoral Dissertation, School of Information and Communication Technology (ICT), Stockholm, Sweden, 2006. [2.9] J. R. Macleod, M. A. Beach, P. A. Warr, T. Nesimoglu, “A Software Defined Radio Receiver Test-bed,” IEEE Vehicular Technology Conference (VTC 2001), vol. 3, no. 2, pp. 1565-1569, Fall 2001. [2.10] R. Hartley, “Modulation System,” U.S. Patent 1,666,206, Apr. 1928. [2.11] D. Weaver, “A Third Method of Generation and Detection of SingleSideband Signals,” Proceedings of the IRE, pp 1703-1705, Dec. 1956. [2.12] A.A. Abidi, “Direct-conversion radio transceivers for digital communications," IEEE Journal of Solid-State Circuits, vol. 30, no. 12, Dec. 1995. [2.13] J. Crols, M. Steyaert, “Low-IF topologies for high-performance analog front-ends for fully integrated receivers," IEEE Journal of Solid-State Circuits, vol. 45, no. 3, Mar. 1998. [2.14] P. Cruz, N. B. Carvalho, K. Remley, “Designing and Testing Software-Defined Radios,” IEEE Microwave Magazine, vol. 11, no. 4, pp. 83-94, 2010. [2.15] J. C. Rudell, “Frequency Translation Techniques for High-Integration High-Selectivity Multi-Standard Wireless Communication Systems,” Doctoral Dissertation, University of California, Berkeley, USA, Fall 2000. [2.16] D. Grace, S. P. Pitt, “Quadrature sampling of high frequency waveforms," Journal of the Acoustical Society of America, vol. 44, pp. 1432-1436, 1968. 64 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Choosing a sampling frequency for a band limited signal2 affects the reconstruction process. A band limited signal with total bandwidth (BW) is denoted in Figure 3.3. Once the continuous signal is represented by a sequence of discrete sample values, its spectrum takes a replicated form, with these replicas separated fs. In other words, a continuous signal cannot be represented in a digital machine in its current band limited form. For Figure 3.3a, the sampling frequency fs=1/Ts=ωs/2π is much larger than the bandwidth, and perfect reconstruction is possible because the infinite replications are not aliased. Similarly, for the case when fs=BW as in Figure 3.3b, the spectrums do not overlap, or alias, over each other and the signal can still be decoded properly. However, in Figure 3.3c, fs is less than BW, and aliasing occurs over the signal. This aliasing corrupts the information in the signal and is unrecoverable. The minimum sampling rate, or the Nyquist sampling rate, should be fs >= BW in order to correctly decode the signal. In practice, an anti-aliasing filter (LP filter) will be necessary before the analog-to-digital conversion in order to eliminate any energy signal located above BW/2 or below –BW/2 that would be folded over the band of interest. X(f) X(f) X(f) (a) (b) fs -fsfs2fs -fs -2fsfs2fs -fs -2fs(c) Figure 3.3 Sampling of a signal using (a) fs >> BW (b) fs = BW and (c) fs < BW 3.3 Subsampling theory 3.3.1 Concept of subsampling As mentioned before, moving the ADC closer to the antenna increases the flexibility of the receiver. However, this conversion just after the antenna would prohibitively increase the bandwidth and sampling frequency requirements of the ADC. Nevertheless, the bandwidth of a bandpass signal is usually a fraction of its center frequency, so that it is possible to subsample the signal (i.e., violating the Nyquist condition) avoiding aliasing between replicas. Subsampling is the process of sampling a signal with a frequency lower than twice the highest signal frequency, and higher than the signal bandwidth BW. Using an ideal S&H device with sampling frequency fs will generate harmonics at 2 From a practical standpoint, the term band-limited signal merely implies that any signal energy outside the range [-BW/2,BW/2] is below the sensitivity of the system. Chapter 3: Subsampling receivers 65 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS fs, 2fs...mfs, where m is an integer. In the case for Figure 3.4a, a bandpass RF signal is centered at fc, while the mth closest harmonic generated by the S&H and lower than fc is k, where k = floor(fc/fs). The replicas of the signal that are generated by the S&H exist at -mfs + fc, while the mirrored versions replicas exist at (m + 1)fs – fc. Figure 3.4b shows these replicas, and the signal replica within the [0-fs/2] range (centered at fif=fc-kfs) can be used to extract the original RF signal. (a) (b) fskfs(k+1)fs BW -fs -kfs -(k+1)fs fs/2 3fs/2 fc fc -fs/2 -3fs/2 -fc -fc (k+1/2)fs -(k+1/2)fs Figure 3.4 Illustration of the concept of subsampling: (a) Frequency domain representation of the RF passband input signal along with the subsampling frequency and S&H harmonics and (b) signal replicas following subsampling process when selecting fs=(fc-fif)/k and fs>BW 3.3.2 Selecting the sampling frequency This section provides the method to select the optimal sampling frequency (fs) for a given signal bandwidth (BW) and carrier frequency (fc). Usually, the minimal sampling frequency is determined by the Nyquist Theorem: fs>2(fc+BW/2). However, for a bandpass signal a sampling frequency lower than the Nyquist frequency can be selected if equation (3.16) still holds [3.3]: mBWffmBWfcsc /)2/(2)1/()2/(2 (3.16) where m is the number of replicas of the signal spectrum in the range [0, fcBW/2], and lies between 1 and floor((fc+BW/2)/BW). An appropriate value is fs=4fc/modd which produces a replica at fs/4 and sometimes it is called “optimal” sampling frequency. Using an odd integer modd ensures that the signal is at fs/4, while meven generates the low frequency alias of the signal at 3fs/4. As an example, for a given input signal at 1070 MHz, with a signal bandwidth equal to 20 MHz, Table 3.1 shows its first ten valid ranges and its first ten optimal sampling frequencies. On the other hand, an example that illustrates the convenience of sampling at 4fc/modd can be observed in Figure 3.5, which shows the output spectrum when an input signal at 1070 MHz is sampled at fs of 475.56MHz (Figure 3.5a) and at nearby frequency of 480 MHz (Figure 3.5b). It can be seen how the second order 66 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS harmonic at 237.78 MHz is placed further from away the desired signal in the case of Figure 24a compared with Figure 3.5b (at 220 MHz). Therefore, sampling at 4fc/modd results in a larger subsampling frequency bandwidth and relaxes the filtering requirements after the S&H. As fs, fc and fif are all directly related, there are bandwidth and frequency tradeoffs when selecting the subsampling frequency. Table 3.1 Valid sampling ranges and optimal sampling frequency for an input signal at 1070 MHz and signal bandwidth equal to 20 MHz Upper Limit (MHz) Lower limit (MHz) Optimal frequency (MHz) 2040 1120 1462.7 1020 746.7 856 680 560 611.4 510 448 475.6 408 373.3 389.1 340 320 329.2 291.4 280 285.3 255 248.9 251.8 226.7 224 225.3 212 196.4 203.8 Chapter 3: Subsampling receivers 67 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS (a) (b) 237.78 MHz 118.89 MHz 110 MHz 220 MHz Figure 3.5 Output spectrum of the subsampler when the 1070 MHz RF signal is subsampled at a fs of (a) 475.56 MHz (modd=9 and fif=118.89 MHz) and (b) 480 MHz (modd=9 and fif=110 MHz) Another option in order to relax the ADC requirements could be to place the replica at a lower frequency. However, in practice, high performance ADCs are fine-tuned during design and manufacture to ensure maximum linearity at frequency, their use at lower frequencies not being recommended. Moreover, to sample close to the limits of the valid range could not be prudent because the analog band pass filters have non idealities and sample rates at the clock generator can present instabilities. Therefore, in these cases it would be convenient to consider a band guard be added to the signal bandwidth [3.4]. Finally, there is a case when subsampling is not possible. If a continuous bandpass signal’s lowest frequency is less than the bandwidth, we have a not permissible situation. This condition is shown in Figure 3.6 where fc-BW<BW. There is no way to fold any spectral replicas between this lowest frequency component and DC. In this case, it is only possible to sample the signal meeting Nyquist criteria, i.e., using a sample rate of at least twice the highest frequency component, i.e., fs >2(fc+BW). fc -fcfc+B/2 fc-B/2 BB Figure 3.6 Continuous signal spectrum where subsampling is not posible because fc-BW<BW 68 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 3.4 Non idealities in subsampling A general scheme for a subsampling receiver is shown in Figure 3.7. It deserves to be mentioned that this receiver is very simple, especially if it is compared to the conventional heterodyne architecture. However, as the S&H processes high frequency signals, its requirements are much more restrictive than those expected from the signal bandwidth. The main non-idealities to be considered in the S&H are jitter and folded thermal noise and will be described in the sub-sections. S&H ADC Digital Processing Figure 3.7 Subsampling receiver scheme 3.4.1 Jitter and phase noise 3.4.1.1 Phase noise Clock jitter is an important limitation in the data acquisition systems at high signals frequencies because leads to sampling time uncertainly. Jitter is the deviation of the reference edges of the clock signal with respect to their ideal position in time. In this chapter we will consider this deviation as a random noise. As shown in Figure 3.8, a random error τn from the nominal sampling time instant tn causes a random error ετ(n) in the amplitude of the sampled signal [3.5]. This effect can be seen as an addition of noise to the output signal, resulting in a degradation of the output Signal-to-Noise Ratio (SNR). y(t) y(tn) y(tn+τn) tntn+τn τn ετ(n) t Figure 3.8 Concept of jitter The amplitude error (verror) is proportional to the derivative of the input signal [3.5,3.6]: Chapter 3: Subsampling receivers 69 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS dt dv tv in error (3.17) With a jitter value of ∆t. For a sine wave of frequency fin and amplitude Ain, the maximum error is [3.5,3.6]: ininerror ftAv2 max_ (3.18) There are two main sources of jitter noise, the phase noise associated to the clock reference and the aperture jitter of the S&H. The aperture jitter of an S&H implemented with a MOS transistor is signal-dependent, as the transistor threshold voltage depends on the input signal. Concerning the system clock, there are two primary mechanisms that cause jitter: the thermal noise and the coupling noise. The latter can be caused by crosstalk and/or ground loops within, or adjacent to, the area of the circuit. Special care has to be taken designing the power lines in the data acquisition board that will be described in Chapter 3. In a first order approach, these two sources of jitter noise can be considered as uncorrelated Gaussian stochastic processes, each one with a particular standard deviation. Being ∆trms the standard deviation of jitter (or root mean square), which usually defined as a percentage of the sampling period, the sampling error in equation (3.17) can be re-written as [3.5]: 2 2)/()( in inrmsinrmserror A ftdtdvtv (3.19) where σ() is the standard deviation. Therefore, the resulting SNR on the sampled signal is then [3.5]: )2log(20 2 2 2/ log20 inrms in inrms in jitter ft A ft A SNR (3.20) This approximation will be true if 2πfin∆trms<<1, otherwise the general expression for the SNR due to the uncorrelated random jitter noise for a sinusoidal input signal can be expressed as follows [3.7,3.8]: otherwisee tftf SNR rmsin tf rmsinrmsin jitter :)1(2/1 12:4/1 log20 222 2 222 (3.21) The expression of SNR for 2πfin∆trms<<1 is valid for all jitter distributions while the other SNR expression only applies to a random jitter with Gaussian distribution N(0, ∆trms) [3.7]. Moreover, small jitter noise can be approximately 70 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS regarded as sampled Additive White Gaussian Noise (AWGN) while for large jitter, this assumption is not valid anymore. Note that the SNR is degraded when the input frequency increases. This SNR will be added to the SNR in the analog-to-digital conversion stage (SNRADC in equation (3.22) [3.5]), i.e., the degradation caused by thermal noise and quantization noise. 1010 1010log20 jitter ADC SNR SNR Total SNR (2.22) In the particular case of subsampling, jitter noise is an important limitation due to high input frequencies are processed. Thus, in order to validate this theoretical study, jitter noise is simulated using typical values for receivers subsampling based, i.e., the input frequencies in the GHz range, the sampling frequencies around 500 MHz (which is a typical limit for high resolution commercial ADCs, as is described in Chapter 3), and a 20 MHz signal bandwidth, due to how it is a typical value for many communications standards and is used to characterize experimentally the data acquisition board proposed in Chapter 3. Therefore, using these values, jitter noise has been simulated (using MATLAB) as a stochastic process with average equal to zero and standard deviation equal to ∆trms. Figure 3.9 [3.9] illustrates the maximum admitted jitter (Axis X) to obtain a concrete SNR (Axis Y) for three different input frequencies (1, 2 and 4 GHz) sampling at the optimum frequency (from equation fs=4fc/modd) immediately lower than 500 MHz. In this example, the jitter noise is integrated in a signal bandwidth equal to 20 MHz and it can be observed how the SNR will decrease around 6 dB each time the input frequency is doubled, as can be predicted by equation (3.21). Chapter 3: Subsampling receivers 71 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10-12 40 45 50 55 60 65 70 75 80 Desviación típica de jitter (seg) SNDR (dB) fc=2GHz, fs=470.59MHz, BW=20MHz fc=1GHz, fs=444.44MHz, BW=20MHz fc=4GHz, fs=484MHz, BW=20MHz Aperture jitter (s) SNR (dB) Figure 3.9 SNR requirements as a function of the jitter for different input frequencies 3.4.1.2 Phase noise This traditional method, based on equation (3.22) to obtain the SNR as a function of clock jitter and signal frequency, has some limitations, as the assumption of a full scale scenario. Although this situation may happen in some applications, most commonly the input signal energy is spread over some bandwidth. In these cases it is more realistic to study the jitter effect from the spectrum domain. Since the spectrum of jitter is very difficult to measure directly, the most common method to study its effect is by measuring the phase noise, which is the most widely employed parameter to compare between different clock sources and oscillators. The phase noise is defined as the frequency domain representation of the phase modulation of the clock signal due to the jitter. The clock signal being a sine wave of frequency fs [3.5]: ))(2sin()))((2sin( ttfAtttfAv ssclock (3.23) where υ(t)is the phase noise in the time domain. Assuming υ(t) has small variation around zero, equation (3.23) can be written as [3.5]: )()2cos()2sin( ttfAtfAv ssclock (3.24) The second term of this expression is the additive noise due to the phase modulation. Since the phase noise appears multiplied by a cosine in the above time domain expression, in the frequency domain the spectrum of the phase noise, Φ(f), is convolved with the noise-free clock and appears as sidebands around its center frequency. This noise is usually represented as L(f) (single-sideband phase 72 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS noise power spectrum) and is equal to the noise power spectral density per Hertz at the frequency fs+f normalized by the clock or oscillator signal power A2/2. It is called single-sideband because only one side of the noise power is taken into account; hence it includes only half the noise energy. Thus [3.5]: 10 )( 2 102)( )( 2 1 log10)( fL f ffL (3.25) L(f) is represented in dBc/Hz. Figure 3.10 [3.1] shows an example of phase noise for a clock frequency equal to 1.9 GHz, which is a typical frequency range for the S&H clock source in the implemented systems, as it will be detailed in the following sections. These experimental measurements show a phase noise of around -95 dBc/Hz, -110 dBc/Hz and -125 dBc/Hz at 100 Hz, 1 KHz and 10 KHz respectively. Figure 3.10 Phase noise for a clock frequency equal to 1.9 GHz From equation (3.23), the relationship between υ(t) and jitter is [3.5]: )(2)( sss kTtfkT (3.26) That is equivalent to referencing jitter to the clock period. In the frequency domain, where the clock phase noise is most commonly represented, it is then equal to the clock jitter scaled by 2πfs [3.5]: )(2)( fTff s (3.27) Therefore, we have the following expression to obtain the total jitter from phase noise [3.5]: Chapter 3: Subsampling receivers 73 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 0 10/)( 0 2102 2 1 )( 2 1df f dff f tfL ss rms (3.28) Finally, the SNR degradation can be calculated from the phase noise measurements as well. Assuming a sine wave as input, [3.5,3.10] calculates the expression for the voltage sampling error due to the jitter in the frequency domain: )( 2 2)( in in inerror ffT A ffV (3.29) If we substitute (3.27) in (3.29) the following expression is obtained: )( 2 )( in in s in error ff A f f fV (2.30) In order to obtain the in-band noise that will affect the SNR, equation 30 over the system pass band (fmin, fmax), employing (3.25), results3: max min max min 10/)( 2 2 10log20 )( 2 log10 f f ffL s in f f error in jitter df f f dffV A SNR in (3.31) On the other hand, when an oscillator is used as clock generator it is necessary take account that its phase noise is composed of two main regions as illustrated in Figure 3.11 [3.5,3.11,3.12]. The larger region is due to the thermal noise whose effect is similar to a frequency modulation, generating sidebands that fall inversely proportional with frequency offset, in a slope of -20 dBc/dec. At low frequency offsets, there is a region with a slope of -30 dB/dec due to upconversion of 1/f noise. The corner frequency between two regions, fx, is dependent on the oscillator implementation. Finally, the flat curve is usually called “white” phase noise [3.11] and the dashed curve illustrates the combination of the described curves. 3 Notice that there is no factor 2 because the integration is over only one sideband. 80 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS advantage of using a continuous Σ∆ modulator in front end is to reduce the noise of subsampling process without increasing the power consumption of the ADC. Moreover, using the continuous-time filter of the modulator the requirements of the anti-aliasing filter before the modulator will be less restricted. Otherwise, with the purpose of translating the different RF bands to same IF, this implementation selects a sampling frequency such as the frequency distance between the optimal IF (fs/4) and the IF of each RF band is minimal. The Σ∆ modulation (whose block diagram is similar as shown in Figure 3.18) is followed by a digital programmable decimation filter in order to remove the unwanted components frequency and reduce the oversampled rate to the Nyquist rate of the channel. This decimation filtering is implemented by using multiple stages, each stage being designed for the desired band of each standard. Finally, each standard is down-converted to baseband through the I-Q paths and controlled by a numerical oscillator. After a LP filtering stage the baseband signal is digitally processed. RF multiband filter LNA Continuous-time BP Σ∆ modulator Decimation filter Continuous-time subsampling BP Σ∆ ADC LO 90º LPF LPF DSP Figure 3.19 RF subsampling multi-standard Σ∆ receiver Another interesting application based on subsampling is the impulse radio architectures used in ultra wideband (UWB) radio [3.20,3.21]. UWB presents a high variety of applications, including imaging, surveillance, high-speed data communication and high-resolution location [3.22,3.23]. A common application that works in the 3.1-10.6 GHz band (with a minimum bandwidth of 500 MHz) is indoor communication, which has implementations in high speed short distances (less than 10 m) systems for wireless personal area network (WPAN), or in low data rate communications, such as sensor networks. [3.20] proposes to implement a low complexity 3.1-10.6 GHz UWB system which transmits passband pulses using a pulser and an antenna, and down-converts the received signal via subsampling. A challenge of UWB is to fully exploit the features of the wideband radios for low power and low cost designs in order to increase the efficiency of narrowband systems. Therefore, a feasible alternative to implement these systems will be the subsampling architectures. In this case, the receiver chain will process non sinusoidal carriers, so called impulse radios. Chapter 3: Subsampling receivers 81 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Moreover, UWB has a relatively low received SNR, due to the signal transmission power is limited by regulations, a large in-band noise due to the wideband circuit noise and possible interferences. As a result, a UWB receiver requires only a moderate ADC resolution, i.e., 4-6 bits [3.19]. Thus, the quantization noise is more dominant than the folded thermal noise, being the subsampling receiver a very promising architecture for UWB. For the same reason, the jitter constraint will be much less stringent. On the other hand, [3.21] presents a flexible subsampling receiver based on line spectrum estimation techniques, which are applied in the frequency domain in order to recover the position and the amplitude of the received pulses [3.24]. These pulses will be distorted by the transceiver antennas and the channel, being this pulse distortion very variable among the multipaths employed in these systems. Therefore, delay lines will be implemented in the analog domain in order to equalize the different paths. On the other hand, digital based receivers provide more flexibility and accuracy, but require ADCs sampling at Nyquist rate which are hardly realizable and highly power consuming. An architecture based on interleaved ADCs could be a feasible option but the area is increased and it requires appropriate techniques to compensate circuit mismatches between the parallel branches. As a result, a subsampling architecture is an alternative to implement this application because it provides the flexibility of a digital design without increasing the power consumption or area. Moreover, some applications specifically oriented to multiband and non linear systems employ subsampling techniques. This section introduces a couple of examples which work in these scenarios. However, these applications will be studied in more detail in Chapter 4, due to the necessity of additional restrictions in order to avoid the overlapping between signals and harmonics. Firstly, [3.25] presents a subsampling receiver for cognitive radio applications. The main utility of this multiband system, whose block diagram is illustrated in Figure 3.20, is to scan the wireless spectrum to know what slots in the whole spectrum are underutilized in order to be managed more efficiently and to able to be reused dynamically. This receiver presents the advantages proper of the subsampling based systems, such as, low complexity and flexibility, but there will be an additional challenge in order to avoid the overlapping between different slots when this spectrum is subsampled. Bank of BP filters S&H ADC Spectrum sensing unit (baseband processing) Figure 3.20 Subsampling based receiver for spectrum sensing 82 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Secondly, an example of a subsampling application in a non linear scenario is presented in [3.26]. The proposed system consists of the implementation of a subsampling receiver in the feedback loop of a transmitter. This feedback loop is utilized to accomplish the digital pre-distortion (DPD) linearization process of the power amplifier [3.27,3.28], whose idea is illustrated in Figure 3.21. This concept is based on extracting the behavioral model of the nonlinear transmitter, estimating its inverse behavior model, in order to pre-distort the digital baseband signal (previously to be transmitted) to compensate the extracted effects in the power amplifier. Therefore, since g()=f-1() in Figure 3.21, it is possible to obtain the input signal as y=f(g(x))=f(f-1(x))=x. f(u)g(x) DPD x u y x u u x yy Figure 3.21 Digital pre-distortion idea The concept behind the DPD technique is based on extracting the behavioral model of the nonlinear transmitter, estimating its inverse behavior model, in order to pre-distort the digital baseband signal (previously to be transmitted) to compensate the extracted effects in the power amplifier. Since the power amplifier is the main source of nonlinearity, because its highest efficiency state is operating close to the maximum output power, a scheme as showed in Figure 3.22 will be necessary. This architecture implements a transmitter for dual-band applications. It is possible to observe how the baseband signals x1 and x2 are pre-distorted to obtain xpd1 and xpd2 by the digital block that implements the inverse function of the power amplifier. These signals are converted to analog domain and up-converted to RF and combined in order to feed the power amplifier and be transmitted. This RF signal will be coupled to a feedback loop that is composed by a subsampling receiver, i.e., a BP filter, an S&H and an ADC. The subsampling receiver reduces the power consumption and the complexity in comparison with the typical feedback loops for linearization and it is employed to extract the IF signal which be digitally down-converted in order to obtain the baseband nonlinear signals y1 and y2. These baseband signals, besides xpd1 and xpd2, will feed the digital analyze block in order to obtain the necessary coefficients that will be employed as inputs by the pre-distorted blocks, besides the input signals x1 and x2, in order to adjust the pre-distorters dynamically. Chapter 3: Subsampling receivers 83 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Pre-distorter Pre-distorter DAC DAC RF up-converter RF up-converter S&H ADC Digital down-conversion Analyzing Stage Dual-band power amplifier Coupler x1 x2 xpd1 xpd2 y1 y2 Figure 3.22 Dual-band digital predistortion with subsampled feedback loop 3.6 References [3.1] J. R. G. Oya, A. Kwan, F. Muñoz, F. M. Ghannouchi, M. Healoui, F. Márquez, E. López-Morillo, A. Torralba, “Subsampling Receivers with Applications to Software Defined Radio,” Data Acquisition, InTech, Chapter 7, pp. 165-194, 2012. [3.2] C. L. Phillips, E. Riskin, “Signals, Systems and Transforms,” 4th Edition, Prentice Hall, Upper Saddle River, NJ, 2008. [3.3] R. Vaughan, N. Scott, D. White, “The Theory of Bandpass Sampling,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 19731984, Sep. 1991. [3.4] R. G. Lyons, “Understanding Digital Signal Processing,” Prentice Hall, Upper Saddle River, NJ, 2001. [3.5] C. Azeredo-Leme, “Clock Jitter Effects on Sampling: A Tutorial,” IEEE Circuits and Systems, vol.11, no. 3, pp. 26-37, 2011. [3.6] B. Brannon, A. Barlow, “Aperture uncertainty and ADC system performance,” Analog Devices, Inc., Application Note AN-501, 2006. [3.7] Y. R. Sun, “Generalized Bandpass Sampling Receivers for Software defined Radio,” Doctoral Dissertation, School of Information and Communication Technology (ICT), Stockholm, Sweden, 2006. [3.8] S. Karvonen, “Charge-Domain Sampling of High Frequency Signals with Embedded Filtering,” Doctoral Dissertation, Faculty of Technology, Department of Electrical and Information Engineering, University of Oulu, Finland, Jan. 2006. 84 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [3.9] J. R. G. Oya, A. Jurado, F. Muñoz, A. Torralba, “High Frequency Analog-to-Digital Conversion Based on Subsampling”, XXIV Conference of Design of Circuits and Integrated Systems (DCIS’2009), Zaragoza, Spain, Nov. 2009. [3.10] V. Arkesteijn, E. Klumperink, B. Nauta, “Jitter requirements of the sampling clock in software radio receivers,” IEEE Trans. Circuits Syst. II, vol. 53, no. 2, pp. 90–94, Feb. 2006. [3.11] W. Kester, “Converting oscillator phase noise to time jitter,” Analog Devices, Inc., Tutorial MT-008, 2009. [3.12] T. Lee, A. Hajimiri, “Oscillator phase noise: A tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326–335, Mar. 2000. [3.13] D. Lee, “Analysis of jitter in phase-locked loops,” IEEE Trans. Circuits Syst. II, vol. 49, no. 11, pp. 704–711, May 2002. [3.14] M. R. Yuce, W. Liu, “Alternative Wideband Front-End Architectures for Multi-Standard Software Radios,” IEEE 60th Vehicular Technology Conference (VTC’2004), vol. 3, pp. 1968-1972, Fall 2004. [3.15] J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado, A. J. Garrido, J. Baños, “Data Acquisition System Based on Subsampling for Testing Wideband Multistandard Receivers," IEEE Transactions on Instrumentation and Measurements, vol. 60, no. 9, pp. 3234-3237, Sep. 2011. [3.16] H. Pekau, J. W. Haslett, “A comparison of analog front end architectures for digital receivers,” Canadian Conference on Electrical and Computer Engineering (CCECE’2005), pp. 1073-1077, 2005. [3.17] M. B. Dadi, R. Bouallegue, “On the RF Subsampling ContinuousTime ΣΔ Downconversion Stage for Multistandard Receivers,” International Conference on Computer Engineering and Technology (ICCET), vol. 6, pp. 167-171, June 2010. [3.18] A. I. Hussein, W. B. Kuhn, “Bandpass Σ∆ modulator employing undersampling of RF signals for wireless communication,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 7, pp. 614–620, July 2000. [3.19] M. B. Dadi, R. Bouallegue, “Subsampling Continuous-Time Bandpass ΣΔ Modulator for Radio Frequency A/D Conversion,” 10th International Conference on Information Sciences Signal Processing and their Applications (ISSPA’2010), pp. 181-184, 2010. Chapter 3: Subsampling receivers 85 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [3.20] S-W. M. Chen, R. W. Brodersen, “A Subsampling Radio Architecture for Ultrawideband Communications,” IEEE Transactions on Signal Processing, vol. 55, no. 10, pp. 5018-5031, Oct. 2007. [3.21] Y. Vanderperren, W. Dehaene, G. Leus, “A Flexible Low Power Subsampling UWB Receiver Based on Line Spectrum Estimation Methods,” IEEE International Conference of Communications (ICC’2006), vol. 10, pp. 4694-4699, 2006. [3.22] S. Roy, J. R. Foerster, V. S. Somayazulu, D. G. Leeper, “Ultrawideband radio design: The promise of high-speed, short-range wireless connectivity,” Proceedings of the IEEE, vol. 4, no. 2, pp. 295–311, Feb. 2004. [3.23] G. R. Aiello, G. D. Rogerson, “Ultra-wideband wireless systems,” IEEE Microwave Mag., vol. 4, no. 2, pp. 36–47, June 2003. [3.24] J. Zhang, T. Abhayapala, R. Kennedy, “Principal Components Tracking Algorithms for Synchronization and Channel Identification in UWB Systems,” IEEE Eighth International Symposium on Spread Spectrum Techniques and Applications, pp. 369-373, Sept. 2004. [3.25] A. Kwan, S. A. Bassam, F. M. Ghannouchi, “Sub-sampling Technique for Spectrum Sensing in Cognitive Radio,” IEEE Radio and Wireless Symposium (RWS’2012), pp. 347-350, 2012. [3.26] S. A. Bassam, A. Kwan, W. Chen, M. Helaoui, F. Ghannouchi, “Subsampling Feedback Loop Applicable to Concurrent Dual-Band Linearization Architecture,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no.6, part 2, pp. 1990-1999, 2012. [3.27] F. M. Ghannouchi, O. Hammi, “Behavioral modeling and predistortion,” IEEE Microwave Magazine, vol. 10, no. 7, pp. 52–64, Dec. 2009. [3.28] S. A. Bassam, M. Helaoui, F. M. Ghannouchi, “Crossover Digital Predistorter for the Compensation of Crosstalk and Nonlinearity in MIMO Transmitters,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1119-1128, May 2009. 86 Chapter 3: Subsampling receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS CHAPTER 4 DATA ACQUISITION SYSTEMS BASED ON SUBSAMPLING FOR TESTING WIDEBAND MULTISTANDARD RECEIVERS CHAPTER CONTENTS 4.1 Data acquisition systems based on COTS .............................................................. 89 4.1.1 Choice of components ....................................................................................... 89 4.1.2 Experimental results .......................................................................................... 90 4.1.2.1 S&H characterization ............................................................................ 90 4.1.2.2 Subsampling receiver characterization ................................................. 92 4.2 Data acquisition systems based on PCB ............................................................... 101 4.2.1 PCB design ...................................................................................................... 101 4.2.2 Experimental results ........................................................................................ 103 4.3 Noise performance optimization based on multiple clocking techniques ............ 104 4.3.1 Theoretical study ............................................................................................. 105 4.3.2 Experimental results ........................................................................................ 106 4.3.2.1 COTS level .......................................................................................... 107 4.3.2.2 PCB level ............................................................................................ 110 88 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 4.4 Comparison with other implemented multi-standards receivers ........................... 112 4.5 References ............................................................................................................. 116 As described in Chapter 2, if a multi-standard receiver is implemented by stacking different receivers for different standards into a single receiver, the area and power consumption will be extremely high. Therefore, a properly designed multi-standard receiver must share the hardware resources and use tunable and programmable devices, reducing the area and power consumption, which is a very important approach for battery power devices. Otherwise, for multi-standard applications such as instrumentation or validation, the main constraint is the capability of covering the maximum number of standards as possible. A data acquisition board based on subsampling for high performance lowcost multi-standard test equipment is presented in this chapter. Due to the necessity of flexible and low cost receivers in the test industry, the selected architecture is based on subsampling techniques. Previously, a state of the art study and an experimental evaluation at COTS level were performed in order to validate the design and determine the real specifications of the data acquisition system. With a signal bandwidth of 20 MHz it achieves 8.5 bit resolution for a programmable carrier frequency ranging from 0 up to 3.3 GHz, and more than 8 bit resolution up to 4 GHz. By a proper selection of the center frequency and signal bandwidth, the proposed board can be used to digitize the signal in most of present wireless standards. This design is intended to be part of a test system; that is, the input signal of the subsampling receiver is assumed to be filtered and free of interferences. A last section describes the achieved improvement of the noise performance by using two clocking stages architecture. This approach allows the sampling frequency of the first stage to increase, resulting in a lower contribution of the first S&H to the total folded thermal noise. This section is structured in a first part dedicated to the theoretical study, where the expressions of the expected improvement are deduced, and a second part dedicated to the experimental validation of these techniques. Considering a signal bandwidth of 20 MHz, the improved data acquisition system achieves an ENOB of more than 9 bits for a programmable carrier frequency up to 2.9 GHz and 8 bits up to 6.5 GHz, presenting an improvement in the resolution of 0.5-1 bit. The chapter finalizes presenting a comparison with other implemented multi-standard receivers. Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 89 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 4.1 Data acquisition systems based on COTS 4.1.1 Choice of components Since the data acquisition system is based on commercial devices, they will have to be chosen in order to minimize the effects of the main problems encountered using subsampling, i.e., jitter and folded thermal noise, as detailed in Chapter 2. These non idealities fix the specifications of the main building blocks of the system, i.e., the S&H and the ADC. After a study on commercial components, we decided to use an external S&H before the ADC since an internal S&H bandwidth is limited to 3 GHz approximately with a resolution around 8 bits. However, when using an external S&H, it is possible to obtain a higher resolution for a wider bandwidth. This is a feasible alternative because the S&H can subsample the RF inputs covering a high analog bandwidth and the obtained IF replica can be converted to digital by a high resolution, intermediate frequency ADC. After realizing a study of the state of the art, the chosen S&H is the Inphi 1821 TH [4.1], with the following features: Wider bandwidth (18 GHz), in order to cover most of wireless communication standards. Minimum aperture jitter (50 fs). Integrated noise over the first Nyquist band (clocking at 1 GHz) equal to 0.64 mV. This value is very similar to the other studied S&H from Hittite [4.2] or Teledyne [4.3]. Wider frequency range (0-6 GHz) for 10-bit linearity. Although the maximum sampling frequency is equal to 2 GS/s, this S&H has the capability to sample at the interested frequency (around 500 MS/s) for this application. This requirement (500 MS/s) is given by the maximum sampling frequency for commercial 10-bit A/D converters, since using a maximum sampling frequency is convenient in order to reduce the overlapping noise effects. Concretely, the A/D converter chosen is E2V AT84AS001 [4.4]. The rest of components will be described as they are utilized in the experimental characterization that is detailed in the following section. 96 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.7 Measured SFDR vs. input signal amplitude 4.1.2.2.2.3 3rd order intermodulation distortion (IMD3) measurement For these experiments a single tone modulated in amplitude (AM modulation) without carrier suppression is employed as input and, therefore, the signal input is composed by three tones equally spaced 1 MHz. Figure 4.8 illustrates the IM measured for the same input frequencies (1, 2 and 3 GHz) clocking at the optimal sampling frequency. In this case the input amplitude must be reduced in order to optimize the performance, distributing the total energy in the three different tones. Although the characterization of SNDR for the all frequency range has been implemented for a single tone case, as described in the following sections, it is possible to observe how there is an amplitude range (around -3 dBm) where the obtained IMD3 is not a problem and its SNDR have acceptable values, i.e., very close to the optimal performance. Therefore, using several tones as input in this amplitude range would lead to very similar SNDR results as described in the following sections. -3 -2 -1 012345 50 52 54 56 58 60 62 64 66 68 Ain (dBm) SFDR (dB) Fin=1001 MHz y Fs=445,3 MHz Fin=2001 MHz y Fs=471,2 MHz Fin=3001 MHz y Fs=480,4 MHz Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 97 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.8 Measured IM vs. input amplitude 4.1.2.2.2.4 Subsampling properties in the implemented system As described about the S&H characterization, this implemented receiver at COTS level can be used to illustrate some subsampling effects studied in the theoretical sections. Firstly, the dependency of the overlapping thermal noise within band signal on the subsampling frequency was experimentally characterized, with its effect illustrated in Figure 4.9 [4.21]. This figure represents ENOB obtained for different optimal subsampling frequencies of an input signal at 2001 MHz with 20 MHz of input bandwidth. As expected the total resolution is decreased when lower sampling frequencies are used. The same effect can be appreciated from Figure 4.10 and Figure 4.11, where it is possible to observe how the noise floor increases in the case of using the lowest sampling frequency (Figure 4.11). -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 20 25 30 35 40 45 50 55 60 65 70 Ain (dBm) IM (dB) Fc=1001 MHz y Fs=444,9 MHz Fc=2001 MHz y Fs=470,8 MHz Fc=3001 MHz y Fs=480,2 MHz 98 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.9 Measurement of the overlapping thermal noise: ENOB obtained for different optimal sampling frequencies Figure 4.10 Output spectrum of a 2001 MHz input signal subsampled at 470.8 MHz 200 250 300 350 400 450 500 0 1 2 3 4 5 6 7 8 9 fs (MHz) enob 10 3 10 4 10 5 10 6 10 7 10 8 10 9 0 20 40 60 80 100 120 Hz dBm Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 99 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.11 Output spectrum of a 2001 MHz input signal subsampled at 216.3 MHz Another interesting measurement is on the influence of the jitter, which is more critical at higher input frequencies. This effect is illustrated in Figure 4.12 [4.21], showing the ENOB obtained for different input frequencies using the optimal subsampling frequency immediately less than 500 MHz and an input bandwidth of 20 MHz. Figure 4.12 Measurement of the jitter noise: ENOB obtained for different input frequencies 1000 1500 2000 2500 3000 3500 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 fc (MHz) enob 10 3 10 4 10 5 10 6 10 7 10 8 10 9 0 20 40 60 80 100 120 Hz dBm 100 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 4.1.2.2.2.5 Measured resolution for all the input range Finally, the total resolution of the proposed system is illustrated in Figure 4.13 [4.21]. These results are obtained for an input frequency up to 3.3 GHz integrating in an input bandwidth of 20 MHz and clocking at a frequency close to the optimal sampling frequency immediately lower than 500 MHz. Therefore, these final results show a data acquisition system at COTS level that converts to digital signals with the following resolution: Around 9 bits up to 2 GHz input frequency. More than 8 bits up to 3.1 GHz input frequency. Figure 4.13 ENOB vs. input frequency The system performance obtained from measurements is summarized in Table 4.1. As an example, Figure 4.14 [4.21] illustrates the output spectrum for a 3 GHz input frequency and a 480.2 MHz sampling frequency. 500 1000 1500 2000 2500 3000 3500 0 1 2 3 4 5 6 7 8 9 10 Fin (MHz) enob Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 101 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Figure 4.14 Output spectrum for a 3 GHz input frequency Table 4.1 System performance at COTS level Maximum Input Frequency 3.1 GHz Signal Bandwidth 20 MHz Sampling Frequency <500 MHz ENOB (SNDR) >8.1 bits SFDR >61.8 dBc Voltage Supply S&H -5,2 V Voltage Supplies ADC 5 V (Analog), 3.3 V (Digital, Output) Power Consumption 3.7 W 4.2 Data acquisition systems based on PCB 4.2.1 PCB design A data acquisition module at PCB level for high performance low-cost multi-standard test equipment was presented in [4.22]. This work provides high resolution over a large bandwidth with only a low-jitter wideband S&H and an intermediate frequency ADC, by means of subsampling. Using commercial devices on a multilayer printed circuit board, experimental results showed more 103104105106107108109 -20 0 20 40 60 80 100 120 Hz dBm BW=20MHz 102 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS than 8 bits resolution for a 20 MHz signal bandwidth with up to 3.8 GHz center frequency, enough to cover the requirements of test systems for most of present wireless communication standards. These commercial devices are the same that used at COTS level, i.e., the S&H Inphi 1821TH and the ADC E2V AT84AS001. These devices are the main components of the proposed data acquisition system for which a multi layer PCB prototype was designed and fabricated (Figure 4.15 [4.22]). Moreover, this prototype includes other components, such as baluns [4.23], bias tees [4.24] and LP passive filters (Minicircuits LFCN-160 [4.25]). Thanks to a higher availability of surface mount devices (SMD), the chosen filters let to implement a better adjustment of the filtering stage because its cutoff frequency is lower and, therefore, the 2nd order harmonics, which are in the 200-250 MHz9, are more attenuated. This design uses a Class 7 board with DE104i FR4 dielectric, six metal layers and microstrip lines adapted to 50 . The features of this class and this dielectric are obtained from [4.26] and are detailed in Appendix B. On the other hand, the rules and expressions employed to adapt the components (designing the dimensions of traces and layers) were obtained from [4.27] and also are described in Appendix B. S&H IN+ INCLK+CLKADC IN+ INOUT+ OUTOUT D11-D012 Filter LP Filter LP Bias tee Bias tee Balun CLK+CLKBalun Figure 4.15 Block diagram and designed PCB prototype Employing the external metal layers (1 and 6) for signals, the adjacent metal layers for ground (2 and 5) and the most internal layers (3 and 4) for power supplies, the resultant stack-up is as showed in Figure 4.16, which follows a 9 Since the chosen optimal sampling frequency is in the range of 400-500 MHz in order to fold the desired IF replica to fs/4, the 2nd order harmonic will be located in the range of 200-250 MHz. Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 103 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS typical structure proposed by the manufacturer Labcircuits [4.26] and has a thickness equal to 1.22 mm. Copper (Signal) Copper (Signal) Copper (Ground) Copper (Ground) Copper (Power) Copper (Power) Prepreg Prepreg Prepreg Core Core 0.669 mils 0.669 mils 0.669 mils 0.669 mils 0.669 mils 0.669 mils 3.397 mils 3.397 mils 6.693 mils 6.693 mils 6.693 mils Figure 4.16 Implemented stack-up The circuit was carefully laid out in order to minimize the jitter effect. The distance between signal tracks, pads and metal layers was carefully chosen in order to reduce crosstalk and inter-symbol interference, which cause jitter. Other rules followed to reduce jitter were a correct decoupling from the power lines and the signal planes employing the technique called picket fences [4.28], consisting in placing closely spaced VIAs (vertical interconnect access) between different ground planes. A typical distance between VIAs equal to 1/20 wavelength (λ) was selected. Finally, the dimensions of the designed PCB are 16.05 x 10.64 cm2. 4.2.2 Experimental results The data acquisition system was experimentally characterized, with the obtained performance summarized in Table 4.2 [4.22]: Table 4.2 System performance at PCB level Signal Bandwidth 20 MHz Signal Input Frequency 3.3 GHz Sampling Frequency <500 MHz ENOB (SNDR) >8.2 bits Linearity (SFDR) >9.49 bits IMD3 >60.4 dB Power Consumption 3.7 W 104 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS The measured SFDR and IMD3 were about 60 dB regardless of the input frequency, and thus the ENOB (based on the maximum SNDR) is larger than 8.2 bits for sinusoidal input signals up to 3.3 GHz. Figure 4.17 [4.22] shows the system resolution as a function of the carrier frequency up to 20 GHz, for a sampling frequency very close to 500 MHz. The results provide a useful characterization of the system response and clearly show the effect of jitter. Up to 3.3 GHz there is no significant influence of jitter, as the ENOB is nearly constant in this range. The resolution falls as the input frequency increases, mostly due to the influence of jitter. The system response provides an ENOB larger than 7 bits up to 6 GHz, 6 bits up to 13 GHz and 5.5 bits at 20 GHz. Figure 4.17 ENOB vs. input frequency (20 MHz signal band, up to 20 GHz input carrier frequency) Therefore, this work presents a data acquisition module for testing wireless receivers based on subsampling, which covers most present wireless communication standards requirements, with an ENOB between higher than 8 bits up to 4 GHz center frequency for a 20 MHz signal bandwidth. 4.3 Noise performance optimization based on multiple clocking techniques As described in Section 4.2, a limitation of the data acquisition systems based on subsampling is the maximum sampling frequency, which will be given by the ADC specification and is around 400-500 MHz for commercial ADCs with large enough resolution. In order to reduce the folded noise effect, this section describes a method to improve the resolution, which employs two consecutive subsampling stages 1091010 4 5 6 7 8 9 fin (Hz) ENOB Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 105 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [4.29]. The use of two subsampling processes allows the sampling frequency of the first stage to be increased, resulting in a lower contribution of the first S&H to the folded thermal noise, such as described in Section 3.4.1. 4.3.1 Theoretical study Figure 4.18 shows two different alternatives to implement a subsampling based receiver. Figure 4.18a illustrates the scheme for a unique subsampling process implemented in Section 4.2 while Figure 4.18b illustrates the scheme with two different clocks. The sampling frequency of the first S&H in Figure 4.18b is selected between 1.2 GHz and 2 GHz (given by the maximum sampling frequency clock specifications of the S&H), obtaining a band-limited signal at the output. As the first sampling frequency is very large the folded thermal noise added by this stage is reduced. After filtering, the resulting signal is subsampled again by a second S&H at 400-500 MHz. However, some drawbacks of the proposed system are a higher complexity and power consumption than the one stage subsampling receiver. =1-20 GHz Filter LP = 400-500 MHz =1-20 GHz Filter BP clock = 1,2-2 GHz (b) (a) c f c f s f 1s f S&H1 clock S&H1 clock S&H2 ADC clock S&H2 ADC = 400-500 MHz 2s f Figure 4.18 Clocking schemes for: (a) a unique clock and (b) two different clocks The S&H in Figure 4.18 can be modeled as shown in Figure 3.14a, where the switch introduces thermal noise of power spectral density Sin(f)=4kTRon that will be filtered by the RC circuit, resulting in an output noise power of Pn,out=kT/C, as was obtained in Section 3.4.2. In this section, the output noise was considered to be a Gaussian thermal noise filtered by a brick-wall filter of bandwidth equal to Beff (noise bandwidth), as shown in Figure 3.14c: dB on eff f CR B3 24 1 (4.1) Where f3dB is the 3-dB bandwidth of the RC filter. On the other hand, the SNR in [-Beff ,Beff] is defined as [19]: oi sNmN P SNR )1( (4.2) 112 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 4.4 Comparison with other implemented multistandards receivers There are two main classifications of multi-standards receivers. In section 2.2.6 a comparative of multi-standard receivers about digitalization techniques (i.e., mixing or subsampling based systems) was introduced. Although subsampling techniques have some problems as the folded thermal noise effect or the aliasing in multi-band scenarios (as detailed in Chapter 4), for SDR applications are very convenient in order to place, using a few building blocks, the analog-to-digital conversion stage as close the antenna as possible. Moreover, multi-standards receivers might be classified about their band strategy, i.e., if they implement a narrow-band strategy or a wide-band strategy. A narrow-band strategy is implemented by the receivers that are designed for some specifics standards, employing dedicated channels, while a wide-band strategy is implemented by the ones that cover a higher number of wireless communication standards. Therefore, narrow-band receivers might provide a finer optimization for specific standards while wide-band receivers might be considered universal receivers and are used for more general applications. Although these wideband solutions are more flexible, their main inconvenience is the RF front-end must meet the requirements for each standard and they are not optimum for any standard. Since it has been described in this chapter, the works presented in [4.22,4.29] might be an approach to the idea of universal receiver for SDR applications. Other works have been published, which can be considered multistandard receivers. However, some of these works are based on mixing techniques, losing part of the flexibility and simplicity provided by the subsampling based systems. On the other hand, there are also multi-standard receivers, which although they are based on subsampling, are optimized for a given number of wireless standards, without covering all the applications. Examples in both directions are present in the literature. [4.36,4.37] are examples of works which employ wideband strategies. [4.37] presents a receiver front-end for multi-standard wireless applications, its analog bandwidth being up to 3.5 GHz. [4.36] presents a wideband-multi-standard system that can be considered as an universal receiver, covering input frequencies between 0.8 and 6 GHz and being based in mixing techniques. Although [4.36] is a more complex solution than [4.29], this work has a large tuning range and other benefits as a high linearity and low power consumption, because of its implementation in IC (Integrated Circuit). As a main inconvenience, since [4.36,4.37,4.22,4.29] are wideband solutions and, therefore, they are not optimum for any standard. Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 113 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS About the narrow-band strategy, [4.34] proposes an alternative multistandard receiver solution separating into two different RF channels, one for the 2.4 GHz and 5 GHz WLANs and the other for the GSMs. The different channels share a common programmable baseband, this solution being highly efficient, because every path is optimized to a specific standard. On the hand, the main drawback of this work is, besides the limitation of the number of standards, the area consumption, due to the high selectivity is achieved by means of many inductors. An example of a solution based on narrow-band strategies is showed in Figure 4.23a [4.38]. In this receiver, dedicated Bluetooth and GPS links allow connectivity while making a phone call or/and sending or receiving data through a WLAN. The WLAN path connects to IEEE802.11a/b/g/n routers, while the cellular-dedicated channel can switch from one of the GSM bands to the UMTS/WCDMA. Moreover, the selection is provided by off chip SAW filters, which relax the linearity requirements. Other works provide a high level of hardware sharing, as [4.39], where the different specific standards employ a common acquisition and digitalization stages. This work proposes a solution for Bluetooth, GSM, UMTS and WLAN, where the last three standards share the same circuitry after the filter bank (Figure 4.23b), allowing reuse some building blocks in the receiver architecture. This hardware sharing maximization means a minimum area consumption, making it possible thank to all the considered standards, except Bluetooth, do not need to be covered at the same time, i.e., when an application is active, the others can be switched off in order to save power. On the other hand, data acquisition systems for different communications standards use subsampling techniques in order to process high frequency signals with only a few components. [4.40] proposes a subsampling receiver for three different standards (GSM, UMTS and IEEE 802.11g), which validates these topologies at a simulation level in order to be applied for multi-standard radio design. An additional goal of this work is the design of the RF and IF filters for the different standards, in order to avoid the aliasing caused by the subsampling process. In other published works [4.41,4.42], the receivers based on subsampling are implemented experimentally only for fixed bands. [4.41] proposes a low noise subsampling implementation for the 2.1 GHz band, and [4.42] for 2.4 GHz (IEEE 802.11a/g WLAN standards). In [4.41] an IC receiver designed in 0.18 µm CMOS, whose main goal is a tunable LC filter implementation, is proposed. [4.42] shows a 0.18 µm CMOS receiver which represents the most complete subsampling receiver reference, thanks to the optimization performed for parameters as thermal noise level, jitter-induced noise and nonlinearity. Finally, there are also receivers 114 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS based on subsampling for UWB applications, like the one in [4.43], which operates in the 3.1-10.6 GHz band with low power consumption. 0º90º VGA1VGA2 VGA1VGA2 VCO ADC ADC n n Tunable SAW Multi-Band LNA Digital Gain and Band Selection Cellular Radios 0º90º VGA1VGA2 VGA1VGA2 VCO ADC ADC n n Tunable SAW Multi-Band LNA Digital Gain and Band Selection Wireless LANs GPS SAW GPS Receiver Path Bluetooth SAW Bluetooth Receiver Path (a) 0º90º VGA1VGA2 VGA1VGA2 VCO ADC ADC n n Multi-Band LNA Digital Gain and Band Selection Bluetooth SAW Bluetooth Receiver Path (b) Figure 4.23 Multi-standard receiver architectures proposed in [4.38] (a) and [4.39] (b) Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 115 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Finally, Table 4.6 [4.29] shows the specifications for most common wireless communication standards [4.34] and the results obtained in some of these previously published works about the noise performance. These results are compared with the obtained in [4.22] in order to observe the benefits of implement a multiple clock technique for multi-standard receivers based on subsampling. It can be seen that, employing the data acquisition system designed in [4.29], only the ENOB specifications for IEEE 802.11a are not achieved, although they are very close. Moreover, note that some specifications, like Noise Figure (NF) for UMTS (I) and 802.11b/g, or resolution for Bluetooth, were not achieved without the improvement proposed in [4.29], i.e., when a unique clock source is used [4.22]. Comparing with the other published work, similar results about NF and Noise PSD can be observed with respect to [4.29], showing a larger influence of the jitter (i.e., reducing the resolution with the input frequency) in the work presented in [4.29]. Table 4.6 Standard specifications and results Standard GSM 1800 UMTS (I) Bluetooth 802.11b/g 802.11a Standard requirements Carrier Freq. (MHz) 1805.21879.8 21102170 2400 2400 5000 Signal Bandwidth (MHz) 0.2 5 1 20 20 ENOB (bits) 9 6 11 8 9 NF (dB) 9.3 4.6 10.7 6.5 18.2 Experimental results of previously published acquisition systems ENOB [4.22] (bits) 11.76 9.56 10.36 8.2 7.41 NF [4.22] (dB) 6.1 6.5 8.3 8.3 13.1 NF [4.34] (dB) 5.2 5.6 5.8 NF [4.37] (dB) 5.8 6 6.5 6.5 NF [4.40] (dB) 7.5 7.2 Noise PSD [4.42] (dBm/Hz) -131 Experimental results of [4.29] ENOB (bits) 12.47 9.97 10.86 8.7 8.34 NF (dB) 3.6 4.4 6.2 6.2 9.3 Noise PSD (dBm/Hz) -129.7 -128.8 -126.9 -126.9 -123.8 116 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 4.5 References [4.1] 1821TH, 18 GHz Bandwidth 2 GS/s THA, Inphi Corps. Datasheet. [4.2] HMC660LC4B, 0.02-4.5 GHz Wideband 3 GS/s Track-and-Hold Amplifier, Hittite Microwave Corporation. Datasheet. [4.3] RTH010-060 Series, 8-16 GHz Bandwidth 1-4 GS/s Dual Track-andHold, Teledyne Scientific Company. Datasheet. [4.4] AT84AS001, 12-bit 500 Msps ADC, E2V Technologies. Datasheet. [4.5] 1821TH, 18 GHz Track and Hold, Inphi Corps. Application Note. [4.6] On line: www.minicircuits.com [4.7] E8257D PSG, Microwave Analog Signal Generator, Agilent Technologies. Datasheet. [4.8] SMIQ, Vector Signal Generator, Rohde & Schwarz. Datasheet. [4.9] 16720-A, Measurements Modules for the 16900 Series, Agilent Technologies. Datasheet. [4.10] ZAPDJ-2, Power Splitter/Combiner 2 Way-180º 50Ω, Minicircuits. Datasheet. [4.11] ZFSCJ-2-4, Power Splitter/Combiner 2 Way-180º 50Ω, Minicircuits. Datasheet. [4.12] ZFSCJ-1-2, Power Splitter/Combiner 2 Way-180º 50Ω, Minicircuits. Datasheet. [4.13] BLK-89, DC-Block 50 Ω, Minicircuits. Datasheet. [4.14] ZFTB-4R2GW-FT, Bias-Tee 50 Ω Wideband, Minicircuits. Datasheet. [4.15] ANNE-50, Termination SMA 50 Ω, Minicircuits. Datasheet. [4.16] SLP-250, Low Pass Filter 50 Ω, Minicircuits. Datasheet. [4.17] Cable, 2-FT SMA M-N M, Minicircuits. Datasheet. [4.18] Cable, 1.5-FT SMA M-SMA M, Minicircuits. Datasheet. [4.19] Adapter, SMA F-SMA F, Minicircuits. Datasheet. [4.20] AT84AS001-EB, Evaluation Board, E2V Technologies. User Guide. [4.21] J. R. G. Oya, A. Jurado, F. Muñoz, A. Torralba, “High Frequency Analog-to-Digital Conversion Based on Subsampling”, XXIV Chapter4: Data acquisition systems based on subsampling for testing wideband multi-standard receivers 117 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Conference of Design of Circuits and Integrated Systems (DCIS’2009), Zaragoza, Spain, Nov. 2009. [4.22] J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado, A. J. Garrido, J. Baños, “Data Acquisition System Based on Subsampling for Testing Wideband Multistandard Receivers," IEEE Transactions on Instrumentation and Measurements, vol. 60, no. 9, pp. 3234-3237, Sep. 2011. [4.23] SBTCJ-1W, Power Splitter/Combiner 2 Way-180º 50Ω, Minicircuits. Datasheet. [4.24] TCBT-6G, Bias-Tee 50 Ω Wideband, Minicircuits. Datasheet. [4.25] LFCN-160, Low Pass Filter 50 Ω, Minicircuits. Datasheet. [4.26] On line: www.labcircuits.com [4.27] K. Mitzner, “Complete PCB Design Using OrCAD Capture and Layout,” Newnes & Elsevier, Burlington, MA, 2007. [4.28] D. Brooks, “Signal Integrity and Printed Circuit Board Design,” Prentice Hall, Upper Saddle River, NJ, 2003. [4.29] J. R. G. Oya, F. Muñoz, A. Torralba, A. Jurado, F. Márquez, E. López-Morillo, “Data Acquisition System Base on Subsampling using Multiple Clocking Techniques,” IEEE Instrumentation and Measurements, vol. 61, no. 8, pp. 2333-2335, Aug. 2012. [4.30] R. Vaughan, N. Scott, D. White, “The Theory of Bandpass Sampling,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 19731984, Sep. 1991. [4.31] J. R. G. Oya, A. Jurado, F. Muñoz, A. Torralba, F. J. Márquez, E. López-Morillo, “Multiple Clocking High Analog-to-Digital Conversion Based on Subsampling”, XXVI Conference of Design of Circuits and Integrated Systems (DCIS’2011), Albufeira, Portugal, Nov. 2011. [4.32] SLP-550, Low Pass Filter 50 Ω, Minicircuits. Datasheet. [4.33] SHP-300, High Pass Filter 50 Ω, Minicircuits. Datasheet. [4.34] F. Agnelli et al., “Wireless Multi-Standard Terminals: System Analysis and Design of a Reconfigurable RF Front-End,” IEEE Circuits and Systems Magazine, vol. 6, no.1, pp. 38-59, Jan. 2006. [4.35] RBP-400, Band Pass Filter 50 Ω, Minicircuits. Datasheet. 118 Chapter 4: Data acquisition systems based on subsampling for testing wideband multistandard receivers SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [4.36] R. Bagheri et al., “An 800 MHz-6 GHz Software-Defined Wireless Receiver in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, j.41, no.12, pp. 2860-2876, Dec. 2006. [4.37] M. Vidojkovic, M. A. T. Sanduleanu, V. Vidojkovic, J. van der Tang, P. Baltus, A. H. M. van Roermund, “A 1.2V Receiver Front-End for Multi-Standard Wireless applications in 65nm CMOS LP”, 34th European Solid-State Circuit Conference (ESSCIRC 2008), pp. 414417, 2008. [4.38] F. Svelto, M. B. Vahidfar, M. Brandolini, “Reconfigurable Si RF Receiver Front-Ends for Multistandard Radios”, 1st European Conference on Wireless Technology, (EuWiT 2008), pp.33-36, 2008. [4.39] M. Brandolini, P. Rossi, D. Manstretta, F. Svelto, “Toward Multistandard Mobile Terminals-Fully Integrated Receivers Requeriments and Architectures”, IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, March 2005. [4.40] R. Barrak, A. Ghazel, F. Ghannouchi, “Optimized Multistandard RF Subsampling Receiver Architecture,” IEEE Transactions on Wireless Communications, vol. 8, no. 6, pp. 2901-2909, Jun. 2009. [4.41] H. Pekau, J. W. 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CHAPTER 5 SUBSAMPLING TECHNIQUES FOR NONLINEAR AND MULTI-BAND APPLICATIONS CHAPTER CONTENTS 5.1 Studied scenarios .................................................................................................. 121 5.2 Subsampling in nonlinear environments............................................................... 123 5.3 Subsampling for multi-band systems .................................................................... 123 5.4 Subsampling for multi-band systems in non linear environments ........................ 124 5.4.1 Implemented algorithm ................................................................................... 125 5.4.2 Subsampling applications for multi-band and nonlinear systems ................... 126 5.4.2.1 Spectrum sensing in cognitive radio ................................................... 127 5.4.2.2 Subsampling feedback loop for concurrent dual band power amplifier linearization ......................................................................................................... 129 5.4.3 Optimization of dual band receivers in nonlinear environments ..................... 132 5.4.3.1 Subsampling for concurrent dual band and nonlinear systems using multiple clocking techniques .............................................................................. 132 5.4.3.2 Optimization of the receiver architecture ............................................ 137 5.4.3.3 Experimental validation ...................................................................... 139 5.5 References ............................................................................................................ 143 120 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Chapter 5 describes the additional challenges of implementing subsampling techniques for multi-band and nonlinear applications. A first section of this chapter is dedicated to introduce the context where these applications are useful, while the next two sections introduce the previously published expressions to implement, separately, subsampling in multi-band and non linear scenarios. A fourth section integrates both effects, detailing the designed algorithm to find the valid sampling frequency ranges and describing an optimization of a particular case for dual band receivers in a nonlinear environment. This optimization is based on the multiple clocking techniques described in Chapter 4 and on a multifilter structure implementation between the S&H and the ADC. Finally this optimization is experimentally validated. Chapter 5: Subsampling techniques for nonlinear and multi-band applications 121 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 5.1 Studied scenarios Due to the emergence of several co-existing wireless technologies in the cellular industry, there is a trend to design multi-standard receivers targeting the optimization of their flexibility, simplicity and power consumption. The two main drawbacks of the systems based on subsampling are the jitter and the thermal folded noise, which make system implementation even more dificult for multi-band or non-linear applications. There is a challenge when using subsampling concurrently in a multi-signal environment and/or nonlinear conditions, because the replicas of the generated harmonics are folded back in the band of interest and may overlap with the desired signals. This issue was addressed in [5.1] where a universal formula for subsampling in nonlinear system was developed for single band applications. In dual band receiver applications, the main problem of subsampling is the possible overlapping between the replicas of the two desired signals in the IF frequency band. This problem was studied in [5.2] for multiband linear and non interfering environment. As one example of application, a dual band subsampling receiver has been proposed for use in a feedback loop of a dual band transmitter for linearization purposes [5.3] using digital predistortion. In [5.4] a subsampling receiver for dual band applications was proposed, due its simplicity, to allow the cognitive radio sense different bands and check and see if they are in use. In [5.4], the designed subsampling receiver does not consider any interferers, harmonics or intermodulation effects. This chapter extends the above study [5.3,5.4] by optimizing the SNR of concurrent dual-band signals at the receiver in a multi-signal or nonlinear environment. The requirement of increasing the analog bandwidth and reducing the effect of the folded noise leads to propose new receiver topologies with the objective of improving these features for a larger number of communication standards. Interferences and spurious signals in the received spectrum can be treated as intermodulation products using the same optimization technique that will be described later, so when these signals are subsampled the resulting aliasing components with these unwanted and spurious signals must not overlap with the desired signal. As an additional benefit, these extra conditions used in the sampling frequency selection can lead to more relaxed RF filter requirements, due to the known unwanted signals in the spectrum will not affect the desired signal bandwidth at IF and, therefore, they will be filtered more easily after being subsampled. 128 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS (a) (b) Figure 5.6 (a) Subsampling based receiver for spectrum sensing in cognitive radio systems and (b) measurement setup for validating spectrum sensing concept using subsampling receiver As an example for spectrum sensing using a subsampling receiver, two RF bands are selected: the official digital video broadcasting band at 698-752 MHz, and an unlicensed band at 902-928 MHz. With these two bands and using the algorithm described in the previous section, a subsampling frequency of 255 MHz is selected. Figure 5.6b [5.4] shows the measurement setup used for spectrum sensing. Two signal generators are used to obtain the two RF bands, then the bands are combined using a power combiner and passed into the receiver. A SP Devices development board using two TI ADS5474 ADCs [5.9,5.10] operating in a time interleaved manner is used as the subsampling device. A logic analyzer is used to capture the digital data streaming from the ADC board, while another signal generator provides a clock source for the ADC. A three channel signal is sent in the DVB band, while a 2 channel signal is sent in the unlicensed band. Different power levels are configured for each channel to simulate different received signals. Figure 5.7a shows the spectra of these two bands in the RF domain. Figure 5.7b [5.4] shows the two bands subsampled using a frequency of 255 MHz. Since the ADCs are operating in a time interleaving fashion, the differences between each ADC may cause gain mismatches and timing skew [5.11]. Chapter 5: Subsampling techniques for nonlinear and multi-band applications 129 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS (a) (b) Figure 5.7 Spectra of (a) the input RF signal to the receiver and (b) the subsampled RF signal for bands (698-752 MHz, 902-928 MHz) using a subsampling frequency of 255 MHz Figure 5.8 [5.4] shows the input signals overlaid with their subsampled output after digital demodulation. With the subsampling receiver, the captured signal has approximately a 50 dB signal to noise floor. (a) (b) Figure 5.8 Spectra of the input and filtered output baseband signals for the 698752 MHz band (a) and 902-928 MHz band (b) The technique may be extended to multiple bands, where changing the subsampling clock may allow different RF bands to be demodulated concurrently. In [5.4], the cognitive radio senses up to 14 bands, sensing two bands at any given time. 5.4.2.2 Subsampling feedback loop for concurrent dual band power amplifier linearization The power amplification (PA) unit is typically the most inefficient component in wireless transmitters. This is caused by an inverse relationship that exists between efficiency and signal quality based on the signal power being transmitted [5.12]. At low input power, efficiency is low and the amplifier operates in a linear behavior, which results in good signal quality at the amplifier output. However, operating the amplifier at its highest efficiency state close to the maximum output power causes the gain characteristics to become compressed, and the input-output relationship becomes nonlinear. The nonlinear behavior 130 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS reduces the in-band signal quality and causes out-of-band spectral regrowth. Nonlinearity is further complicated in a dual band operation, where the device produces many intermodulation and cross modulation signals. This inverse relationship causes difficulties for the wireless operator, and typically a linear operation mode is used such that signal quality is good, and spectral regrowth is minimal and does not cause interference in other channels. Digital predistortion allows for the operation of signal in the high efficiency region while reducing spectral regrowth and improving signal quality [5.13]. This is performed by analyzing the input and output signals of the power amplifier, and generating an inverse behavioral model (predistorter) of the amplifier. The cascade of both the digital predistorter and the power amplifier results in a linear gain at the output for the full power range. The proposed architecture was illustrated in Figure 3.22 (section 3.5.2). A dual band PA operating at 880 MHz and 1978 MHz is used to test the subsampling feedback loop for concurrent dual band linearization [5.3]. Two communication signals with 5 MHz bandwidths are sent at the center of these bands. The PA is predicted to have a 5th order nonlinearity, and all the harmonics, intermodulation, and cross-modulation products up to 4 GHz are accounted. In addition, a 25 MHz guard band is placed around each band frequency to account for the spectral regrowth that will happen during the initial analysis stage. The harmonics, cross-modulation, and intermodulation signals may be ignored; their only restriction is to not lie inside the guard band of the signals, in order to compute the regrowth effect at the DPD block when the signal is downconverted. The subsampling algorithm outlined in section 5.4.1 calculates the minimal subsampling frequency of between 619.7 MHz and 620.1 MHz. Figure 5.9a shows a simulation of the RF spectra of all the components from DC to 4 GHz, while Figure 5.9b shows the subsampled components using a frequency of 619.8 MHz [5.3]. Chapter 5: Subsampling techniques for nonlinear and multi-band applications 131 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS (a) (b) Figure 5.9 The (a) predicted RF fundamental and harmonics up to 4 GHz and (b) subsampled result using a sampling frequency of 619.8 MHz The same setup described in Figure 5.6b is used to generate the dual band signal, and capture the RF output. Figure 5.10a shows the RF spectra at the output of the PA [5.3]. Compared to Figure 5.9a, there is an extra term p, which is a 7th order intermodulation product at 436 MHz. The rejection of the i and j terms are due to the design of the PA output matching network. Figure 5.10b [5.3] shows the normalized spectra of the subsampled RF PA output. There is attenuation from the upper band signal caused by the limitation of the ADC’s bandwidth of 1.4 GHz. The captured time domain signal may be digital filtered and demodulated and to retrieve the amplifier output of the two bands, and further post-processing can determine the digital predistortion model. 132 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS (a) (b) Figure 5.10 (a) RF spectra at the output of the PA and (b) normalized spectra of the captured subsampled signal using an ADC operating at 619.8 MHz 5.4.3 Optimization of dual band receivers in nonlinear environments An analysis with the objective of noise performance optimization is presented in this section. An independent clock solution for the S&H, and ADC is proposed to limit the noise effects; and a bank of bandpass filters is used to filter out most of the aliased nonlinear and interfering components. Several different subsampling architectures and filter configurations are analysed in theoretical and measurement environments. 5.4.3.1 Subsampling for concurrent dual band and nonlinear systems using multiple clocking techniques The receiver performance is defined in terms of noise, linearity, sensitivity, dynamic range and bandwidth [5.14]. These parameters define the applicability of a receiver to be employed for a given standard. In the case to implement a multistandard receiver, it is necessary to maximize the analog input bandwidth and at the same time, the rest of parameters must be optimized in order to cover as many wireless communication standard requirements as possible. This part of the thesis is focused on an optimized concurrent dual-band subsampling receiver for noise performance and versatility, in order to cover most wireless communication standards. The optimization takes advantage of the flexibility proper of subsampling, it is possible to study different valid alternatives to clock the receiver in order to maximize its noise performance. In section 3.4 the main sources of noise in a subsampling receiver were described. Jitter noise mainly depends on the input signal frequency (which is a Chapter 5: Subsampling techniques for nonlinear and multi-band applications 133 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS characteristic of the standard), while increasing the sampling frequency can reduce the folded thermal noise. As described in section 4.3, clocking the S&H and the ADC with the same clock limits the maximum sampling frequency of the system to that of the ADC, which is usually, significantly lower than the maximum sampling frequency of the S&H. Otherwise, employing an additional higher frequency clocking the S&H it is possible to increase the SNR of the receiver. Moreover, for this dual-band application, additional degrees of freedom can be achieved using a multiple clock scheme, in order to cover a higher number of dual-band combinations of wireless communication standards. Figure 5.11 illustrates the folded noise (green line) for the single clock (Figure 5.11a) and the multiple clock (Figure 5.11b) cases, considering for both cases the same thermal noise level at the input of the S&H (red line) and from the ADC (blue line). Since the effective noise bandwidth of the S&H is typically much larger than that of the ADC, the improvement achieved at the S&H in Figure 5.11b is usually dominant. In Figure 5.11b a BP filter will be necessary in order to decrease the out-of-band noise folded by the second subsampling process, while a LP filter with a cutoff frequency equal to fs/2 is enough in Figure 5.11a. However, this BP filter might reduce the flexibility of the receiver when it is used in multi-band applications and in a nonlinear environment. This work tries to find the optimal filter bandwidth that reduces the folded noise, while avoiding a significant reduction in the number of valid sampling frequencies in order to find a high value within this range. S&H S&H ADC ADC Beff1 Beff1 Beff2 Beff2 fs fs1 fs2 fs/2 fs/2 fs1/2 fs2/2 (a) (b) Figure 5.11 Folded noise effects using single clock (a) and multiple clock (b) Figure 5.12 shows the effects of a third order nonlinearity when a dual band signal passes through a nonlinear subsampling receiver. In the first scenario the S&H and the ADC are clocked at the same rate. In the second scenario the clock rate of S&H and ADC has been chosen differently. Figure 5.12a presents the first scenario where both S&H and ADC are using the same clock rate. The two carrier frequencies at 880 MHz and 1.82 GHz are sampled at 400 MHz, this frequency being calculated by the algorithm described in section 5.4.1. Using this sampling frequency, Figure 5.12a also shows the different Nyquist bands at the S&H input, along which the input signals and their harmonics and 134 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS intermodulation products are distributed. The subsampled signals and their harmonics and intermodulation products are all folded to IF. After subsampling, the signal is filtered and converted to digital domain, where the Nyquist Theorem is met. Similarly, Figure 5.12b presents the scenario where the S&H and ADC use different clock rates. In order to reduce the folded noise effect, the S&H sampling frequency is increased to 2 GHz, while the input RF signal at the S&H is the same as in the case of Figure 5.12a. Since there is a second subsampling process, aliasing between the target signals and their harmonics and intermodulation products have to be avoided and, therefore, the second sampling frequency has to be carefully selected using the same method detailed in section 5.4.1. In this particular case, 400 MHz has been chosen to be the second sampling frequency. fs=400MHz f2=1.82GHz f1=880MHz -2f1+f2 -f1+f2 2f1 3f1 f1+f2 -f1+2f2 2f1+f2 2f2 S&H+LPF fs/2=200MHz 2f1+f2 -f1+2f2 2f2 -2f1+f2 f1+f2 -f1+f2 2f1 3f1 ADC 2f1+f2 fs/2=200MHz -f1+2f2 2f2 -2f1+f2 f1+f2 -f1+f2 2f1 3f1 fs=2GHz S&H+LPF fs/2=1GHz -2f1+f2 2f1 ADC 2f2 2f1+f2 3f1 f1+f2 -f1+2f2 -f1+f2 fs/2=200MHz (a) (b) Figure 5.12 Folded effects for harmonics and intermodulation products using a single clock (a) and multiple clock (b) techniques Besides optimizing the receiver on its noise performance, the architecture based on two independent clock sources is employed to find a valid sampling frequency for most of combinations in case of dual band RF input to a third order nonlinear receiver. From the work presented in [5.6] for some studied combinations it was not possible to find a sampling frequency without avoiding overlapping between the desired signals and their harmonics. With the objective to cover all the studied cases, a bank of filters between the S&H and the ADC was proposed to remove some harmonics in order to have more valid frequency ranges for the second sampling process. Only one filter in the bank of bandpass filters may be active at any given time. The general idea of this receiver is illustrated in Figure 5.13. BP1 BPn fs1 fs2 LNA S&H ADC DSP Figure 5.13 Optimized architecture based on multiple clocking and BP filters Chapter 5: Subsampling techniques for nonlinear and multi-band applications 135 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS These filters will remove some harmonics and intermodulation products relaxing the requirements to find a valid second sampling frequency. The drawback of this architecture is a more restrictive specification about where the desired signal must be folded by the S&H without being filtered. Therefore, in some cases, this restriction can lead to a low valid first sampling frequency (at the S&H), which leads to more folded noise than when an architecture without using a bank of filters is employed. Figure 5.14 demonstrates the subsampling frequency plan selection used for the optimized architecture. First, the dual band signal’s center frequencies at (f1, f2), bandwidths (BW1, BW2), and an estimate of the nonlinearity order of the system are used to predict the number of intermodulation, harmonics, and cross modulation products. Then, the algorithm outlined in section 5.4.1 generates the range of valid subsampling frequencies for the S&H, F1. A loop is entered to find the maximum subsampling frequency (less than or equal to the S&H maximum frequency operation), where both dual band signal’s subsampled IFs fall into one band pass filter in the filter bank, denoted by BPselected. A signal’s subsampled IF can be determined by the following equation: oddis f f floorifffremf evenis f f floorifffrem f s x sxs s x sx ifx 2/ ),( 2/ ),( 1 11 1 1 (5.5) where fx is the input frequency before subsampling and x is either 1 or 2, fifx is the frequency of the signal after subsampling, fs1 is the subsampling frequency, and rem(.) is the remainder of the division operation. 136 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Nonlinearity Order Band 1 f1, BW1 Generate intermodulation, harmonics, cross modulation Generate range of subsampling frequencies in the first stage, F1 fif11, fif12 both lie in one of BPFs (BPselected)? Select lower fs1 from F1 Compute fif11, fif12 from f1, f2 and fs1 Band 2 f2, BW2 Set fs1 to maximum available subsampling frequency fs1 NO YES fs2 Generate range of subsampling frequencies in the second stage, F2 Set fs2 to maximum available subsampling frequency Subsample band 1, band 2, intermodulation, harmonics, and cross modulation using fs1 Filter out of band signals using BPselected Compute fif21, fif22 from f1, f2, fs1 and fs2 STOP Figure 5.14 Algorithm flow diagram for computing optimal subsampling frequencies in the proposed architecture After determining the first valid subsampling frequency, fs1, all the signals generated by the nonlinearity are subsampled. The residual signals out of the bandpass filter band are removed from further analysis. The algorithm presented in section 5.4.1 is then re-used to generate another range of valid subsampling Chapter 5: Subsampling techniques for nonlinear and multi-band applications 137 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS frequencies for the ADC, F2. The subsampling frequency for the ADC, fs2, will be selected as the closest to the maximum sampling frequency of the ADC within the range F2. 5.4.3.2 Optimization of the receiver architecture In order to optimize the noise performance of a dual band receiver in a non linear scenario a particular case has been researched in [5.6], where seven input frequencies have been selected to study the selective combinations for different dual band applications. These chosen standards are WCDMA (V) at 880 MHz, GSM-DCS at 1.82 GHz, WCDMA (I) at 2.12 GHz, Bluetooth at 2.4 GHz, WiMAX at 3.5 and 5.8 GHz, and 802.11a at 5.2 GHz. Since the main focus is to cover the maximum number of standards, it is mandatory to use an S&H before the ADC in order to have enough analog bandwidth. The S&H features from Inphi with part number 1821TH has been selected as reference for this work, because of its high input analog bandwidth (up to 18 GHz), minimum aperture jitter (50 fs) and a maximum clock frequency equal to 2 GHz. The first studied scenario is based on high resolution ADC with a high sampling frequency to reduce the folded noise effect. With this focus in mind the selected ADC was a 12-bit ADS5400 from Texas Instruments with maximum clock frequency of 1 GHz [5.15]. Using a sampling frequency of almost 1 GHz, it is possible to cover all the dual band applications, as illustrated in Figure 5.15a (Case 1) [5.6], where the meaning of axis x is detailed in Table 5.3. This table defines each dual-band signal scenario as the combination of two different communication standards. Using as reference the typical resolution given by the datasheets, the theoretical SNR for each dual-band scenario was estimated from equations (3.21) and (4.3), taking in account the jitter and the folded noise effects respectively. Another option is to use a higher resolution ADC, like the 14-bit ADS5474 from Texas Instruments (Case 2 in Figure 5.15a). This device was selected because its maximum sampling frequency is 400 MHz. However, as shown in Figure 5.15a, this option is less flexible, because it is not possible to find any sampling frequency lower than 400 MHz for the first three scenarios. In order to improve the SNR without losing flexibility, two steps subsampling approach is proposed, where the sampling frequency of S&H was set at around 2 GHz and the sampling frequency of ADC at around 1 GHz (Case 3 in Figure 5.15a). Therefore, a theoretical 3 dB improvement is achieved from equation (4.6) in respect to Case 1. However, since this first approach is implemented without BP filters, a new folded noise effect will be added from equation (4.3) because a second subsampling process may be necessary. Despite not using BP filters, note that a LP filter with a cutoff frequency equal to fs1/2 144 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [5.4] A. Kwan, S. A. Bassam, F. M. Ghannouchi, “Sub-sampling Technique for Spectrum Sensing in Cognitive Radio,” IEEE Radio and Wireless Symposium (RWS’2012), pp. 347-350, 2012. [5.5] H. Hashemi, A. Hajimiri, “Concurrent multiband low-noise amplifiers-theory, design, and applications,” IEEE Transaction on Microwave Theory and Techniques, vol.50, no.1, pp.288-301, Jan 2002. [5.6] J. G. Oya, A. Kwan, S. A. Bassam, F. Muñoz, and F. M. Ghannouchi, “Optimization of Subsampling Dual Band Receivers Design in a Nonlinear Systems,” IEEE MTT-S International Microwave Symposium Digest (IMS’2012), pp. 1-3, Montreal, QC, Canada, June 2012. [5.7] J. H. Kim, H. Wang, H-J. Kim H-J, J-U. Kim, “Bandpass Sampling Digital Frontend Architecture for Multi-Band Access Cognitive Radio,” IEEE Global Telecommunications Conference (GLOBECOM 2009), pp. 1-6, 2009. [5.8] S. Haykin, “Cognitive Radio: Brain Empowered Wireless Communications”, IEEE Journal on Selected Areas in Communication, j. 48, no. 2, pp. 201-220, 2005. [5.9] ADS5474, 14-Bit 400-MSPS Analog-to-Digital Converter, Texas Instruments. Datasheet. [5.10] ADS5474, ADS5440/44/63/74 EVM, Texas Instruments. User Guide. [5.11] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, K. Kobayashi K, “Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems,” IEEE Transactions on Circuits and Systems I Fundamental Theory Applications, vol. 48, no. 3, pp. 261271, 2001. [5.12] E. McCune, “High-efficiency, Multi-mode, Multi-band Terminal Power Amplifiers,” IEEE Microwave Magazine, vol. 6, no. 1, pp. 4455, 2005. [5.13] F. M. Ghannouchi, O. Hammi, “Behavioral modeling and predistortion,” IEEE Microwave Magazine, vol. 10, no. 7, pp. 52–64, Dec. 2009. [5.14] F. Agnelli et al., “Wireless Multi-Standard Terminals: System Analysis and Design of a Reconfigurable RF Front-End,” IEEE Circuits and Systems Magazine, vol. 6, no.1, pp. 38-59, Jan. 2006. Chapter 5: Subsampling techniques for nonlinear and multi-band applications 145 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS [5.15] ADS5400, 12-Bit 1-GSPS Analog-to-Digital Converter, Texas Instruments. Datasheet. [5.16] E8257D PSG, Microwave Analog Signal Generator, Agilent Technologies. Datasheet. [5.17] ZX60-6013E, Connectorized Amplifier 50 Ω, Minicircuits. Datasheet. [5.18] E8663D PSG, RF Analog Signal Generator, Agilent Technologies. Datasheet. [5.19] SMIQ, Vector Signal Generator, Rohde & Schwarz. Datasheet. 146 Chapter 5: Subsampling techniques for nonlinear and multi-band applications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS CHAPTER 6 CONCLUSIONS AND POSSIBLE FUTURE DIRECTIONS CHAPTER CONTENTS 6.1 Conclusions .......................................................................................................... 148 6.2 Possible future directions ...................................................................................... 149 This chapter presents the main conclusions and contributions of this thesis and describes the possible future directions. 148 Chapter 6: Conclusions and possible future directions SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 6.1 Conclusions This thesis exploits the benefits of the subsampling based systems to be to the RF down-conversion stage in receivers for Software Defined Radio (SDR). There are three distinguishable contributions in this thesis work that come from the data acquisition design for testing wideband multi-standard purposes, the noise performance optimization from multiple clocking techniques, and extension of subsampling techniques to multi-band and non linear environments. All these contributions have been theoretically studied and experimentally validated. Since the SDR objectives can only be obtained with a receiver whose front-end accommodates a wide range of frequency bands and channel bandwidths, subsampling architectures are presented as a feasible alternative to the different possible receiver architectures reviewed in Chapter 1. Moreover, a subsampling scheme has been selected because it leads to extremely flexibility and simplicity, the reduction of the number of components to a minimum being a key when the same receiver has to process different standards. In addition, since the digitization stage will be placed just after the antenna by using subsampling techniques, most of the signal processing will be performed in the digital domain, thus avoiding the limitations of the current ADCs. Therefore, the proposed architecture reduces the number of analog of building blocks, and relaxes the specifications of the ADC, which is the current bottleneck towards a fully digital multi-standard software radio. After describing the subsampling idea in Chapter 2, detailing the main non idealities proper of these techniques (i.e., jitter noise and folded thermal noise), Chapter 3 discusses the usefulness and potential of subsampling technique to design a simple and flexible universal receiver. A data acquisition module for testing wireless receivers based on subsampling has been presented which covers most present wireless communication standards requirements with only one single board. Experimental results of the proposed module show (for a 20 MHz signal bandwidth) an ENOB higher than 8 bits up to 5 GHz center frequency. Another characteristic of the implemented module is its simplicity, with only a few components on a printed-circuit board. These results show that, for testing purposes, the subsampling based receiver is a viable alternative to other typical receiver architectures, with enhanced reconfigurability and programmability. As a second main contribution, the noise performance of the subsampling based receiver has been optimized by using a novel method based on multiple clocking techniques in order to reduce the folded noise effect. An analytical expression for the improvement factor in the SNR with respect to the single-clock solution has been obtained. Finally, a new version of the data acquisition module for testing of wireless receivers has been presented. For the selected frequency plan, with two successive subsampling processes, the ENOB has been shown to improve in approximately 0.5-1 bit. Experimental results show, for a 20 MHz Chapter 6: Conclusions and possible future directions 149 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS signal bandwidth, an ENOB of more than 9 bits up to 2.9 GHz, and more than 8 bits up to 6.5 GHz center frequency. Measurement results show that the design covers the most important wireless standards (i.e., GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX) in terms of tuning frequency and noise performance. As a third main contribution, the subsampling concepts have been extended for multi-band and nonlinear systems, where there is an additional problem about the harmonics and different channel which might be folded in the band of interest. After the challenges and issues on finding the valid subsampling frequencies in multi-band and nonlinear systems have been discussed, an optimized design approach for a concurrent dual band multi-standard subsampling receiver in a nonlinear and / or interfering environment has been presented, proposing a multi-filter architecture along with dual subsampling process. In addition, an efficient algorithm has been developed in order to find the valid sampling frequencies, increasing the flexibility of the receiver and covering the maximum number of dual band applications for different communication standards. As an additional advantage, these conditions used to select the valid sampling frequency can lead to more relaxed RF filter requirements. Experimental results proved the feasibility and the advantages of the proposed architecture, which can be used for different functionalities in a wireless communication transceiver, on both the transmitter and the receiver side. 6.2 Possible future directions Firstly, future works will be intended to integrate all these contributions in a unique data acquisition board for multi-standard and multi-band testing purposes. Therefore, implementing the designed bank of filters between the S&H and the ADC, it will be possible to extend the functionality of the PCB to multi-band and nonlinear environments. Another further objective to improve this thesis work will be the implementation of an autonomous prototype. A FPGA will be included in the board to autonomously select the optimal sampling frequency and the optimal filter bandwidth from the developed algorithms, instead of carrying out these tasks by an external computer. Also, this FPGA will perform the required digital signal processing, potentially increasing the usefulness of including this component. The selected sampling frequency will be used to program a VCO in order to increase the autonomy of the board, avoiding use of an external clock generator. Nevertheless, when the second sampling frequency is not multiple of the first sampling frequency, a second VCO will be necessary, increasing the complexity and the total power consumption. Therefore, other future approach will be to extend the algorithm for dual-band and nonlinear scenario in order to find a new sampling frequency plan based on two multiple frequencies, which reduces the power consumption avoiding a significant noise performance penalty. 150 Chapter 6: Conclusions and possible future directions SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS Moreover, these researches can be associated to other current projects. Besides increasing the autonomy by using a unique data acquisition board, a second main future challenge is to utilize the optimized dual-band receiver within a current project developed by the iRadio Labs, from the University of Calgary. This project includes a subsampling receiver in a feedback loop of a dual-band transmitter for linearization purposes, as described in Chapter 4. Therefore, the focus will be to improve the noise performance in the receiver, avoiding the drawbacks of the previous work (described in section 5.4.2.2), such as the presence of additional spurious due to use an interleaved ADC architecture, or a low analog bandwidth that limits its usefulness for multi-standard applications. In addition, the final objective of this project consists of a whole transmitter design whose promising validation will be implemented by COTS. Using subsampling, the S&H and the ADC implement the feedback loop for linearization, whereas a DAC is used to set the baseband I-Q signals previously to be modulated. A FPGA is connected to both daughter boards, implementing the digital pre-distortion process and the signal generation from the connection with the ADC and the DAC, respectively. The interface between the FGPA and the daughter boards has already implemented, as well as the communication with an envelope modulator employed to increase the efficiency of the power amplifier. On the other hand, an alternative to clock the receiver by using VCOs is utilizing a clock generator board based on direct digital synthesizers (DDSs), which is being currently designed within a project developed by the Electronics Engineering Group, from the University of Seville, and the company AT4 Wireless. Clocking the proposed receiver with this generator can be a feasible alternative when a frequency hopping implementation is required, in order to receive different input signals by rapidly switching the carrier among many wireless communication standards. CHAPTER 7 APPENDIX A: DATA ACQUISITION SYSTEMS BASED ON INTERLEAVING TECHNIQUES CHAPTER CONTENTS 7.1 Theory of operation .............................................................................................. 153 7.1.1 Interleaving idea .............................................................................................. 153 7.1.2 Analysis of time-interleaved ADCs ................................................................. 153 7.2 Time-interleaved ADCs validation ....................................................................... 155 7.2.1 Validation at simulation level .......................................................................... 155 7.2.2 Validation at experimental level ...................................................................... 157 7.3 Calibration techniques .......................................................................................... 160 7.4 Implemented systems............................................................................................ 164 7.5 References ............................................................................................................ 166 The idea of connecting several ADCs in parallel is to maximize the total data acquisition rate. In this appendix these architectures will be introduced, focusing this description on their advantages and inconveniences, such as the 152 Appendix A: Data acquisition systems based on interleaving techniques SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS mismatches errors between the interleaved ADCs, which will need to be compensated. These theoretical concepts will be validated at simulation and experimental levels. Finally, special attention is devoted to the published corrections methods from a bibliographic study detailing the most appropriate calibration techniques in terms of power consumption or digital processing capabilities. Appendix A: Data acquisition systems based on interleaving techniques 153 SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 7.1 Theory of operation 7.1.1 Interleaving idea A time-interleaved ADC operates M parallel ADCs at different sampling times, such as illustrated in Figure 2.15 [7.1]. Ideally, the ith ADC, i = 0, ..., M – 1, samples periodically the input signal at time instants ti, ti+M, ti+2M, with sample rate fs/M, where tm=mTs and Ts=1/fs is the sampling period of the time-interleaved ADC. The final output is created by multiplexing all of the individual ADC outputs in the proper order (e.g. ADC0, ADC1, …, ADCM – 1, ADC0, ADC1, ...). Therefore, the final effect is as if the input signal were sampled once every Ts seconds, i.e., with sample rate fs. Although the data acquisition rate is increased without penalty over other ADC features, these systems present several disadvantages. Firstly, it should be noted that each individual ADC deals with the entire analog input signal, and, therefore, its S&H circuit must be able to preserve the full input signal bandwidth. Secondly, different spurs are caused by the mismatches between ADCs, its location in the spectrum being predicted in the next section. 7.1.2 Analysis of time-interleaved ADCs Let x(t) be an analog signal with Fourier transform Xa(ω). Consider that the time-interleaved ADC outputs the sequence: ),...(),(),...,(),...,(),(),(1210 MMm txtxtxtxtxtx (7.1) Define the discrete-time Fourier transform by10: )exp()()( kk tjtxX (7.2) Ideally, the samples are spaced Ts seconds apart. Then, it can be shown that: )2()( sas fkXfX (7.3) which is the well-known spectrum representation of a uniformly sampled signal. It results in a periodic spectrum with a period equal to the sampling rate [7.2]. 10 In the literature, it is a common notational practice to replace ωtk with a single variable ω´=ωtk, called normalized frequency. Since ω represents ordinary frequency (radians per second), ω´ is expressed in units of radians (per sample). Recall also that by sampling the discrete-time Fourier transform, we obtain the discrete Fourier transform (DFT) [7.1]. B. Papari, D. Asemani, A. Khakpour, “A Wide-Band Time-Interleaved A/D Converter For Cognitive Radio Application With Adaptive Offset Correction,” 2011 Wireless Advanced, pp. 144-148, 2011. C. R. Parkey, M. T. Hunter, D. B. Chester, W. B. Mikkael, “Simulink Modeling of Analog to Digital Converters for Post Conversion Correction Development and evaluation,” IEEE 54th International Midwest Symposium on Circuits and Systems (MWCAS 2011), pp. 1-4, 2011. H. Pekau, J. W. Haslett, “A 0.18µm CMOS 2.1GHz Sub-sampling Receiver Front end with Fully Integrated Secondand Fourth-Order Q-Enhanced Filters,” IEEE International Symposium on Circuits and Systems, pp.3103-3106, New York, July 2007. J. M. D. Pereira, P. M. B. S. Girao, A. M. C. Serra, “An FFT-Based Method to Evaluate and Compensate Gain and Offset Errors of Interleaved ADC Systems,” IEEE Transactions on Instrumentation and Measurement, Vol. 53, no. 2, pp. 423-430, April 2004. A. Petraglia and S.K. Mitra, “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer,” IEEE Transactions on Instrumentation and Measurement, Vol. 40, no. 5, pp. 831-835, Oct. 1991. K. Poulton et al., “A 20 GS/s 8b ADC with a 1 MB memory in 0.18 µm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Vol. 1, pp. 318–496, 2003. M. B. Romdhane, P. Loumeau, “Analog to Digital Conversion specifications for Ultra Wide Band reception,” Proceedings of the Fourth IEEE International Symposium on signal Processing and Information Technology, pp. 157-160, 2004. H. H. Slim, P. Russer, “Digital Automatic Calibration Method for a Time-Interleaved ADCs System used in Time-Domain EMI Measurement Receiver,” IEEE International Symposium Electromagnetic Compatibility (EMC 2011), pp. 476-479, 2011. Y. R. Sun, “Generalized Bandpass Sampling Receivers for Software Radio,” Doctoral Dissertation, Royal Institute of Technology, School of Information and Communication Technology (ICT), Stockholm, Sweden, 2006. F. Svelto, M. B. Vahidfar and M. Brandolini, “Reconfigurable Si RF Receiver FrontEnds for Multistandard Radios,” European Conference on Wireless Technology (EuWiT 2008), pp. 33-36, 2008. M. Tamba, A. Shimizu, H. Munakata, T. Komuro, “A Method to Improve SFDR with Random Interleaved Sampling Method,” International Test Conference 2001, pp. 512520, 2001. R. G. Vaughan, N. L. Scott and D. R. White “The Theory of BandpassSmpling,” IEEE Transactions on Signal Processing, Vol. 39, pp. 1973-1984, Sep. 1991. Y. Vanderperren, W. Dehaene, G. Leus, “A Flexible Low Power Subsampling UWB Receiver Based on Line Spectrum Estimation Methods,” IEEE International Conference on Communications, pp. 4694-4699, 2006. N. Vun, A. B. Premkumar, “ADC Systems for SDR Digital Front-End,” Proceedings of the Ninth International Symposium on Consumer Electronics (ISCE 2005), pp. 359-363, 2005. 258 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 9.5.3 Conference communications “High Frequency Analog-to-Digital Conversion Based on Subsampling”, XXIV Conference of Design of Circuits and Integrated Systems (DCIS’2009), 2009. High frequency Analog-to-Digital Conversion based on subsampling José Ramón García Oya#, Antonio Jurado Díez*, Fernando Muñoz Chavero#, Antonio Torralba Silgado# #Departamento de Ingeniería Electrónica, Universidad de Sevilla c/ Camino de los Descubrimientos s/n 41092 Sevilla, Spain 1[email protected] 3[email protected] 4[email protected] *AT4 wireless c/ Severo Ochoa 2 29590, Málaga, Spain 2[email protected] Abstract— The focus of this work is the implementation of a Analog-to-Digital Converter System using techniques based on subsampling. Its main objective is to improve the features of a receiver used for wideband communications reducing the number of elements of the system with a higher flexibility and resolution. This proposed system is based on commercial devices, mainly a Low Jitter and Wideband Sample&Hold and a High Resolution Intermediate-frequency Analog-to-Digital Converter. Keywords— Analog-to-Digital Converter, ENOB, Jitter, Sample&Hold, Software Defined Radio, SNDR, Thermal Noise I. INTRODUCTION In general, the analog building blocks determine the sensitivity and selectivity of a receiver. The Analog-to-Digital Converter (ADC) is becoming an extremely important block of the receiver architecture, because the place of the ADC into the receiver architecture marks which functions are implemented with analog circuitry and what functionality is done in the digital signal processor. Nowadays there is a trend of increasing the resolution and speed of the ADC of a receiver so that it is possible to place it closer the antenna. Thus the analog front end is greatly simplified and the flexibility of the receiver is improved. The current state of the art of high-frequency ADCs does not allow the use of the ADC directly in the RF domain to get the paradigm of the Software Defined Radio (SDR). However, many research projects focus on finding new solutions towards the SDR, where all the analog functionalities (e.g. mixers, filters, amplifiers, modulators/demodulators) are performed in the digital domain. Nowadays, with a conventional Analog-to-Digital conversion on the headerreceiver, only 7-8 bits are obtained with 3 GS/s Analog-toDigital Converters. The basic specifications of the implemented system in this paper are illustrated with the Table I: TABLE I SPECIFICATIONS OF THE IMPLEMENTED SYSTEM Analog Input Frequency DC-3 GHz Signal Bandwidth 20 MHz Sampling Frequency 400-500 MHz Resolution 9 bits In this paper an architecture based on subsampling is presented in order to improve the flexibility of a communication receiver, reducing the number of analog components. Using techniques based on subsampling, like those shown in this paper, we implement an Analog-to-Digital Conversion System with a resolution higher than 8 bits and with a maximum of 3,1 GHz of center frequency of the RF signals and close to 9 bits with a maximum center frequency of 2 GHz input approximately. This paper is organized as follows: section II introduces subsampling and theoretical concepts on how to obtain the optimal subsampling frequency and to evaluate effect of the main non-idealities that will limit the implemented system. These non-idealities help us to justify the choice of components in section III. In section IV, experimental issues present the attained results about noise and distortion. The paper finishes with conclusions in section V. II. THEORETICAL STUDIES ON SUBSAMPLING A. Concept of subsampling and optimal frequency choice In this section we study the way to calculate optimal subsampling frequency, using the signal bandwidth (BW) and its carrier frequency (fc), in order to avoid aliasing and to maintain the copy generated between -fs/2 and fs/2 and the replicas as far as possible to the desired signal [1-6]. Hereafter, we will use the following notations (see Fig.1):  fs: subsampling frequency  BW: signal bandwidth  fc: carrier frequency  B: fc+BW/2 f fc BW fs fs Fig. 1 Subsampling concept (m=3) The minimal sampling frequency is established by the Nyquist Theorem, fs > 2B. However, we can avoid aliasing with less fs when expression (1) is true: 1 22     m BWf f m BWfc s c (1) m is an entire number whose meaning is the number of copies of the original signal that appears in the range [0, fcBW/2]. The maximum number of copies needed to avoid aliasing is calculated by the expression (2): ) 2 ( max BW BW f floorm c  (2) floor(x) is the entire number nearest to x y less than x. The last expression establishes the limits of fs, the optimal frequency in this range. Concretely, the optimal value to avoid aliasing is one that produces a copy on fs/4. This frequency equals: odd c sm f f4  (3) modd is an entire odd number more than 1:  with modd = 5,9,13, … there is not spectral inversion  with modd = 3,7,11, … there is spectral inversion B. Main non-idealities A general scheme of the implemented receiver is shown in the Figure 2. Its main advantage is its simplicity, eliminating a large amount of components in the traditional heterodyne structure. However, the specifications of the Sample&Hold are much more restrictive than in a traditional receiver. This device will be the most critical in our system because it processes high frequency signals. Fig. 2 Schematic of the receiver implemented The main non-idealities produced in Sample&Hold are the following: 1) Jitter: Ideally, the input signal is sampled in equal frequency fs intervals. Nevertheless, these intervals are different due to jitter [7-9]. This jitter produces an increment of the total noise, thus limiting the effective number of bits (ENOB). Jitter is produced by two different sources: the phase noise associated to the oscillator and the aperture jitter of the Sample&Hold. At a first approximation we can consider these two sources of jitter as non-correlated Gaussian stochastic processes. Aperture jitter of a Sample&Hold depends on the changes of the threshold voltage according to the input voltage so that its feature is dependent on the signal. This section shows how jitter affects Signal to Noise Distortion Ratio (SNDR) in the Sample&Hold output. The focus is the establishment of the maximum allowed jitter standard deviation depending on input frequency and the resolution specifications. When the input is a sinusoidal signal like   ( ) sin 2 in y t A f t   , SNDR is determined by the expression (4):           caseother e f f N A SNDR in f in in _: )1(2 1 12: 4 1 2 222 2 222 2         (4) Where N  is the average power noise and   is the jitter standard deviation. To deduce the last expression, the spectral density was integrated between 0 and fs/2. To obtain more realistic values of the effect fot he jitter we performed simulations (by MATLAB® Software) while considering only the noise in the signal bandwidth is integrated (20 MHz) and the jitter presented by a stochastic process with an average of zero and standard deviation   . The equation (3) has been used to choose the optimal subsampling frequency s f . These simulations verify how the allowed jitter is lower for higher input frequencies. Figure 3 illustrates these conclusions to the following cases:  fc=4GHz, fs=484.84MHz  fc=2GHz, fs=470.59MHz  fc=1GHz, fs=444.44MHz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10-12 40 45 50 55 60 65 70 75 80 Desviación típica de jitter (seg) SNDR (dB) fc=2GHz, fs=470.59MHz, BW=20MHz fc=1GHz, fs=444.44MHz, BW=20MHz fc=4GHz, fs=484MHz, BW=20MHz Fig. 3 Jitter effect depending on input frequency 2) Overlapped Thermal Noise: a typical Sample&Hold produces kT/C noise. To simplify the noise analysis we consider a sampling model as it is illustrated in Figure 4 [10]. This scheme consists of an input band pass signal ( in V ), with an associated noise ( in N ), which is filtered and later applied to a Sample&Hold modelled by a switch and capacitor. Due to the multiple overlapping produced by subsampling, many parts of the signal spectrum will be inside of the band of interest. 4kTRon Ron Cs fs Vin+Nin NBW=Bneq Zo<<Ron Vout (nTs) + Nout Fig. 4 Scheme of noise analysis The equivalent switch resistance has a white noise power spectral equal to ON kTR4 and it is filtered by the transfer function: SON CfR fH  21 1 )(   (5) The result is a filtered white noise with a power equal to S C kT , whose value is independent of the resistance and subsampling frequency. We assume: SON sCR f  2 1  (6) Then, due to the subsampling process, we can approximate all noise power overlapped between 0 and 2 s f , as illustrated in Figure 5. fs/2 fs 2fs 3fs 4fs 12 1 log),( son out CRj fN  Fig. 5 Subsampling effect over the Sample&Noise Although the total noise power is not dependent on subsampling frequency, noise floor reduces if this frequency grows. Concretely, noise floor is reduced 3 dB if subsampling frequency is doubled. Thus, it is convenient to choose a maximum subsampling frequency to distribute noise floor throughout the entire Nyquist band. 3) Other considerations in choosing Sample&Hold:  Its bandwidth should be maximized in order to not filter GHz signals.  Although it has a high bandwidth, the Sample&Hold should be able to sample frequencies close to MHz, due to these values are the maximum sample frequencies for high resolution commercial A/D converters.  Its output ENOB can be limited by linearity, so we should study its THD and SFDR. III. USED COMPONENTS The theoretical study that was briefly explained in section II allows fixing the specifications of the main building blocks of the system, i.e., the Sample&Hold and the ADC. After a study on commercial components, we decided to use an external Sample&Hold for the A/D Converter since an internal Sample&Hold bandwidth is limited to 3 GHz approximately with a resolution around 7-8 bits. However, when using an external Sample&Hold, it is possible to obtain a higher resolution for a wider bandwidth. The chosen Sample&Hold is the Inphi 1821 TH [11], with the following features:  Wider bandwidth (18 GHz).  Wider frequency range (0-6 GHz) for 10-bit linearity.  Thermal noise is not an obstacle (SNR>60 dB)  Low phase noise, with SNR > 60 dB in the range 0-3,2 GHz.  Capability to sample at the interested frequency (around 500 MS/s) This requirement (500 MS/s) is given by the maximum sampling frequency for commercial 10-bit A/D converters, since using a maximum sampling frequency is convenient in order to reduce the overlapping noise effects. Concretely, the A/D converter chosen is E2V AT84AS001 [12]. IV. EXPERIMENTAL RESULTS The receiver system implemented is illustrated in Figure 6. In this system the GHz input signal is generated and converted to differential to be sampled by the Sampled&Hold. By the other side, a unique clock signal is generated to the Sample&Hold and the ADC that is converted to differential signal too, with baluns at lower frequencies. We used the evaluation boards of these devices connected by cables. Also DC blocks and bias tee are used to block the DC signal and to adapt the impedances. This system can be used to illustrate some subsampling effects studied in the previous sections, like the overlapping thermal noise within band signal, which is dependent on the subsampling frequency. This effect is illustrated in Figure 7, where we use the optimal frequency so that third order harmonics are overlapped with the signal (as it is deduced from the theoretical studies), and this way we only measure the noise effect (SNR) integrated in the signal bandwidth, because the second order harmonics will be the furthest possible to the desired signal. Signal amplitude is equal to -1 dBm and noise is integrated in 20 MHz. Signal Generator SMIQ Rohde & Schwarz Balun ZAPDJ-2 Cable N-SMA DC-Block DC-Block Cable SMA-SMA Cable SMA-SMA S&H 1821TH Inphi Clock Generator E8257D Agilent Adap. SM-SF Balun ZFSCJ-2-4 Cable SMA-SMA Balun ZFSCJ-1-2 Balun ZFSCJ-1-2 Cable SMA-SMA Cable SMA-SMA DC-Block DC-Block IN+ INCLK+ CLKADC AT84AS001 e2v Cable SMA-SMA Cable SMA-SMA DC-Block DC-Block Cable SMA-SMA Cable SMA-SMA CLK+ CLKBias-Tee Bias-Tee Filtro 250 Filtro 250 Adap. SM-SF Adap. SM-SF Cable SMA-SMA Cable SMA-SMA Cable SMA-SMA Cable SMA-SMA OUT+ OUTOUT D11-D0 12 Logic Analyzer 16760-A Agilent Fig. 6 A/D converter system implemented Fig. 7 Measurement of the effect of overlapping noise (ENOB vs. the different Subsampling Optimal Frequencies) Another interesting measurement is the influence of the jitter, which is more critical at higher frequencies and hence the main limitation in the implemented system. This effect is illustratedin Figure 8, using the optimal subsampling frequency immediately less than 500 MHz. Fig. 8 Jitter effect measurement (ENOB vs. Carrier frequency) The total resolution of this system is illustrated in Figure 9, using the optimal subsampling frequency immediately lower than 500 Mhz. The final result is an A/D converter system that converts signals up to 3,1 GHz with more than 8 effective bits. 200 250 300 350 400 450 500 0 1 2 3 4 5 6 7 8 9 fs (MHz) enob 1000 1500 2000 2500 3000 3500 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 fc (MHz) enob Fig. 9 ENOB of the implemented system vs. Caarrier Frequency As an example, the output spectrum is illustrated in Figure 10, for a 3 GHz input frequency and a 480,2 MHz optimal subsampling frequency. 103104105106107108109 -20 0 20 40 60 80 100 120 Hz dBm BW=20MHz Fig. 10 Output Spectrum to a 3 GHz Analog Input Signal V. CONCLUSIONS In the present document we have discussed the current limitations of the resolution of A/D converters, which is an obstacle for the use of the digital signal processor directly in RF. In this paper an Analog-to-Digital Converter System using techniques based on subsampling has been presented. We have introduced the subsampling concept and its main non-idealities, like jitter or overlapping thermal noise. The theoretical study has been used to design a system that demonstrates experimentally that the performance of subsampling based system. Experimental features of the proposed receiver system (for signals with a 20 MHz bandwidth) are:  ENOB is around 9 bits to 1-2 GHz input frequency.  ENOB is more than 8 bits up to 3,1 GHz input frequency. Therefore, the experimental results place the subsampling based receiver as an alternative to the typical receiver architectures with an enhanced reconfigurability and programmability. ACKNOWLEDGMENTS This work has been developed within the scope of the TelMAX Project and is partially funded by CDTI –Centro para el Desarrollo Tecnológico e Industrial-, of the Spanish Ministry of Science and Innovation, under the INGENIO 2010 Program / CENIT call. REFERENCES [1] R. G. Lyons, Understanding Digital Signal Processing, United States: Prentice Hall, 2001. [2] M. A. I. Mostafa, S. Embabi, M. C. Fernando and W. C. Chan, Ch. Gore JR, ―Subsampling RF Receiver‖ U.S. Patent 01811614, Dec. 5, 2002. [3] R. G. Vaughan, N. L. Scott and D. R. White ―The Theory of Bandpass Smpling‖ IEEE Transactions on Signal Processing., vol. 39, pp. 19731984, Sep. 1991. [4] Y. R. Sun, ―Generalized Bandpass Sampling Receivers for Software Radio‖ Doctoral Dissertation, Royal Institute of Technology, School of Information and Communication Technology (ICT), Stockholm, Sweden, 2006 [5] M. Negreiros, E. Schuler, L. Carro and A. A. Susin, ―Testing RF Signal Paths Using Spectral Analysis and Subsampling‖ in Proc. SBCCI, 2003. [6] Y. Vanderperren, W. Dehaene and G. Leus ―A Flexible Low Power Subsampling UWB Receiver Based on Line Spectrum Estimation Methods‖ Communications, 2006 IEEE International Conference on Volume 10, Page(s):4694 – 4699, June 2006 [7] J. Catt, ―Clocking High-Speed A/D Converter‖, Maxim Application Note 1558, Jan. 2007. [8] ―Design a Low-Jitter Clock for High-Speed Data converters‖, National Semiconductor Application Note 1558, Nov. 2001. [9] R. Stephens, ―The Rules of Jitter Analysis‖, Agilent Technologies Application Note. [10] S. Karvonen, ―Charge-Domain Sampling of High Frequency Signals with Embedded Filtering‖ thesis, Faculty of Technology, Department of Electrical and Information Engineering, University of Oulu, Finland, Jan. 2006. [11] ―1821TH 18 GHz Bandwidth 2GS/s THA data sheet‖, Inphi, Westlake Village, California, United States. [12] ―12-bit 500 Msps ADC AT84AS001‖, E2V, Saint Egrève Cedex, France. 500 1000 1500 2000 2500 3000 3500 0 1 2 3 4 5 6 7 8 9 10 Fin (MHz) enob 264 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS “Multiple Clocking High Analog-to-Digital Conversion Based on Subsampling”, XXVI Conference of Design of Circuits and Integrated Systems (DCIS’2011), 2011. 405 Multiple Clocking High Analog-to-Digital Conversion based on Subsampling José Ramón García Oya1, Antonio Jurado Díez2, Fernando Muñoz Chavero1, Antonio Torralba Silgado1, Fernando J. Márquez Lasso 1, Enrique López-Morillo 1 1 Departamento de Ingeniería Electrónica, Universidad de Sevilla c/ Camino de los Descubrimientos s/n 41092 Sevilla, Spain [email protected] | [email protected] | torr[email protected] | fernando.mar[email protected] | [email protected] 2 AT4 wireless, c/ Severo Ochoa 2 29590, Málaga, Spain [email protected] 0XOWLSOH&ORFNLQJ+LJK$QDORJWR'LJLWDO&RQYHUVLRQ EDVHGRQ6XEVDPSOLQJ -RVp5DPyQ*DUFtD2\D$QWRQLR-XUDGR'tH])HUQDQGR0XxR]&KDYHUR$QWRQLR7RUUDOED6LOJDGR)HUQDQGR- 0iUTXH]/DVVR(QULTXH/ySH]0RULOOR 'HSDUWDPHQWRGH,QJHQLHUtD(OHFWUyQLFD8QLYHUVLGDGGH6HYLOOD F&DPLQRGHORV'HVFXEULPLHQWRVVQ6HYLOOD6SDLQ R\D#JW H HVLXVHVIPXQR]#JW H HVLXVHVWRUUDOED#XVHVIHUQDQGR PD UTXH]#JL H HVLXVHV HQULTXH ORSH]#JL H HVLXVHV  $7ZLUHOHVV F6HYHUR2FKRD0iODJD6SDLQ DM GL H]#DW ZLUHO HVV FRP  $EVWUDFW²7KLV SDSHU SUHVHQWVD'DWD $FTXLVLWLRQ 6\VWHPIRU WHVWLQJ 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Power spectrum at the input (top) and the output (bottom) of a nonlinear system The universal formula to find valid sampling frequencies in the presence of harmonics is given by [3]: sksk fnifjffnif )1( 111 ++<≤+ (4) Being if1 and jf1 two harmonics of f1 and nk =floor((jf1-if1)/fs). An algorithm to find the range of valid subsampling frequencies for multiband systems is presented in [4]. From the general equations obtained in [4], and considering the particular case of dual band system, the maximum replica order of the lower band (n1) meets the following equation: ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ −+− ≤ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = ))()((2 2211 11 1 LULU L s L ffff f floor f f floorn (5) Where fL1 and fU1 are the low and the high limits of the lower band and fL2 and fU2 are the low and the high limits of the upper band. Knowing f2= R1f1, replica orders of the upper band (n1) meet the following constraint: )()( 111211 RnRfloornnRfloor +≤≤ (6) The eight possible ranges for dual band applications are listed in [4]. Thus, the final sampling ranges will be given the following expression: hmdcmdimddb FFFFF ∩∩∩= (7) Where F is the intersection of all the valid ranges calculated from (4) and (5), Fdb, Fimd, Fcmd and Fhmd are the valid sampling frequency sets for the fundamental signals, intermodulation, cross modulation and harmonic distortion, respectively. In order to find F an algorithm has been developed and written in MATLAB script. This algorithm calculates these ranges and the location of the replicas where the input parameters are the fundamental frequencies, the number of harmonics and the signal bandwidth. As an example, Table I shows the three first valid ranges immediately lower than 2 GHz for the fundamentals signals at 1.82 and 2.4 GHz, considering five harmonics and a signal bandwidth equal to 25 MHz. The subsampled spectrum is illustrated in Fig. 2 for a sampling frequency equal to 2 GHz, showing that there is no overlapping between signals. TABLE I VALID SAMPLING FREQUENCIES BELOW 2 GHZ Lower Frequency Bound (MHz) Upper Frequency Bound (MHz) 1995 2000 1837.5 1978.33 1801.67 1802.5 0100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) f1 - 1820.00 MHz @ 180.00 MHz f2 - 2400.00 MHz @ 400.00 MHz (-1f1 + 1f2) - 580.00 MHz @ 580.00 MHz (3f1 + -2f2) - 660.00 MHz @ 660.00 MHz (-2f1 + 2f2) - 1160.00 MHz @ 840.00 MHz (2f1 + -1f2) - 1240.00 MHz @ 760.00 MHz (-1f1 + 2f2) - 2980.00 MHz @ 980.00 MHz (3f1 + -1f2) - 3060.00 MHz @ 940.00 MHz (-2f1 + 3f2) - 3560.00 MHz @ 440.00 MHz (2f1 + 0f2) - 3640.00 MHz @ 360.00 MHz Fig. 2. Subsampled spectrum for 1.82 and 2.4 GHz input frequency IV. OPTIMIZATION OF THE RECEIVER ARCHITECTURE In order to optimize the proposed receiver, seven input frequencies have been selected to study the selective combinations for different dual band applications. These chosen standards are WCDMA (V) at 880 MHz, GSM-DCS at 1.82 GHz, WCDMA (I) at 2.12 GHz, Bluetooth at 2.4 GHz, WiMAX at 3.5 and 5.8 GHz, and 802.11a at 5.2 GHz. Since the main focus is to cover the maximum number of standards, it is mandatory to use a S&H before the ADC in order to have enough analog bandwidth. The S&H from Inphi with part number 1821TH has been selected for this work, because of its high input analog bandwidth (up to 18 GHz), minimum aperture jitter (50 fs) and a maximum clock frequency equal to 2 GHz. The first studied scenario is based on high resolution ADC with a high sampling frequency to reduce the folded noise effect. With this focus in mind the selected ADC was a 12-bit ADS5400 from Texas Instruments with maximum clock frequency of 1 GHz. Using a sampling frequency of almost 1 GHz, it is possible to cover all the dual band applications, as illustrated in Fig. 3 (Case 1), where the meaning of axis x is illustrated in Table II. Using as reference a typical SNR of the ADC equal to 58 dB, the theoretical SNR for each dual band application was calculated from (2) and (3). Another option is to use a higher resolution ADC, like the 14-bit ADS5474 from Texas Instruments (Case 2 in Fig. 3). This device was selected because its maximum sampling frequency is 400 MHz and, therefore, the folded noise would only be around 4 dB higher than Case 1. TABLE II DUAL BAND APPLICATIONS AND AXIS X CORRESPONDENCE X axis 1 2 3 4 5 6 Input Freq. (GHz) 0.881.82 0.882.12 0.882.4 0.883.5 0.885.2 0.885.8 X axis 7 8 9 10 11 12 Input Freq. (GHz) 1.82 -2.12 1.822.4 0.883.5 1.825.2 1.825.8 2.122.4 2 4 6 8 10 12 40 45 50 55 60 65 SNR (dB) Case 1: @ 1GHz Case 2: @ 400 MHz Case 3: @ 2GHz 1GHz Case 4: @ 2GHz 400MHz Fig. 3. Expected SNR for single and multiple clock architectures However, as shown in Fig. 3, this option is less flexible, because it is not possible to find any sampling frequency lower than 400 MHz for the first three scenarios. In order to improve the SNR without losing flexibility, two steps subsampling approach is proposed, where the sampling frequency of S&H was set at around 2 GHz and the sampling frequency of ADC at around 1 GHz (Case 3 in Fig. 3). Although this architecture improves the SNR by approximately 3 dB from (3) in respect to Case 1, it could be necessary to implement a second subsampling process and, therefore, a new folded noise effect will be added. The last option is to use a multiple clock architecture employing the ADS5474 (Case 4 in Fig. 3) and a first sampling frequency around 2 GHz. Theoretically the SNR is improved around 3 dB in respect to Case 3. In this case, due to the second subsampling process, folded noise effects must be added as well. For the rest of combinations of frequencies the curves present the same tendency, being possible to cover all the scenarios. However, since cases 2 and 4 present the best results about SNR the next step will be to cover all the dual band applications for these cases. The proposed solution is to use a bank of band-pass filters between the S&H and the ADC. This solution will be applied to Case 4, because it has more flexible architecture, with a higher number of available valid ranges. Using this solution, some harmonics will be removed and the flexibility of the receiver will be increased. The solution is based on two filters, whose band-pass ranges are [0-400] and [400-800] MHz. The maximum sampling frequency was selected in order to have both fundamental replicas in each range. The selected filter corresponds to the higher of these two frequencies (Case 5 in Fig. 4). Another solution is to fix a unique BP filter for all the applications (Case 6 and 7 in Fig. 4). In these cases it is possible to cover almost all the standards with only one of these filters, without considerably reducing the resolution. Although in order to maximize the flexibility and the SNR, the optimal architecture is like the one illustrated in Fig. 5, for a more concrete application or more relaxed SNR specifications a single BP filter could be used in order to reduce the complexity of the system. 0 2 4 6 8 10 12 48 50 52 54 56 58 60 62 64 66 SNR (dB) Case 5: envelope of Cases 6 and 7 Case 6: filter in [0-400] MHz Case 7: filter in [400-800] MHz Case 4: @ 2 GHz & 400MHz without filters Case 2: @ 400MHz without filters Fig. 4. Expected SNR for different architectures based on BP filters Fig. 5. Optimized architecture based on multiple clock and BP filters V. CONCLUSION In this paper an optimization for a dual band multi-standard receiver based on subsampling in a non linear environment has been presented. Subsampling techniques have been selected due to the simplicity that these systems present in comparison to traditional receivers. However, receivers based on subsampling have additional sources of noise whose minimization has been the main focus of this work from the study of different architectures. Moreover, dual band systems in nonlinear scenarios have an additional problem because of the overlapping of harmonics. An efficient algorithm has been developed in order to find the valid sampling frequencies, increasing the flexibility of the receiver and covering the maximum number of dual band applications for different communication standards. REFERENCES [1] R. Vaughan, N. Scott, and D. White, “The Theory of Bandpass Sampling,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 1973-1984, September 1991. [2] J. Mitola, “The Software Radio Architecture,” IEEE Communications Magazine, vol. 33, no. 5, pp. 26-38, May 1995. [3] C. H. Tseng, “A Universal Formula for the Complete Bandpass Sampling Requirements of Non Linear Systems,” IEEE Transactions on Signal Processing, vol. 57, no. 10, pp. 38693878, October 2009. [4] C. H. Tseng, and S. C. Chou, “Direct Downconversion of Multiband RF Signals Using Bandpass Sampling,” IEEE Transactions on Wireless Communications, vol. 5, no. 1, pp. 7276, January 2009. [5] M. B. Dadi, and R. Bouallegue, “On the RF Subsampling Continuous-Time ΣΔ Downconversion Stage for Multistandard Receivers,” International Conference on Computer Engineering and Technology (ICCET), vol. 6, pp. 167-171, June 2010. 274 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS 9.5.4 Publications partially related with this thesis “An 8-bit 19 MS/s low-power 0.35 µm CMOS pipelined ADC for DVB-H”, Integration, the VLSI Journal, 2012 An 8-bit 19 MS/s low-power 0.35 mm CMOS pipelined ADC for DVB-H B. Palomo n , F. Mun ˜oz, R.G. Carvajal, J.R. Garcia, F. Marquez Department of Electronic Engineering, University of Seville, Spain article info Article history: Received 6 May 2011 Received in revised form 25 October 2011 Accepted 26 October 2011 Available online 4 November 2011 Keywords: Pipelined ADC CMOS analog integrated circuits Low power Low voltage Opamp-sharing abstract This paper proposes an 8b 19 MHz CMOS pipelined analog-to-digital converter (ADC) for DVB-H. In order to reduce the power consumption a combination of techniques has been used, such as op-amp sharing, low-power amplifiers with gain boosting and an aggressive capacitor scaling. The prototype ADC fabricated in 0.35 mm CMOS demonstrates a maximum differential nonlinearity (DNL) of 0.63 least significant bit (LSB) and a maximum integral nonlinearity (INL) of 0.58 LSB with a peak signal-to-noiseand-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 42.76 and 51.57 dB at 19 MHz. The ADC with an active area of 4.78 mm 2 consumes less than 4 mW at the mentioned sampling frequency. &2011 Elsevier B.V. All rights reserved. 1. Introduction During the last few years much effort has been devoted towards the reduction of the supply power of mixed signal CMOS systems. This is primarily due to the increasing importance of battery-powered electronics, and the continued down-scaling of device sizes. Pipelining has been accepted as one of the best approaches to implement high-speed medium-to-high resolution analog-to-digital converters with minimum power consumption. Digital video broadcasting (DVB) system becomes very attractive for applications in wireless mobile communication devices, such as laptop computers, mobile phone and vehicles [1]. Recently, digital video broadcasting-handheld (DVB-H) has made it possible to deliver broadcast television or other multimedia services to a mobile or handheld device [2] The block diagram of a DVB analog front-end is shown in Fig. 1. The tuner selects the channel converting the OFDM RF signal to a first intermediate frequency around 35 MHz after which it is bandpass filtered by a SAW-filter stage. The SAW filter is followed by a controllable gain amplifier (AGC) in order to adapt the signal level. Finally the resulting signal is converted into a digital signal using an ADC. The proposed receiver implements a subsampling technique as this is the most efficient solution from a power consumption point of view. This technique performs, at the same time, the mixing and sampling process, taking advantage of the band folding inherent to the sampling process. For an intermediate frequency value of 34 MHz and the maximum signal bandwidth defined in the DVB standard (8 MHz), the optimum value for the sampling frequency is next to 19 MHz. Attending to the Mobile and Portable DVB-T Radio Access Interface (MBRAI) from EICTA, the SNR for the demodulation process should be 27 dB in the worst case. An 8 bit ADC achieves the specification, including a security margin in order to anticipate interfering components influence. This paper is organized as follows: the pipelined ADC 1.5-bit per stage architecture is shown in Section 2.Section 3 enumerates and details the low power techniques applied to the ADC in order to achieve such a low consumption. Section 4 describes the circuit implementation and the measurement results. The paper is concluded in Section 5. 2. ADC Architecture A 1.5-bit-per-stage architecture has been used in the pipelined ADC because it shows both the lower power consumption and smallest area compared with architectures based on higher resolution stages. The power efficiency of the 1.5 bit configuration [3–5] rely on that the amplifiers operate at a low closed-loop gain leading to a best settling time for minimum power consumption. A block diagram of the pipeline 1.5-bit/stage architecture is shown in Fig. 2. It consists of a cascade of seven stages. Each stage resolves two bits with a sub-ADC, subtracts the converted value, which only can take values V ref ,V ref or 0 (where V ref is differential reference voltage), from its inputs, and amplifies the Contents lists available at SciVerse ScienceDirect journal homepage: www.elsevier.com/locate/vlsi INTEGRATION, the VLSI journal 0167-9260/$ - see front matter &2011 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2011.10.003 n Corresponding author. Tel.: þ34 954487472; fax: þ34 954487373. E-mail addresses: [email protected] (B. Palomo), [email protected] (F. Mun ˜oz), [email protected] (R.G. Carvajal), [email protected] (J.R. Garcia), [email protected] (F. Marquez). INTEGRATION, the VLSI journal 45 (2012) 222–227 276 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS “Compact low-power implementation for continuous-time ΣΔ modulators”, Integration, the VLSI Journal, 2012. Compact low-power implementation for continuous-time SD modulators E. Lo ´pez-Morillo a , F. Mun ˜oz a, n , A. Torralba a ,F.Ma ´rquez a , I. Rebollo b , J.R. Garcı ´a-Oya a a Electronic Engineering Department, Escuela Superior de Ingenieros, University of Sevilla, Camino de los Descubrimientos s/n, 41092 Sevilla, Spain b Farsens S.L., Parque Tecnolo ´gico de San Sebastia ´n, Paseo Mikeletegi 54, Planta 0—Oficina 1, 20009 San Sebastia ´n, Spain article info Article history: Received 11 April 2012 Received in revised form 27 September 2012 Accepted 2 October 2012 Keywords: Analog-digital conversion Sigma-delta modulation Low power abstract This paper presents a low-area continuous time (CT) sigma–delta ( SD ) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT SD modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25 kHz signal bandwidth with 7 mW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35 mW. A Figure Of Merit (FOM) of 0.267 pJ/state has been achieved with a total area consumption (without pads) of 110 mm125 mm in a 0.35 mm CMOS technology. &2012 Elsevier B.V. All rights reserved. 1. Introduction RFID (Radio Frequency Identification) systems have been traditionally used for identification and tracking applications, replacing the classic barcodes in several applications such as supply chain management, inventory control in warehousing, airport baggage control and manufacturing. The RFID system is made up of two main blocks called transponder (tag), normally embedded in a label, and the reader. RFID tags can either be passive or active. An active tag takes the energy from a battery, so that it can transmits longer distances and uses more sophisticated signal processing. A passive tag scavenges the energy from the electromagnetic field emitted by the reader. As it does not need any battery it can be smaller and cheaper than an active tag and with unlimited lifetime. Interest for the passive applications is growing due to the high fabrication and maintenance costs of active tags. Combining sensors with passive RFID tags opens the way for new applications of RFID in consumer electronics, automotive, medicine and healthcare. As the passive RFID sensor nodes are powered by energy scavenging, ultra-low power consumption and robustness against process variation and changes in the supply voltage are essential requirements. In addition, as typical in mass production applications, low area consumption is crucial in order to decrease the fabrication cost. In the design of passive RFID tags with sensing capability, most of the reported works are focused on antenna and RF front-end design. However, much effort is still needed on the sensor interface, in which the ADC (Analog-to-Digital Converter) is a crucial component. The design of ADCs for passive RFID systems is a current challenge for the IC design research community as it must combine low power consumption, small area and robustness against power supply variations. This paper presents a compact ADC implementation which converts the signal coming from a MEMS (Micro Electro– Mechanical System) accelerometer, which has a high potential for a variety of applications in mobile phones, laptops, game consoles and handheld devices. The accelerometer is a singleended output signal structure presently available in a 0.35 m m CMOS technology, which is still a reliable and cheap technology for MEMS. The whole system is intended to be powered by an UHF RFID front-end, which provides a 3 V nominal supply voltage typical for the selected technology [1]. As the ADC will be integrated in the same die with the MEMS accelerometer, it has been designed in the same technology with a single-ended input. The basic ADC specifications are summarized in Table 1. A resolution of 8 bits is required in a 25 kHz signal bandwidth. Although the nominal supply voltage is 3 V, the ADC must have a Contents lists available at SciVerse ScienceDirect journal homepage: www.elsevier.com/locate/vlsi INTEGRATION, the VLSI journal 0167-9260/$ - see front matter &2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.vlsi.2012.10.001 n Corresponding author. Tel.: þ34 954 481 308. E-mail address: [email protected] (F. Mun ˜oz). Please cite this article as: E. Lo ´pez-Morillo, et al., Compact low-power implementation for continuous-time SD modulators, INTEGRATION, the VLSI journal (2012), http://dx.doi.org/10.1016/j.vlsi.2012.10.001 INTEGRATION, the VLSI journal ](]]]])]]]–]]] 278 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS “A Novel CMOS Tunable Linear Transconductor Based on Quasi Floating Gate Transistors,” XXIII Conference of Design of Circuits and Integrated Systems (DCIS’2008), 2008. T. Sánchez-Rodríguez1, F. Muñoz1, Jose Ramón García1, Jose Manuel Rodríguez1, Mariano Jimenez-Fuentes1 and R. G. Carvajal1 1. Escuela Superior de Ingenieros, Departamento de Ingeniería Electrónica, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Sevilla, Spain Abstract— A novel CMOS low voltage tunable linear transconductor is presented. It is based on the transconductor presented in [1] and [2]. The transconductor presented in [2] employs Floating-Gate Transistors at the input stage of each inverter of the architecture presented by Nauta in [1], improving its low voltage operation capabilities. The approach proposed here employs quasi-floating gate transistors instead of floating gate transistors, obtaining further improvements such as higher transconductance and rejection DC common mode voltage. Moreover, a dynamic biasing technique has been incorporated, in order to solve one of the mayor drawbacks of previous implementations, the sensitivity of the linearity of the transconductor to process variations. The presented transconductor achieves very high speed operation and it is suitable for high frequency continuous time filters. It has been designed in a 0.5 μm CMOS technology from 1.4 V power supply. Index Terms—Analog CMOS, Quasi-Floating Gate Transistors, Transconductor. I. INTRODUCTION HE market in which we are involved is looking for highspeed and low-power transconductor amplifiers for portable communications systems [1]-[4]. The reduction in power consumption and the scaling down of supply voltages can be achieved using specific low-voltage techniques as the one proposed in [5] and high frequency operation can be obtained using transconductors with a reduced number of internal nodes (poles) as in [1] and [2]. The main advantage of the transconductor presented by Nauta in [1] is that the absence of internal nodes leads to very high frequency operation. Despite of this attractive feature, there are some drawbacks which do not allow reliable programmability methods, biasing schemes to overcome process variations or low voltage operation capabilities: The supply voltage must be larger than the sum of the threshold voltages of a p-mos and a n-mos transistors. Programmability of the transconductance is achieved by modifying the supply voltage. It is quite sensitive to the input common mode voltage and process variations (any offset at the input appears at the output and any variation at the value of the input common mode voltage degrades the output common mode voltage decreasing the linearity of the transconductor). Although the approach in [2] allows simple implementation of programmability schemes and low voltage operation by using Multiple-Input Floating-Gate transistors, this is at the cost of a reduction of the transconductance due to the capacitive divider in the floating gate transistor terminals, and therefore, the maximum achievable working frequency is reduced. Moreover, the sensitivity of the transconductor to process variations was still an open issue. In this paper a new transconductor based on quasi-floating gate transistors is presented. It solves the problem of the sensitivity of the transconductor to process variations, provides a simple programmability scheme, and increases the transconductance, while maintaining the low voltage operation capabilities and the very high frequency operation due to the absence of internal nodes. In Section II the proposed transconductor architecture will be described and its advantages will be explained. Moreover, section III will provide simulation results of the transconductor that confirms the theoretical assumptions. As it will be seen in this section, the transconductor presents improved performances in terms of programmability, sensitivity to process variations and low voltage operation capabilities while maintaining noise, linearity and power consumption figures. The OTA has been laid-out and sent for fabrication in a standard 0.5 μm CMOS technology, so as experimental results will be provided during the conference. II. PROPOSED TRANSCONDUCTOR A. Quasi-Floating Gate Transistors Quasi-Floating Gate Transistors have recently been used for many analog circuits as they present improved performances for circuits in which any possible offset at the input voltage cause degradation of the circuit operation [5]. As it is reported in [6], a quasi floating gate (QFG) A Novel CMOS Tunable Linear Transconductor Based on Quasi Floating Gate Transistors T 280 Appendix C: Publications SUBSAMPLING RECEIVERS WITH APPLICATIONS TO SOFTWARE DEFINED RADIO SYSTEMS “A Very Low Power 8-Bit 16MSamples/s Pipelined Converter for DVB-H,” XXIII Conference of Design of Circuits and Integrated Systems (DCIS’2008), 2008. A VERY LOW POWER 8-BIT 16MSAMPLES/S CMOS PIPELINED CONVERTER FOR DVB-H B. Palomo, F. Muñoz, R.G. Carvajal, J.R. García, H. ElGmili and A. Torralba Grupo de Ingeniería Electrónica, Universidad de Sevilla Abstract. A 2.5V, 8-bit, 16 MS/s pipeline analog-to-digital converter (ADC) for DVB application and battery powered systems has been implemented in 0.35 μm CMOS technology. In order to reduce the power consumption a combination of techniques has been used, such as op-amp sharing, low-power amplifiers with gain boosting and an aggressive capacitor scaling. The post-layout simulation shows a peak signal-to-noise-anddistortion ratio (SNDR) of 48.51 dB, maximum differential nonlinearity (DNL) of 0.40 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.06 LSB, and a power consumption of less than 4 mW. 1. INTRODUCTION During the last few years much effort has been devoted towards the reduction of the supply power of mixed signal CMOS systems. This is primarily due to the increasing importance of battery-powered electronics, and the continued down-scaling of device sizes. Pipelining has been accepted as the best approach to implement high-speed medium-to-high resolution analog-to-digital converters with minimum power consumption. 2. 1.5-BIT/STAGE STRUCTURE This 1.5 bit configuration is particularly suitable to minimize the converter’s total power dissipation [1]-[3] because the amplifiers operate at a low closed-loop gain leading to a best settling time for minimum power consumption. A block diagram of the pipeline 1.5-bit/stage architecture is shown in Fig 1. It consists of a cascade of seven stages. Each stage resolves two bits with a sub–ADC, subtracts the converted value from its inputs, and amplifies the resulting residue by a gain of two. The last stage of the pipeline does not need to generate a residue and, then, it does not require an opamp. The resulting 14 bits are combined with digital correction to yield eight bits at the output of the ADC. Comparators offset up to ±Vref/4 can be tolerated without degradation of the overall SNDR using the mentioned technique. Stage 1 Stage i Stage 7 n1 bits ni bits n7 bits ADC i DAC i + Vin (i) Dout (i) Vcda (i) Vout (i) Vres(i)2X S/H Figure1. Pipeline-ADC 1.5-bit/stage architecture. A fully differential solution has been implemented to maximize the power supply rejection ratio (PSRR) and to minimize even harmonic distortion. A switched-capacitor implementation was also selected, which operates using a non-overlapping two-phase clock. 3. LOW POWER TECHNIQUES The main contribution of this paper is the clever combination of different power saving techniques to achieve a very low power solution, which will be now described. 3.1. The sample and hold amplifier The sample and hold amplifier (SHA) at the input of the pipelined converter usually takes one third of the overall converter power consumption [8]. The dedicated SHA has been removed in our design and the sampling operation is performed by the switchedcapacitor residue amplifier (based on a MDAC) of the first stage. In this case, special care needs to be paid to the input switches involved in the sampling process, and a clockboosting technique [4] has been implemented to improve its linearity. In this way a resistance independent on the input signal is achieved in the “on” state, as a constant voltage is applied across the gate-to source terminals of the NMOS transistor switch.