Baseband-processor for a passive UHF RFID transponder

Baseband-P ocesso o a Passi e UHF RFID T ansponde Jose A. Rod iguez-Rod iguez*, Manuel Delgado-Res i u o and Angel Rod iguez-Vazquez Ins i u e o Mic oelec onics o Se ille (lMSE-CNM-CSIC) -Uni e si y o Se ille Pa que Tecnol6gico de la Ca uja, A da. Ame ico Vespucio sin, 41092-Se ille, SPAIN Abs ac -This pape desc ibes he design o a dig i al p ocesso a ge ing he Class-l Gene a ion-2 EPC P o ocol o UHF RFID ansponde s, and p oposes di  e en echniques o educing i s powe consump ion. The p ocesso has been implemen ed in a O.35�m CMOS echnology p ocess using au oma ic ools o bo h he logic syn hesis and layou . Pos -layou simula ions con i m he ully unc ionali y o he p o o ype and p edic a wo s -case powe consump ion o only 2.9�A a 1.2V sup ply. I. INTRODUCTION Nowadays, Radio equency IDen i ica ion (RFID) de ices ind many applica ions in ields such as manu ac u ing, p oduc dis ibu ion and sales, au o mo i e, anspo a ion and cus ome se ices, and building access con ol [1, 2]. RFID communica ions use a mas e -sla e con igu a ion o med by a eade and a se o ansponde s ( ags, in sho ) [3,4]. Each ag has a unique iden i ica ion numbe s o ed in a non- ol a ile memo y, which is add essed by he eade o es ablish he communica ion link. Upon he commands sen by he eade , he selec ed ag deli e s he eques ed in o ma ion. In he so-called senso y ags, such in o ma ion migh no only consis on iden i ica ion da a bu also con ain en i onmen al eadou s (e.g., empe a u e, p essu e, op ical o chemical a iables) ob ained om an embedded senso in e ace. The abil i y o senso y ags o moni o , eco d and e en eac o ambien condi ions a e expec ed o p omo e a new wo ld o applica ions o RFIDs. Tags a e classi ied in o ac i e o passi e depend ing on how ene gy is supplied o he de ice. Passi e ags ha e no in e nal powe sou ce a ailable, as in he case o ac i e ansponde s, bu hey a e emo ely biased by he eade by means o an on-chip RF- o-DC con e sion s age [5, 6]. Because o he sca ce supply ing condi ions, powe consump ion minimiza ion is a p io i y o passi e ags. This pape ocuses on he design o he digi al sec ion a passi e UHF RFID senso y ag o hal -duplex communica ions in he 860-960 MHz ange. The base band p ocesso implemen s he EPCTM Class-l Gene  a ion-2 (Gen2) p o ocol [7], which is b ie ly e iewed in Sec ion II. Gi en he complexi y o he p o ocol, he powe consump ion o he baseband p ocesso is com pa able o ha o he analog sec ion o he ag [4]. Hence, i is necessa y o apply low-powe design s a - egies a i s implemen a ion. These powe sa ing ech niques and he a chi ec u e o he baseband p ocesso a e p esen ed in Sec ion III. Nex , Sec ion IV shows he layou o he p ocesso and p esen s ex ac ed simula ions which con i m he sys em unc ionali y and p e dic a wo s -case powe consump ion o only 2.9/-lA a I.2V supply. Finally, Sec ion V concludes he pape . II. EPC GEN 2 REVIEW The EPCTM Class-l Gene a ion-2 (Gen2) p o ocol [7] is a highly lexible p o ocol which allows a wide a ie y o ai in e ace and encoding possibili ies: • Reade o ag communica ions ( o wa d link) can be done wi h h ee ypes o ASK modula ion using £ulse-In e al Encoding (PIE) o ma . • Tags communica e in o ma ion o he eade (backwa d link) by backs e ch modula ing he ampli ude and/o phase o he RF ca ie using ei he I-phase space (FMO) o Mille -Modula ed Subchase (MMSC) encoding o ma s. • The s anda d suppo s di e en da a a es bo h a he o wa d ( om 26.7 o 128 kbps) and backwa d ( om 5 o 640 kbps) links. Fo wa d link communica ions is always p eceded by a p eamble. Fig.l(a) shows an example, co e sponding o a Que y ins uc ion. The p eamble com p ises a ixed-leng h s a delimi e , a da a-O symbol, a eade - o- ag calib a ion symbol (RTeaT), and ag- o- eade calib a ion symbol (TReaT). These wo la e symbols a e used o de ine he o wa d and back wa d da a a es, espec i ely. In o he ins uc ions, only he RTeal symbol is ansmi ed. The du a ion o RTeal is equal o he leng h o a da a-O symbol plus he leng h (a) (b) 12.5,us±5% ITa!'; 2.5·Ta!';';'x';'3·Ta!'; 1.l·llTcal';'x';'3·llTcal Ta i 0.51'ol';:S; x S; To i da�-O R:J� J I PIV I da�-1 L-...J Fig. 1: (a) P eamble used in eade o ag signalling. (b) Da a encoding in PIE o ma . * Con ac au ho : [email p o ec ed]; phone +34954466666; h p://www.imse-cnm.csic.es 978-1-4244-6878-2/10/$26.00 ©2010 IEEE 344 o a da a-I symbol. They a e bo h ep esen ed in Fig.1 (b) and de ine he PIE encoding used o eade - o- ag signalling. The du a ion o a logical '0', called Ta i, amoun s 6.25 o 25J.ls. The leng h o he logical' I' can ange be ween 1.5*Ta i o 2* Ta i. Rise ime, all ime and pulse wid h (PW) a e iden ical o da a-O and da a-I symbols and hei alid anges a e de ined in he p o ocol. Signal decoding a he ag is simply accomplished by a ime- o-digi al con e sion using a mas e clock signal. The numbe o clock cycles comp ised du ing he symbol RTCal a e compu ed and di ided by 2 o de me a pi o . I a symbol has less numbe o cycles han pi o hen i is a da a-O symbol, o he wise is a da a-I symbol. Da a a es o he backwa d link a e ob ained by di iding he mas e clock equency by in ege alues. The numbe o clock cycles pe bi in he backwa d link, N BLF' is, he e o e, compu ed as _ {in (TRCal- m)} NBLF - ound DR (I) whe e he di ide a io, DR , speci ied in he Que y command, can be 8 o 64/3; m is he mas e clock e quency; and in (·) is an ope a o whose ou pu may ake on wo possible in ege alues which a e ob ained by ei he ounding up o down i s a gumen . In (1), such in ege numbe depends on he a p io i unknown phase ela ion be ween he local oscilla o and he demodula ed RF signal. The Gen 2 p o ocol de ines ole ance ma gins o he di e en backwa d equen cies which can be syn hesized om (1). Taking in o accoun hese ole ances and he iming esolu ion equi emen s o he o wa d link, as well as, he need o educing he dynamic powe consump ion o he p ocesso , i can be ound ha he minimum mas e clock equency imposed by Gen2 equi emen s is 1.92 MHz [8, 9]. Besides he al eady men ioned Que y command, he EPC Gen 2 p o ocol de med many o he s com mands/ac ions bo h o he o wa d and backwa d links. Thei desc ip ion is beyond he scope o his pape , none heless, i is wo h men ioning ha hey all ha e been ully implemen ed in he p oposed baseband p ocesso . III. BASEBAND PROCESSOR lIl . Low-Powe Design S a egies Besides selec ing he lowes clock equency able o comply wi h he Gen2 speci ica ions, wo ha d wa e-le el echniques ha e been conside ed o powe sa ing. They a e e e ed o as �lock-Qa ing (CG) and �lock-Managemen (CM) [6]. A. Clock Ga ing Powe consump ion can be educed by ac i a ing 345 he minimum numbe o blocks [10]. Fo ins ance, i he sys em has no comple ely in e p e ed a ecei ed command, he e is no need o ac i a e hose blocks equi ed o backwa d link communica ions. Clock ga ing builds on his idea, i.e., disabling blocks when hey a e dispensable [11]. This can be simply done by and-combining he clock o igge pulses which ac i a e he block wi h an enable lag, in acco dance wi h he command ha he p ocesso is cu en ly handling. B. Clock Managing Depending on he p ocesso s a e, some o hei blocks can ope a e a equencies below he mas e clock. As will be shown nex , depending on he com mand ha is being handled, only ou blocks need o un a ull speed: Pie_Decode , FSM_Co e, FSM_Tx and Tx. The es o he blocks can be clocked a a ac ion o he mas e equency o sa e powe . The lowe limi o he dedica ed clock equencies is de e mined by he ime in e al be ween wo ising edges o he demodula ed inpu signal. 111.2. A chi ec u e Fig.2 shows he block diag am o he p ocesso . I is a sys em con olled by a Timing Uni which gene  a es he clock and igge signals equi ed o he decoding, encoding and p ocessing ope a ions. This block is esponsible o he implemen a ion o he low-powe design s a egies desc ibed abo e. In he decoding sec ion, a alling-edge igge ed lip- lop is used o synch onize he demodula ed signal coming om he analog on -end o he RFID, da a _ dem, o he mas e clock signal. Reade o ag communica ions use £ulse-In e al Encoding (PIE) o ma and, he e o e, he esul ing digi ized o wa d link, da a _in, mus be con e ed in o bina y o ma . This is accomplished in he PIE Decode block whose ou pu is sequen ially s o ed in a 16-bi Shi Regis e block a a a e de med by he igge pulses, enyulse_shi . Once he p eamble pa ame e s a e ead, he PIE Decode se s on he end y ea lag. Nex , he Command Decode block e alua es he da a s o ed in he egis e o iden i y which ins uc ion has been sen by he eade . This is a simple ask because commands in he EPC Gen 2 p o ocol include a ield which unequi ocally add esses he ins uc ion ecei ed by he ag. Ope a ion o he Command Decode block is con olled by he igge signal enyulse_cmd, a delayed e sion o enyulse_shi , o allow a mo e uni o m dis ibu ion o cu en consump ion o e ime. When he command ecei ed is iden i ied, he Command Decode se s on he end_cmd lag and codi ies he ins uc ion in a 4-bi ec o , cmdJD. Besides illing Shi Regis e , he ou pu o he PIE Decode block is also ans e ed o a �clic Redun dancy �heck (CRe) uni o ansmission e o de ec ion. The EPC Gen 2 p o ocol uses wo ypes o CRC; en- Julse shi en- Julse=cmd en- JulseJx Decoding en- Julse_5 en- Julse_16 clk- Jie clk co e c/Ox Encoding clk3dc S ack FSM_Tx G � ··· 0 Senso Fig. 2: A chi ec u e o he p oposed baseband-p ocesso CRC-5 and CRC-16. The o me is used by Que y commands, whe eas he la e is used by Selec and Access commands. In en o y commands a e unp o ec ed. Once he Command Decode iden i ies he ype o ins uc ion ha i is being ecei ed, i disables he useless CRC block(s) o powe sa ing. The esul s o he CRC compu a ions a e s o ed in bu e s and hese alues a e used by a Check CRC block o assess hei alidi y. The CRC blocks, CRC-5 o CRC-16 a e ena bled each ising edge o da a _in, employing pulses enyulse_5 and enyulse_I6, espec i ely. Once he command is iden i ied, he Command Decode passes cmd jD o he FSM Rx block, inside he p ocessing sec ion. This block is con olled by he igge pulses en yulse JX, a delayed e sion o signal enyulse_cmd, and i is o med by a se o Fini e S a e Machines (FSM), one pe Gen2 command. Only ha FSM add essed by he Command Decode is ac i e; he o he s a e disabled. The ac i e FSM sequen ially s o es he command pa ame e s in he egis e s o he S ack block. Only ha egis e which is being add essed by he FSM Rx block is ac i e, he o he s emain o . The FSM Rx block no i ies he Timing Uni by means o he s ackJeady lag when he ecep ion is mished and, hen, he igge pulses o he CRC mod ules and he PIE Decode block a e disabled. The FSM Co e block decides he ag's s a e, pe  o ms he equi ed s a e ansi ions, ead he pa ame e s s o ed in he S ack by he FSM Rx, and igge s he FSM Tx block acco ding o he command ha has been ecei ed. When ope a ions a FSM Co e a e concluded a non-ze o 5-bi ec o , o de _ou , is ansmi ed o he 346 clUx P ocessing FSM Tx block and FSM Co e is disabled by he Timing Uni . A he encoding sec ion, he FSM Tx block pe  o ms he ac ions eques ed by he eade such as w i e/ ead he EEPROM, ga he pa ame e s o in o  ma ion o send, and con ol he ansmi e o he backwa d link. The ac ions a e g ouped in o 7 ypes, acco ding o he da a o ma o be ansmmi ed o he ope a ion o be execu ed by he Encoding sec ion o he baseband-p ocesso . The e is one FSM o each possi ble ac ion ype, and, as be o e, only one FSM is ena bled a a ime. The Tx block encodes he da a in FMO o MMSC a he bi a e eques ed by he eade . When he eques ed ac ion has been mished o he ansmis sion is comple ed, he FSM Tx block se s on he lag end_ ans e , FSMTx and Tx (i equi ed) a e disabled, and FSM Co e is ac i a ed again o check i he p oc esso mus change he s a e o emain in he same con igu a ion. A e his e alua ion, FSM Co e se s on he lag end_co e. O he impo an blocks o he RFID ag a e a Ran dom Numbe Qene a o (RNG), o secu ing commu nica ions, and a mixed-signal ci cui y o gene ic senso signal acquisi ion. This la e consis s o a Sig nal Condi ioning block and a .successi e App oxima ion Regis e (SAR) ADC. The o me is used o adap he senso y in o ma ion o he signal ange o he ADC. The ADC is clocked by he Timing Uni block h ough he signal clk_adc, and i s ope a ion is con olled by he FSM Tx block. Addi ionally, a lip- lop, no shown in Fig.2, has been included o synch onize a gene al baseband ese signal o he mas e clock. dala in n -,.-----, 'nn ln m TIlYmnn -,n � da a Olll_ ----, ,-- __________ ----' : II.IJU1 ll L =� cik Ix II T C a / � i � O � i · � : i � i i i 3 iO ; ii i � l....!!..- � O � Tllcal 0 0 pi ol I s l....!!.._ masle elk el yie enYlIlse_cllld _ � __ _____, ���;--;-;-c c;_;_-;-;-_;_;_;__;_;_; -  en Yliise JX ----- -��.I..l. LU..JU-l..J...J..-L.LJ.-L.U-- enYliIseJ cl6 _ ___ + -!-!-:�-;-;-:I;-;-;-: ;-;-;--;-;--;-;-;-_;_;_; - - enYlilseJ c5 ----A- ...u..JU-l.J..J..J � L..L...L .J...J.. ......... -L.U -- mas e _elk JUUUliUUUUliU1J dala_in enyulse_cllld 1 ____ ----' enyulse_ .x I _____ � en Yliise J c5 I======----===::j Fig. 3: Expe imen al Resul s. IV. SIMULATION AND EXPERIMENTAL RESULTS P io o silicon in eg a ion, he baseband p ocesso was syn hesized on a Xilinx XC3S1000 FPGA o debugging pu poses. A e an exhaus i e es , he VHDL code was ound ully unc ional. As an illus a ion, Fig.3 shows he expe imen al e i ica ion o a Que y command ansmission a 128 kbps, and a esponse ansmission a 640 kbps, bo h he maximum equency allowed in he o wa d and backwa d link, espec i ely. The scopes we e cap u ed using he logic analyse Agilen 16902B. The igu e shows ha he p ocesso success ully calcula es he iming cons an s implica ed in he RFID communica ion. Fig.3 also illus a es he clock ga ing echnique employed in he p ocesso . The PIE Decode is only enabled when he ag is ecei ing da a and i is disabled o he wise. The FSM Tx wo ks a maximum equency in his pa icula example (a Que y command) bu i is only enabled du ing da a ansmission. The CRC-J6 and CRC-5 modules a e enabled when he ag is decod ing he in o ma ion sen by he eade and, when he p ocesso de ec s ha he ecei ed command do no use CRC-J6, co esponding block is disabled. Finally, i can be seen in he inse ha he di e en clocks a e delayed among hemsel es o lowe he peaks o dynamic powe . A e FPGA alida ion, a silicon p o o ype has been designed in a 0.351lm CMOS echnology. I s lay ou is shown in FigA, whe e a bank o supply capaci o s and an ADC o senso signal acquisi ion can be iden i ied oge he wi h he p ocesso and he EEP ROM. The chip occupies 7mm2 including pads. The ADC is an ul a low-powe lO-bi SAR con e e , in ended o slow- a ying signals. I is clocked by a signal 128 imes slowe han he mas e clock ( he ADC in e nally di ides elk_adc by 2), equi es 12 347 Fig. 4: Layou o he RFIO baseband-p ocesso . clock cycles o comple e a con e sion and only con sumes 150n W. Fig.5 shows an exempla y pos -layou simula ion o he p o o ype, in his case, illus a ing he ADC ope a ion when he ag ecei es a W i e command. A e an ini ial ese , he ADC makes i e consecu i e con e sions which a e ans e ed o he FSM Tx block a e e y adc _da a ..Jeady pulse. Once he las con e  sion is pe o med, he ADC en e s in powe down mode and he FSM Tx block a e ages he samples and s o es he esul in he EEPROM. The powe consump ion o he p ocesso was es i ma ed using digi al and analog models o he base band-p ocesso and he ADC, espec i ely, assuming maximum bi - a es o he o wa d and backwa d links. Fig.6 illus a es he dissipa ion pe block du ing a com munica ion lux which in ol es i e consecu i e com mands, including ag selec ion and memo y eading. In o al, he p ocesso consumes less han 2.9IlA, assum ing wo s -case iming condi ions. No e ha he Timing Uni , FSM Tx, TX and PIE Decode blocks a e he mos powe -demanding elemen s o he p ocesso because hey a e clocked a he mas e equency. Anyhow, he powe consump ion o he la e wo blocks has been conside ably educed hanks o he applied clock ga  ing echniques. Table I compa es he achie ed pe o mance wi h o he implemen a ions in he li e a u e. As can be seen, [6] achie es lowe powe consump ion, howe e , i is clocked a a mas e equency o 480kHz and i does no suppo he comple e EPC Gen2 s anda d. Re e  ences [10], [12] and ully comply wi h he s anda d bu a a highe powe consump ion han in he p oposed p ocesso . Finally, [13] adds an AES c yp og aphic TABLE I. Compa ison wi h p e iously published designs. Mas e Cu en CMOS Re e ence F equency Consump ion Technology [6] 480 KHz 1.471lA 0.35 11m [10] 2.56 MHz 6.401lA 0.18 11m [12] 1.28 MHz 5.1 IlA 0.35 11m [13] 2MHz 4.171lA 0.18 11m This wo k 1.92 MHz 2.9 I A 0.35 11m Fig. 5: Communica ion be ween he P ocesso and he ADC 3,0000 .FSW Rx • Shi « Re9is.� 2,5000 aCRe-IS :::L .CRC-:i c-.C"""'""" 0..- .Q 2,0000 OS"" li E :::J 1,5000 (J) c 0 • O he s ) 1,0000 C o SyncFlipFlopl � • SyncFlipFlopO 0,5000 • FShI Co e :::J o FShITx&TX <..) • PieDecode 0,0000 • Timing Uni Fig. 6: Cu en consump ion pe block o he baseband-p oces so module o he ag bu only suppo s he manda o y commands de med by he s anda d and uses a CMOS echnology wi h a smalle ea u e size. V. CONCLUSIONS In his wo k, a baseband p ocesso o RFID appli ca ions a ge ing he EPC Gen2 p o ocol has been designed and implemen ed in a 0.35J.lm CMOS p oc ess. The design was alida ed in a Xilinx Spa an3 FPGA, and he pos -layou simula ions show ha he p ocesso consumes less han 2.91.1A ope a ing a max imum equency allowed o he backwa d and o wa d link. 348 ACKNOWLEDGMENTS This wo k was suppo ed by he Spanish Minis y o Educa ion & Science unde g an s TEC2006-03022 and TEC2009-08447, and he Jun a de Andalucia unde g an TIC-02818. REFERENCES [1] K. Finkenzelle , RFID Handbook: Fundamen als and Applica ions in Con ac less Sma Ca ds and Iden i ica ion, 2nd ed. John Wiley & Sons L d, Chiches e (UK), 2003. [2] D. Dolkin, The RF in RFID Passi e-UHF -RFID in P ac ice. Newnes, Ams e dam (The Ne he lands), 2008. [3] C. Ma, X. Wu, C. Zhang, and Z. Wang, "A low-powe RF on -end o passi e UHF RFID ansponde s." IEEE Asia Paci ic Coi . Ci cui s Sys ems (APCCAS 2008), pp.73-76, Dec. 2008. [4] J.-P. Cu y, M. Decle cq, C. Dehollain, and N. Joeh!. Design and Op imiza ion o Passi e UHF RFID Sys ems. Sp inge , New Yo k, 2007. [5] U. Ka haus, and M. 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