Baseband-processor for a passive UHF RFID transponder

Baseband-Processor for a Passive UHF RFID Transponder Jose A. Rodriguez-Rodriguez*, Manuel Delgado-Restituto and Angel Rodriguez-Vazquez Institute of Microelectronics of Seville (lMSE-CNM-CSIC) -University of Seville Parque Tecnol6gico de la Cartuja, Avda. Americo Vespucio sin, 41092-Seville, SPAIN Abstract -This paper describes the design of a dig ital processor targeting the Class-l Generation-2 EPC Protocol for UHF RFID transponders, and proposes dif ferent techniques for reducing its power consumption. The processor has been implemented in a O.35�m CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations con firm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9�A at 1.2V sup ply. I. INTRODUCTION Nowadays, Radio frequency IDentification (RFID) devices find many applications in fields such as manufacturing, product distribution and sales, auto motive, transportation and customer services, and building access control [1, 2]. RFID communications use a master-slave configuration formed by a reader and a set of transponders (tags, in short) [3,4]. Each tag has a unique identification number stored in a non-vol atile memory, which is addressed by the reader to establish the communication link. Upon the commands sent by the reader, the selected tag delivers the requested information. In the so-called sensory tags, such information might not only consist on identifica tion data but also contain environmental readouts (e.g., temperature, pressure, optical or chemical variables) obtained from an embedded sensor interface. The abil ity of sensory tags to monitor, record and even react to ambient conditions are expected to promote a new world of applications for RFIDs. Tags are classified into active or passive depend ing on how energy is supplied to the device. Passive tags have no internal power source available, as in the case of active transponders, but they are remotely biased by the reader by means of an on-chip RF-to-DC conversion stage [5, 6]. Because of the scarce supply ing conditions, power consumption minimization is a priority for passive tags. This paper focuses on the design of the digital sec tion a passive UHF RFID sensory tag for half-duplex communications in the 860-960 MHz range. The base band processor implements the EPCTM Class-l Gener ation-2 (Gen2) protocol [7], which is briefly reviewed in Section II. Given the complexity of the protocol, the power consumption of the baseband processor is com parable to that of the analog section of the tag [4]. Hence, it is necessary to apply low-power design strategies at its implementation. These power saving tech niques and the architecture of the baseband processor are presented in Section III. Next, Section IV shows the layout of the processor and presents extracted simula tions which confirm the system functionality and pre dict a worst-case power consumption of only 2.9/-lA at I.2V supply. Finally, Section V concludes the paper. II. EPC GEN 2 REVIEW The EPCTM Class-l Generation-2 (Gen2) protocol [7] is a highly flexible protocol which allows a wide variety of air interface and encoding possibilities: • Reader to tag communications (forward link) can be done with three types of ASK modulation using £ulse-Interval Encoding (PIE) format. • Tags communicate information to the reader (backward link) by backstretch modulating the amplitude and/or phase of the RF carrier using either I-phase space (FMO) or Miller-Modulated Subchaser (MMSC) encoding formats. • The standard supports different data rates both at the forward (from 26.7 to 128 kbps) and backward (from 5 to 640 kbps) links. Forward link communications is always preceded by a preamble. Fig.l(a) shows an example, corre sponding to a Query instruction. The preamble com prises a fixed-length start delimiter, a data-O symbol, a reader-to-tag calibration symbol (RTeaT), and tag-to-reader calibration symbol (TReaT). These two latter symbols are used to define the forward and back ward data rates, respectively. In other instructions, only the RTeal symbol is transmitted. The duration of RTeal is equal to the length of a data-O symbol plus the length (a) (b) 12.5,us±5% ITa!'; 2.5·Ta!';';'x';'3·Ta!'; 1.l·llTcal';'x';'3·llTcal Tari 0.51'ol';:S; x S; Tori da�-O R:J� J I PIV I da�-1 L-...J Fig. 1: (a) Preamble used in reader to tag signalling. (b) Data encoding in PIE format. * Contact author: [email protected]; phone +34954466666; http://www.imse-cnm.csic.es 978-1-4244-6878-2/10/$26.00 ©2010 IEEE 344 of a data-I symbol. They are both represented in Fig.1 (b) and define the PIE encoding used for reader-to-tag signalling. The duration of a logical '0', called Tari, amounts 6.25 to 25J.ls. The length of the logical' I' can range between 1.5*Tari to 2* Tari. Rise time, fall time and pulse width (PW) are identical for data-O and data-I symbols and their valid ranges are defined in the protocol. Signal decoding at the tag is simply accomplished by a time-to-digital conversion using a master clock signal. The number of clock cycles comprised during the symbol RTCal are computed and divided by 2 to defme a pivot. If a symbol has less number of cycles than pivot then it is a data-O symbol, otherwise is a data-I symbol. Data rates of the backward link are obtained by dividing the master clock frequency by integer values. The number of clock cycles per bit in the backward link, N BLF' is, therefore, computed as _ {int(TRCal-fm)} NBLF -round DR (I) where the divide ratio, DR , specified in the Query command, can be 8 or 64/3; fm is the master clock fre quency; and int(·) is an operator whose output may take on two possible integer values which are obtained by either rounding up or down its argument. In (1), such integer number depends on the a priori unknown phase relation between the local oscillator and the demodulated RF signal. The Gen 2 protocol defines tolerance margins for the different backward frequen cies which can be synthesized from (1). Taking into account these tolerances and the timing resolution requirements of the forward link, as well as, the need for reducing the dynamic power consumption of the processor, it can be found that the minimum master clock frequency imposed by Gen2 requirements is 1.92 MHz [8, 9]. Besides the already mentioned Query command, the EPC Gen 2 protocol defmed many others com mands/actions both for the forward and backward links. Their description is beyond the scope of this paper, nonetheless, it is worth mentioning that they all have been fully implemented in the proposed baseband processor. III. BASEBAND PROCESSOR lIlt. Low-Power Design Strategies Besides selecting the lowest clock frequency able to comply with the Gen2 specifications, two hard ware-level techniques have been considered for power saving. They are referred to as �lock-Qating (CG) and �lock-Management (CM) [6]. A. Clock Gating Power consumption can be reduced by activating 345 the minimum number of blocks [10]. For instance, if the system has not completely interpreted a received command, there is no need to activate those blocks required for backward link communications. Clock gating builds on this idea, i.e., disabling blocks when they are dispensable [11]. This can be simply done by and-combining the clock or trigger pulses which acti vate the block with an enable flag, in accordance with the command that the processor is currently handling. B. Clock Managing Depending on the processor state, some of their blocks can operate at frequencies below the master clock. As will be shown next, depending on the com mand that is being handled, only four blocks need to run at full speed: Pie_Decoder, FSM_Core, FSM_Tx and Tx. The rest of the blocks can be clocked at a frac tion of the master frequency to save power. The lower limit of the dedicated clock frequencies is determined by the time interval between two rising edges of the demodulated input signal. 111.2. Architecture Fig.2 shows the block diagram of the processor. It is a system controlled by a Timing Unit which gener ates the clock and trigger signals required for the decoding, encoding and processing operations. This block is responsible for the implementation of the low-power design strategies described above. In the decoding section, a falling-edge triggered flip-flop is used to synchronize the demodulated signal coming from the analog front-end of the RFID, data _ dem, to the master clock signal. Reader to tag communications use £ulse-Interval Encoding (PIE) format and, therefore, the resulting digitized forward link, data _in, must be converted into binary format. This is accomplished in the PIE Decoder block whose output is sequentially stored in a 16-bit Shift Register block at a rate defmed by the trigger pulses, enyulse_shift. Once the preamble parameters are read, the PIE Decoder sets on the end yrea flag. Next, the Command Decoder block evaluates the data stored in the register to identify which instruction has been sent by the reader. This is a simple task because commands in the EPC Gen 2 protocol include a field which unequivocally addresses the instruction received by the tag. Operation of the Command Decoder block is controlled by the trigger signal enyulse_cmd, a delayed version of enyulse_shift, to allow a more uniform distribution of current consump tion over time. When the command received is identi fied, the Command Decoder sets on the end_cmdflag and codifies the instruction in a 4-bit vector, cmdJD. Besides filling Shift Register, the output of the PIE Decoder block is also transferred to a �clic Redun dancy �heck (CRe) unit for transmission error detec tion. The EPC Gen 2 protocol uses two types of CRC; en-fJulse shift en-fJulse=cmd en-fJulseJx Decoding en-fJulse_5 en-fJulse_16 clk-fJie clk core c/Ox Encoding clk3dc Stack FSM_Tx G � ··· 0 Sensor Fig. 2: Architecture of the proposed baseband-processor CRC-5 and CRC-16. The former is used by Query commands, whereas the latter is used by Select and Access commands. Inventory commands are unpro tected. Once the Command Decoder identifies the type of instruction that it is being received, it disables the useless CRC block(s) for power saving. The results of the CRC computations are stored in buffers and these values are used by a Check CRC block to assess their validity. The CRC blocks, CRC-5 or CRC-16 are ena bled each rising edge of data _in, employing pulses enyulse_5 and enyulse_I6, respectively. Once the command is identified, the Command Decoder passes cmd jD to the FSM Rx block, inside the processing section. This block is controlled by the trigger pulses en yulse JX, a delayed version of signal enyulse_cmd, and it is formed by a set of Finite State Machines (FSM), one per Gen2 command. Only that FSM addressed by the Command Decoder is active; the others are disabled. The active FSM sequentially stores the command parameters in the registers of the Stack block. Only that register which is being addressed by the FSM Rx block is active, the others remain off. The FSM Rx block notifies the Timing Unit by means of the stackJeady flag when the reception is fmished and, then, the trigger pulses of the CRC mod ules and the PIE Decoder block are disabled. The FSM Core block decides the tag's state, per forms the required state transitions, read the parame ters stored in the Stack by the FSM Rx, and triggers the FSM Tx block according to the command that has been received. When operations at FSM Core are concluded a non-zero 5-bit vector, order_out, is transmitted to the 346 clUx Processing FSM Tx block and FSM Core is disabled by the Timing Unit. At the encoding section, the FSM Tx block per forms the actions requested by the reader such as write/read the EEPROM, gather parameters or infor mation to send, and control the transmitter for the backward link. The actions are grouped into 7 types, according to the data format to be transmmited or the operation to be executed by the Encoding section of the baseband-processor. There is one FSM for each possi ble action type, and, as before, only one FSM is ena bled at a time. The Tx block encodes the data in FMO or MMSC at the bit rate requested by the reader. When the requested action has been fmished or the transmis sion is completed, the FSM Tx block sets on the flag end_transfer, FSMTx and Tx (if required) are disabled, and FSM Core is activated again to check if the proc essor must change the state or remain in the same con figuration. After this evaluation, FSM Core sets on the flag end_core. Other important blocks of the RFID tag are a Ran dom Number Qenerator (RNG), for securing commu nications, and a mixed-signal circuitry for generic sensor signal acquisition. This latter consists of a Sig nal Conditioning block and a .successive Approxima tion Register (SAR) ADC. The former is used to adapt the sensory information to the signal range of the ADC. The ADC is clocked by the Timing Unit block through the signal clk_adc, and its operation is controlled by the FSM Tx block. Additionally, a flip-flop, not shown in Fig.2, has been included to synchronize a general baseband reset signal to the master clock. dala in nr-,.-----,r'nnrlnrvmfTIlYmnnr-,nr� data Olll_ ----, ,-- __________ ----' : II.IJU1fllfL =� cik Ix II T C a / � i � O � i · � : i � i i i 3 iO ; ii i � l....!!..- � O � Tllcal 0 0 pivol I s l....!!.._ masler elk elfyie enYlIlse_cllld _ � __ _____, ���;--;-;-c c;_;_-;-;-_;_;_;__;_;_; -  en Yliise JX -----f-��.I..l.\LU..JU-l..J...J..-L.LJ.-L.U-- enYliIseJrcl6 _ ___ + -!-!-:�-;-;-:I;-;-;-: ;-;-;--;-;--;-;-;-_;_;_; - - enYlilseJrc5 ----A- ...u..JU-l.J..J..Jf� L..L...L .J...J.. ......... -L.U -- master_elk JUUUliUUUUliU1J dala_in enyulse_cllld 1 ____ ----' enyulse_r.x I _____ � en Yliise Jrc5 I======----===::j Fig. 3: Experimental Results. IV. SIMULATION AND EXPERIMENTAL RESULTS Prior to silicon integration, the baseband processor was synthesized on a Xilinx XC3S1000 FPGA for debugging purposes. After an exhaustive test, the VHDL code was found fully functional. As an illustra tion, Fig.3 shows the experimental verification of a Query command transmission at 128 kbps, and a response transmission at 640 kbps, both the maximum frequency allowed in the forward and backward link, respectively. The scopes were captured using the logic analyser Agilent 16902B. The figure shows that the processor successfully calculates the timing constants implicated in the RFID communication. Fig.3 also illustrates the clock gating technique employed in the processor. The PIE Decoder is only enabled when the tag is receiving data and it is disabled otherwise. The FSM Tx works at maximum frequency in this particular example (a Query command) but it is only enabled during data transmission. The CRC-J6 and CRC-5 modules are enabled when the tag is decod ing the information sent by the reader and, when the processor detects that the received command do not use CRC-J6, corresponding block is disabled. Finally, it can be seen in the inset that the different clocks are delayed among themselves to lower the peaks of dynamic power. After FPGA validation, a silicon prototype has been designed in a 0.351lm CMOS technology. Its lay out is shown in FigA, where a bank of supply capaci tors and an ADC for sensor signal acquisition can be identified together with the processor and the EEP ROM. The chip occupies 7mm2 including pads. The ADC is an ultra low-power lO-bit SAR converter, intended for slow-varying signals. It is clocked by a signal 128 times slower than the master clock (the ADC internally divides elk_adc by 2), requires 12 347 Fig. 4: Layout of the RFIO baseband-processor. clock cycles to complete a conversion and only con sumes 150n W. Fig.5 shows an exemplary post-layout simulation of the prototype, in this case, illustrating the ADC operation when the tag receives a Write command. After an initial reset, the ADC makes five consecutive conversions which are transferred to the FSM Tx block at every adc _data ..Jeady pulse. Once the last conver sion is performed, the ADC enters in powerdown mode and the FSM Tx block averages the samples and stores the result in the EEPROM. The power consumption of the processor was esti mated using digital and analog models for the base band-processor and the ADC, respectively, assuming maximum bit-rates for the forward and backward links. Fig.6 illustrates the dissipation per block during a com munication flux which involves five consecutive com mands, including tag selection and memory reading. In total, the processor consumes less than 2.9IlA, assum ing worst-case timing conditions. Note that the Timing Unit, FSM Tx, TX and PIE Decoder blocks are the most power-demanding elements of the processor because they are clocked at the master frequency. Anyhow, the power consumption of the latter two blocks has been considerably reduced thanks to the applied clock gat ing techniques. Table I compares the achieved performance with other implementations in the literature. As can be seen, [6] achieves lower power consumption, however, it is clocked at a master frequency of 480kHz and it does not support the complete EPC Gen2 standard. Refer ences [10], [12] and fully comply with the standard but at a higher power consumption than in the proposed processor. Finally, [13] adds an AES cryptographic TABLE I. Comparison with previously published designs. Master Current CMOS Reference Frequency Consumption Technology [6] 480 KHz 1.471lA 0.35 11m [10] 2.56 MHz 6.401lA 0.18 11m [12] 1.28 MHz 5.1 IlA 0.35 11m [13] 2MHz 4.171lA 0.18 11m This work 1.92 MHz 2.9 ItA 0.35 11m Fig. 5: Communication between the Processor and the ADC 3,0000 .FSW Rx • Shift « Re9is.�r 2,5000 aCRe-IS :::L .CRC-:i c-.C"""'""" 0..- .Q 2,0000 OS"" li E :::J 1,5000 (J) c 0 • Others t) 1,0000 C o SyncFlipFlopl � • SyncFlipFlopO 0,5000 • FShI Core :::J o FShITx&TX <..) • PieDecoder 0,0000 • Timing Unit Fig. 6: Current consumption per block of the baseband-proces sor module to the tag but only supports the mandatory commands defmed by the standard and uses a CMOS technology with a smaller feature size. V. CONCLUSIONS In this work, a baseband processor for RFID appli cations targeting the EPC Gen2 protocol has been designed and implemented in a 0.35J.lm CMOS proc ess. The design was validated in a Xilinx Spartan3 FPGA, and the post-layout simulations show that the processor consumes less than 2.91.1A operating at max imum frequency allowed for the backward and forward link. 348 ACKNOWLEDGMENTS This work was supported by the Spanish Ministry of Education & Science under grants TEC2006-03022 and TEC2009-08447, and the Junta de Andalucia under grant TIC-02818. REFERENCES [1] K. Finkenzeller, RFID Handbook: Fundamentals and Applica tions in Contactless Smart Cards and Identification, 2nd ed. John Wiley & Sons Ltd, Chichester (UK), 2003. [2] D. Dolkin, The RF in RFID Passive-UHF -RFID in Practice. Newnes, Amsterdam (The Netherlands), 2008. [3] C. Ma, X. Wu, C. Zhang, and Z. Wang, "A low-power RF front-end of passive UHF RFID transponders." IEEE Asia Pacific Coif. Circuits Systems (APCCAS 2008), pp.73-76, Dec. 2008. [4] J.-P. Curty, M. Declercq, C. Dehollain, and N. Joeh!. Design and Optimization of Passive UHF RFID Systems. Springer, New York, 2007. [5] U. Karthaus, and M. Fischer, "Fully integrated passive UHF RFID transponder IC with 16.7-!lW minimum RF input power." IEEE J. Solid-State Circ., vo1.38, pp. 1602-1608, Oct. 2003. [6] I. Zalbide, J. Vicario, and I. Velez, "Power and energy optimiza tion of the digital core of a Gen2 long range full passive RFID sensor tag." 2008 Int. Con! on RFID, pp.l25-133, Apr. 2008. [7] EPC™ Radio-Frequency Identity Protocols Class-I Genera tion-2 UHF RFID Protocol for Communications at 860-960 MHz. Version 1.2. May 2008. [8] Impinj, Gen 2 Tag Clock Rate -What You Need To Know, 2005. [9] F. Cilek, K. Seemann, G. Holweg, and R. Weigel, "Impact of the Local Oscillator on Baseband Processing in RFID Transponder." Int. Symp. Signals, Systems and Electronics (ISSSE 2007), pp.23 1-234, 2007. [1O]Y. Roostaie, Y. Najafi, S. Mohammadi, and A. Foto wat-Ahmady, "A low power baseband processor for a dual mode UHF EPC Gen 2 RFID tag." Int. Coif. on Design and Technol ogy of Integrated Systems in Nanoscale Era (OTIS 2008), pp.l-5, Mar. 2008. [II]M. Mueller, A. Wortmann, S. Simon, M. Kugel, and T. Schoe nauer, "The impact of clock gating schemes on the power dissi pation of synthesizable register files." 2004 Int. Symp. Circuits and Systems (ISCAS 2004), vo!.2, pp. 609-612, May 2004. [12]H. Yan, H. Jianyun, L. Qiang, and M. Hao, "Design of low-power baseband-processor for RFID tag." Int. Symp. on Applications and the Internet (SAINT 2006), vol.4, pp. 63-66, Jan. 2006 . [13]A. Ricci, M. Grisanti, I. De Munari, and P. Ciampolini, "Design of a 2 !l W RFID baseband processor featuring an AES cryptog raphy primitive," 15th IEEE International Conference on Elec tronics, Circuits and Systems (ICECS 2008), pp. 376-379, Sep. 2008.