High-Speed Serial Interfaces for Event-Driven Neuromorphic Systems

High-Speed Se ial In e aces o E en -D i en Neu omo phic Sys ems M. Jabłoński1, T. Se ano-Go a edona2, and B. Lina es-Ba anco2 1AGH Uni e si y o Science and Technology, Depa men o Au oma ics and Bioenginee ing, K akow, Poland 2Ins i u o de Mic oelec ónica de Se illa, IMSE-CNM (CSIC and Uni . Se illa), SPAIN. be [email protected] Abs ac —Neu omo phic Enginee ing is he discipline o building senso y p ocessing a i icial sys ems inspi ed in he neu al p ocessing ound in li ing beings. Biological neu al b ains show massi e connec i i y among neu ons, which is no ealis ic o mimic using wi es wi hin silicon chips o be ween chips. Add ess- E en -Rep esen a ion is a echnology widely used among neu omo phic enginee s o emula e such massi e in e connec i i y by ime-mul iplexing as digi al channels by ansmi ing “Add ess E en s” be ween neu ons ha mimic he neu al spikes ansmi ed in biology. He e we show on-going p og ess on bi - se ial SATA AER in e -FPGA communica ions o mul i- ile scalable neu omo phic sys ems. I. INTRODUCTION Add ess E en Rep esen a ion (AER) is a communica ion echnique p oposed in he ea ly 90s [1], widely adop ed by neu omo phic enginee s. O iginally, he AER echnique would mul iplex in ime he spike ac i i y o silicon neu ons (in he ange o a ew Hz) in o a high-speed asynch onous hand-shaked mul i-bi pa allel digi al bus, ansmi ing each spike in a ew nano seconds. Since hen, AER based sys ems ha e g own in complexi y and esou ces, equi ing highe and highe communica ion bandwid hs and logic esou ces. Wi h he g ow h o neu omo phic sys ems, p ocessing and communica ion in as uc u es pe o mance equi emen s ha e inc eased. In AER-based sys ems he connec i i y is one o he main pe o mance bo lenecks. In e aces wi h pa allel digi al buses ha e limi ed bandwid h due o bus equency limi a ions, in e -bi ji e and skew, as well as bus leng h design es ic ions. On he o he hand, bi -se ial in e aces allow o se e al Giga bi s pe second speeds as well as adjus able e en bi leng hs. The wo-wi e 4-phase handshake p o ocol, highly ypical in pa allel AER links, can be subs i u ed by a low con ol mechanism when he e a e LVDS links in bo h di ec ions [2]. In his pape we show on-going p og ess on AER bi -se ial links be ween FPGAs, es ed a 1.5Gbps, capable o ansmi ing 32-bi Add ess E en s a a a e o up o 37.43Meps (mega e en s pe second). These links exploi pa allel- o-se ial anscei e s a ailable in Spa an-6 FPGAs. E en s a e gene a ed by a 32-bi bi -pa allel Tes Pa e n Gene a o (TPG) unning a a highe unco ela ed clock, which in e aces o he anscei e h ough a clock-domain-c ossing in e ace and high-speed synch onize s. The link has been es ed on a cus om PCB ha includes one Spa an-6 150 (wi h se ial anscei e s) FPGA and 4 bidi ec ional SATA connec o s, which we call he “AER-Node” PCB, and is in ended o g id assembly o many o hem. II. AER-NODE PCB The AER-Nodeboa d was designed wi h he aim o demons a e ha spike-p ocessing unde AER is easible and con enien o high speed ame- ee ision, il e ing, p ocessing and ac ua ion, using spikes om ision senso s o DC mo o s. Scalabili y is p o ided by ou SATA connec o s o bidi ec ional LVDS high-speed communica ions o enable a mesh o AER-Nodeboa ds [9]. Func ionali y can be inc eased wi h p ope daugh e boa ds, h ough wo pa allel 28-bi connec o s and wo 8-bi da a connec o s. (a) (b) Fig.1:(a) AER-Nodeboa d wi h 4 bidi ec ional SATA and 2 pa allel AER connec o s. (b) Tes assembly whe e all 4 bidi ec ional SATA links a e in e changing unco ela ed e en s in bo h di ec ions. Fo each bidi ec ional SATA link, Xilinx p o ides a pa allel/se ial anscei e w appe (called he e “GTP ile”), syn hesized by he Co e Gene a o u ili y. Fig. 2: “GTP ile” anscei e w appe p o ided by Xilinx, showing inpu and ou pu signals and ela ed clocks. Fig. 2 shows one such “GTP ile” oge he wi h i s inpu and ou pu signals and ela ed clocks. All GTP iles wi hin he FPGA use an ex e nal e y low ji e e e ence clock wi h di e en ial clock lines. These di e en ial clock lines eed in o special ab ic wi hin he FPGA, and once inside, a e ans o med om di e en ial o single ended be o e eeding he GTP ile. In ou AER-Node boa ds we ha e used ex e nal clocks o ei he 100MHz o 150MHz. The 100MHz e e ence clock can be used o LVDS da a a es o line = {1.0, 1.25, 2.0, 2.5}Gbps, while he 150Mhz one would p o ide line = {0.75, 1.5, 3.0}Gbps. O he e e ence equencies a e also possible. In he p esen wo k we used an AER-Node boa d wi h an ex e nal clock o 150MHz. The GTP ile includes a ansmi e side (TX) which eads 8n bi s o pa allel da a (DATA_ou ) and se ializes i ou o he LVDS_ou di e en ial line. When using 8b/10b encoding [11] an addi ional n-bi lag ‘cha isk’ signals whe he he co esponding 8-bi wo d should be ea ed as a egula da a o a comma command. The GTP ile also includes a ecei e side (RX) which pe o ms he opposi e. The GTP ile can be syn hesized o allow o di e en sizes o he pa allel DATA_ou /in wo d. The pa allel da a can ha e mul iple o 8 bi s, whe e hese mul iples can be ei he n = 1, 2, 4, o 8, hus allowing ‘DATA_ou /in’ o sizes 8, 16, 32, o 64 bi s. In his wo k we used always n = 4, which co esponds o 32-bi pa allel da a wo ds. The GTP ile in e nal PLLs ans o m he ex e nal e e ence clock in o he high speed line equency o LVDS bi -se ial ansmission. I also p o ides wo e e ence clocks o use ci cui y o equency and n . When using 8b/10b encoding line = 10n , and he 8n bi s o ‘DATA_ou /in’ and n bi s o ‘cha isk’ a e ead a he ising edges o clock . Fo example, i using a 150MHz ex e nal e e ence clock and se ing line = 1.5Gbps wi h n = 4, hen = 37.5MHz and 4 = 150MHz. Consequen ly, his would allow o a heo e ical maximum e en h oughpu o 37.5Meps (mega e en s pe second), being each e en o 32-bi s. As we will see in Sec ion IV, he maximum e en h oughpu is sligh ly less, which is due o he need o pe iodically ansmi commas o e en alignmen , clock co ec ion and low con ol. III. BIT-SERIAL BI-DIRECTIONAL AER LINK AER links be ween chips ha e adi ionally been pu ely asynch onous [1], using bi -pa allel po s oge he wi h wo lines o 4-phase handshaking. A se ial-wo d app oach was also p oposed [3], which would educe he numbe o pa allel bi s by hal . In he p esen app oach we a e using a clocked “GTP ile” ha in e aces on one side h ough LVDS o ano he FPGA “GTP ile”, and on he o he side o in-FPGA clocked use ci cui y. This clocked use ci cui y may un a he same equency he GTP ile is eading (TX) DATA_ou o p o iding (RX) DATA_in, o may un a a di e en equency (ei he co ela ed o and 4 , o o ally unco ela ed). Ul ima ely, he FPGA use ci cui y would in e ace o an ex e nal pa allel AER de ice (such like an AER e ina senso [4], [5]) which is ully asynch onous. He e we wan o explo e he case whe e he “GTP ile” has o connec , inside he FPGA, o a synch onous pa allel AER ci cui clocked a he maximum possible equency. Fo his, we syn hesized a “Tes Pa e n Gene a o ” (TPG) which we we e able o clock a 375MHz. This clock was gene a ed om a second X al on he PCB, which is unco ela ed o he low-ji e di e en ial one shown in Fig. 2. Fig. 3(a) illus a es he es app oach by showing a simpli ied diag am o he ci cui y connec ing o he TX pa o he “GTP ile” in Fig. 2. The e is a high speed Tes Pa e n Gene a o clocked a TPG = 375MHz, which p o ides a bi -pa allel DATA o 32-bi s h ough handshaking (Req and Ack). These handshaking signals go h ough high-speed synch onize s, each clocked by ei he TPG o 4 , as shown in he igu e. The TX FSM clocked a 4 in e aces wi h he “GTP ile” on one side, and on he o he side in e aces h ough a clock domain c ossing ci cui y wi h he high speed TPG. Since “GTP ile” eads and w i es da a acco ding o he ising edges o , he TX FSM will p o ide a signal “phase” o he ci cui s unning a equency 4 o signal when he ising edge o is app oaching. The TX FSM and clock domain c ossing ci cui y a e bo h clocked by he same clock 4 , and in e change in o ma ion abou hei in e nal s a us h ough signals “ alid” and “busy”. The “clock domain c ossing” ci cui in his case is a he simple and is gi en Fig. 3(b). Fig. 3: (a) In e acing ci cui y be ween high speed clocked Tes Pa e n Gene a o and GTP ile. (b) De ails o clock domain c ossing ci cui . IV. EXPERIMENTAL RESULTS In his Sec ion we p o ide ini ial expe imen al cha ac e iza ion esul s o he case o line = 1.5Gbps, 4 = 150MHz, and = 37.5MHz. A. In eg i y o LVDS Signals in FPGA BUILT-IN GTPs The quali y o bi -se ial ansmission using GTP in e aces embedded in FPGAs depends on se e al ac o s. The p ima y sou ce o e o s is he equency misma ch o he clocks in ol ed and hei ji e . F equency misma ch (usually wi hin a ew ens ppms) can be success ully esol ed by clock co ec ion echniques based on elas ic bu e s and a ailable wi hin he GTP iles [7], [8]. Physical p ope ies o he link, such as quali y o PCB aces, wi es and connec o s also impac signal in eg i y. A basic me ic ypically used o he e alua ion o bi - se ial in e aces is BER (Bi E o Ra e), which indica es he numbe o e oneous bi s ha ha e been ansmi ed du ing a es pe iod - he lowe he alue he be e he link. Fo his pu pose Xilinx p o ides dedica ed Tes Pa e n Gene a o s based on 7-bi PRBS (Pseudo Random Bi S eam), which can be gene a ed and e i ied inside a GTP anscei e i connec ed in loop-back mode. A me hod equen ly used o di ec ly measu e signal in eg i y is he Eye-Diag am analysis, which gi es mo e de ailed analog in o ma ion on ime and ol age ma gins o a pa icula link and i s se up (p e-emphasis, equaliza ion). I allows also de e mining he op imum sampling poin o a oid iola ion o ime- ol age ma gins embedded in o an Eye- Diag am. This me hod can howe e ha e he d awback ha he shape o he diag am can be a ec ed by a aching he sampling p obe, as his is an “in asi e” me hod. Fo example, Fig. 4 shows measu ed eye-diag ams a wo di e en sampling poin s. (a) (b) Fig. 4: Eye-Diag ams o LVDS link measu ed a di e en posi ions: (a) a FPGA RX inpu pins, (b) a in e -PCB SATA connec o a TX side. An al e na i e non-in asi e echnique o s udying physical channel p ope ies is he Ba h-Tube analysis. A Ba h-Tube cu e can be acqui ed by measu ing he BER alue o a ixed pe iod o ime and sweeping a ange o Sampling Poin alues. The esul is a ba h-shaped cu e ha usually yields e y low alues o BER (i.e. o 0.0) in he middle o he diag am, i.e. a ound 0.5UI (Uni Window). This co esponds o hal o he pe iod o he clock cycle, eco e ed om he ecei ed da a bi - s eam. T h e cen e o he egion whe e he BER cu e eaches 0.0 is he op imum Sampling Poin o he se up o a pa icula loop-back link (see Fig. 5). Plo s we e collec ed wi h he ChipScope ha dwa e debug in e ace and so wa e plug-in iBERT [8] o Spa an6 de ices. Besides he Sampling Poin , he ollowing pa ame e s also signi ican ly impac ansmission quali y: Vol age Swing, TX- P eemphasis, and RX-Equaliza ion. They should be adjus ed o gi e minimum BER a a pa icula speed o he link. Fig. 5 shows some sample Ba h-Tube diag ams o a ious RX- Equaliza ion pa ame e s. Fig. 6 shows he o e lap o he ba h g aph wi h he eye diag am. Fig. 5: Ba h-Tube diag am o loop-back connec ion a 1.5Gbps, TX- P eemphasis 2.5dB, Vol age Swing 929mV Fig. 6: Ba h-Tube cha embedded in o Uni -Window o he Eye-Diag am, o 1.5Gbps, TX-P eemphasis 2.5dB, ol age swing 929mV. B. E en E o Ra e (EER) Cha ac e iza ion Fo ou bi -se ial in e -FPGA link i is in e es ing o cha ac e ize he “E en E o Ra e” (EER), as his would include all possible e o sou ces, no only physical, bu also logical, as he p ope ope a ion o he low con ol p o ocol, he clock co ec ion scheme, o he mul i-by e e en alignmen [2]. In o de o es EER we used he TPG discussed in Sec ion II clocked a a e y high clock equency o TGP = 375MHz. The es se up in ol ing wo AER-Node PCBs (NB1 and NB2) is shown in Fig. 7. The pa allel-se ial anscei e link in each FPGA includes he “GTP ile”, he “TX block” (clocked a 4 , he as e use clock p o ided by “GTP ile”) and an “RX block” (clocked a , he slowe use clock p o ided by “GTP ile”). Besides he TPG, he e a e also wo “Synch onous Tes Pa e n Checke s” (STPC) clocked a equency . The STPC a he end o he chain in each FPGA es s EER o he whole ansmission chain, while he STPC be ween “GTP ile” and “TX block” es s clock domain c ossing issues. Fig. 7: Tes se up consis ing o wo AER-Node PCBs (NB1 and NB2), each wi h one bi -se ial link (“GTP ile”, “TX block” and “RX block”) oge he wi h a “Tes Pa e n Gene a o ” (TPG) clocked a e y high equency TPG = 375MHz and wo “Synch onous Tes Pa e n Checke s” (STPC) clocked a he slowe clock p o ided by “GTP ile” = 37.5MHz. Table I: Measu ed E o s, 32-bi E en Th oughpu and skew be ween pai s o AER-Node Boa ds on all 4 links In e nal STPC e o s EER RX Measu ed Th oughpu (eps) Clk skew (ppm) NB2 → NB1 0 0.0 37426439 -16.134 NB1 → NB2 0 0.0 37427647 16.133 NB4 → NB3 0 0.0 37428143 -29.409 NB3 → NB4 0 0.0 37425942 29.408 Long e m es s o se ial connec ions a 1.5Gbps we e pe o med concu en ly be ween wo AER-Node PCBs o each all 4 se ial links, as connec ed in Fig. 2(b), du ing 20 hou s o o e . No e o s we e de ec ed a none o he STPCs, as shown in Table I: columns “In e nal STPC e o s” and “EER” (which co esponds o he e o s coun ed a he STPC a he end o he pa hs). The h oughpu measu ed a he in e nal STPCs was always 37,427,043 eps, which co esponds exac ly o he expec ed TX side gene a ed e ec i e da a a e (excluding he COMMA densi y we we e using). Howe e , he measu ed h oughpu a ies sligh ly on he pa h ends STPCs (RX side), which a e he ones shown in Table I unde “RX Measu ed Th oughpu ”, because hese a e numbe s a e measu ed using he clocks a he des ina ion AER-Node boa d whose clock di e s by a ew ens o ppms. The measu ed di e ence be ween he TX and RX h oughpu s is gi en unde column “Clk skew” in ppms. CONCLUSIONS We ha e shown co ec ope a ion o bi -se ial AER links be ween cus om made PCBs o mul i- ile PCB assembly in e connec ed h ough 4 SATA links. Ini ial expe imen s ope a ing a 1.5Gbps a e epo ed. The links a e s imula ed h ough asynch onous handshaking echniques inside each FPGA by Tes Pa e n Gene a o s clocked by unco ela ed clocks. These unco ela ed clocks we e se a he maximum possible equency we we e able o se , 375MHz, in o de o es he channel a i s maximum possible h oughpu . Exhaus i e es s we e pe o med o e i y he co ec ope a ion, including eye diag am measu emen s, ba h- ube measu emen s, bi e o a es, and e en e o a es. ACKNOWLEDGMENTS This wo k has been suppo ed by Spanish g an s (wi h suppo om he Eu opean Regional De elopmen Fund) BIOSENSE (TEC2012-37868-C04- 02/01), Andalusian g an NANO-NEURO (TIC-6091), Polish g an om he Minis y o Science and Highe Educa ion o he Republic o Poland AGH UST no. 11.11.120.612, EU CHIST-ERA g an PNEUMA (PRI-PIMCHI-2011-0768), EU FP7 g an HBP (The Human B ain P ojec ) 604102, and H2020 EU g an ECOMODE 644096. REFERENCES [1] M. Si ilo i, “Wi ing conside a ions in analog VLSI sys ems wi h applica ion o ield-p og ammable ne wo ks,” Ph.D. Disse a ion, Compu a ion and Neu al Sys ems, Cali o nia Ins . Technol., Pasadena, CA, 1991. [2] T. Iakymchuk, A. Rosado, T. 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