A simple modulation approach for interfacing three-level Neutral-Point-Clamped converters to the grid

A Simple Modulation Approach for Interfacing Three-Level Neutral-Point-Clamped Converters to the Grid Antonio Ventosa-Cutillasa,∗, Pablo Montero-Robinaa, Federico Cuestaa, Francisco Gordilloa aDepartamento de Ingenier´ıa de Sistemas y Autom´atica. Escuela T´ecnica Superior de Ingenier´ıa. Universidad de Sevilla. Camino de los Descubrimientos, s/n. 41092 Sevilla Abstract Multilevel converters are nowadays an enabling key in the integration of electric power into the grid as they introduce less distortion and, thus, they are more compliant with the grid standards, among other benefits. A well-known topology is the three-level Neutral-Point-Clamped (NPC) whose control requires to deal with the capacitors voltage unbalance. This paper presents a modulation approach where the injection of a common component in the modulated voltage is studied in order to achieve such voltage balance. An optimization problem that, apart from the voltage balance, aims the lowest number of commutations and can be solved very efficiently with up to five computations of the cost function is formulated. The main advantages of the proposed modulation strategy are its simplicity and its flexibility, since it is also valid for unbalanced grid conditions and, with little added complexity, for low (and even zero) power factor conditions. Simulation results under unbalanced grid conditions are provided in order to show its validity under this scenario. The strategy is evaluated and compared with a space-vector-based approach in an experimental setup, yielding similar total harmonic current distortion (4.4%), a 30% reduction in the number of commutations, and better voltage balance performance for lower power factor conditions. Keywords: Synchronous rectifier application, neutral-point-clamped (NPC) converter, multilevel converter, grid-connected rectifier, voltage balancing, optimum zero-sequence voltage injection. 1. Introduction Electronic power converters are nowadays the most used devices for interfacing systems that absorb or generate energy with the grid. Thanks to their capability of transforming the characteristic of the electrical energy, whether if it is ac, dc or intermittent, ∗Corresponding author Email addresses: [email protected] (Antonio Ventosa-Cutillas ), [email protected] (Pablo Montero-Robina), [email protected] (Federico Cuesta), [email protected] (Francisco Gordillo) Preprint submitted to Energy February 28, 2020 they handle the power flow to fulfill the requirements of their applications. One of the5 typical uses comprehends dealing with the ac nature of the grid to either inject/absorb active power to/from a dc load/source or inject/absorb reactive power into the grid. No matter the aim, the quality of the handled power for grid-connected applications is crucial [1, 2]. In such applications, multilevel converters offer several advantages compared with the basic two-level configuration: lower current distortion and smaller voltage stress10 for the semiconductor devices among others [3]. These features make them very appealing for medium and high power applications where the voltage boundaries of the power devices are very limiting [4]. Among the broad choices of different multilevel converter topologies, three-level diode-clamped converter—also known as Neutral-Point-Clamped converter (NPC)—has been widely accepted in the industry and many applications have15 been developed for it [5–7]. However, the use of three-level NPC converters gives rise to a new control problem with respect to the two-level case: the dc-link capacitors voltage balance. This is an inherent feature in multilevel converters as more capacitors appear when the number of levels increases and their voltage might not remain the same under normal operating conditions. Therefore, it is crucial to consider how this unbalance can20 be compensated and to design a strategy to achieve the capacitors voltage equalisation. Considering the three-level NPC topology, the unbalance issue appears due to uneven currents that go through each capacitor, i.e. current entering/exiting the neutral point (NP) [5]. Avoiding the current going through the NP will, however, neglect the benefits of the three-level converter. That is why plenty of research have been carried out as the25 solution for this problem is not unique. A common approach is to separate the control system into two stages: the power flow control and the modulation. The first one is similar in multilevel and two-level topologies and defines some reference signals for the second stage such that the power flow is handled as desired. The second stage is in charge of commanding the switching devices in order to implement the previous control30 signals into the system, thus determining which capacitors are used. In this stage, there are remaining degrees of freedom that can be used for the capacitors voltage balance objective. In a grid-connected power converter, the modulation can be carrier-based pulse width modulation (CBPWM) [8] or space-vector pulse width modulation (SVPWM) [9], among35 others [10, 11]. Carrier-based approaches use one or several carrier signals to modulate the desired output signal of smaller frequency. The output signals to modulate are sampled at an specific rate—referred as switching frequency (fsw)—, and these samples are compared with the carrier signals—usually sawtooth or triangular shaped— whose value goes along its full range every period of fsw. Thus, the switching signals40 change in the intersections of these samples and the carrier. In this kind of modulation for three-level, three-wire grid-connected converters, there exists a common component called zero-sequence that can be added/subtracted to the three output signal samples simultaneously without affecting the modulated phase-to-phase voltage but allowing to modify the dc-link points that are connected. This fact is specially interesting for control-45 ling the capacitors that are charged/discharged [12]. Alternatively, SVPWM generally uses the nearest three-vector (NTV) strategy [7, 13] or the nearest three-virtual-vector (NTV2) one [14] to achieve modulation. The main idea is to consider simultaneously the output signals of the three phases by using several concatenated switching vectors, although, there exist redundant switching vectors that provide the same output voltage50 2 value but they use different levels. Therefore, the exploitation of this degree of freedom also makes possible to modify the connected points [6]. In summary, in order to deal with the modulation and the capacitors voltage balancing, CBPWM uses carriers and the zero-sequence component, while SVPWM uses concatenated switching vectors, including redundant ones [15]. In spite of being different techniques, several works in the55 literature have found equivalences between the zero-sequence injection and the redundant switching vectors use [16]. In early CBPWM approaches, the zero-sequence component was computed as a third harmonic signal that, in summary, entails the injection of a current into the NP that correct the unbalance [17]. This approach, however, requires to know the phase of the60 grid in addition to costly trigonometric computations. Nowadays, several approaches exist that considerably reduce the computational burden, solve the balancing issue and mitigate the low-frequency voltage oscillations of the NP [12, 16, 18–22]. Paper [20] summarizes the different kind of zero-sequence voltage injection control into: 1) Constant injection; 2) Constant charging injection; and 3) Maximum charging injection. Reference65 [19] presents two approaches based on the zero-sequence voltage injection, which exhibit their simplicity in terms of computational burden compared with other existing methods at the expense of increasing the number of commutations. From the NP current perspective, in [22], an analysis of the zero-sequence computation is made in order to obtain the relationship between it and the neutral current. In this way, a precise algorithm is70 proposed that computes the exact value of the zero-sequence to achieve the desired neutral current. However, such accuracy may not be necessary for a real application as the ripple at steady state that would result from not doing so could be negligible. Later, in [12], an analysis of the previous paper is developed resulting in a simpler flowchart with less computation burden. In [23], the equivalences among several neutral point current75 control approaches that achieve balancing with CBPWM and SVPWM are presented. However, none of the approaches presented in [12, 19, 22, 23] aims to reduce as much as possible the number of commutations at the same time that the voltage balance is achieved. There exists a controllability issue in the capacitors voltage balancing with zero-80 sequence injection when the operating conditions have a power factor different from unity. Depending on this value and the modulation index, the zero-sequence degree of freedom may not be enough to achieve voltage balancing at all time [18]. In this regard, [18] analyses the zero-sequence injection with an additional carrier in CBPWM such that this issue is overcome. The additional carrier introduces the use of another level within85 the switching period, which increases the total number of commutations. Regarding SVPWM, firstly, it is necessary to locate the voltage vector within the three-level Space Vector hexagon, i.e. the sector where it is located, in order to know which switching vectors, among the 27 available for NPC converters, should be used to modulate it. Then, these switching vectors are sequenced and theirs duty ratios are90 computed. The switching vector selection and sequencing, however, is not unique and plenty of criteria can be used [9, 14, 15, 24, 25]. Indeed, this is one of the advantages of SV-based approaches as many degrees of freedom are exhibited, although it is more complex to implement compared with CBPWM approaches [26] as several steps have to be taken into account: sector location, vectors selection, duty ratios computation,95 3 vectors sequencing and hardware implementation. Paper [9] presents a straightforward application of SVPWM to three-level NPC voltage and current inverters where these tasks are achieved. This application does not consider capacitors voltage balancing, though. In NPC converters, the switching vectors are classified as large, medium or short. The first ones do not create unbalance; the second ones inject one phase current into the NP; while100 the third ones come in pairs that produce the same effect on the system power flow control but inject the opposite current into the NP. Therefore, to achieve capacitors voltage balancing and without changing the switching vector positions, the redundant switching vectors can be used. In this way, [15] proposes a SVPWM with balancing capabilities by combining the medium vectors—that creates unbalances—with the redundant vectors.105 Alternatively, [25] presents a similar approach but aiming a reduction in the number of commutation. There exists a modification of SVPWM known as virtual space vector (VSV) [14]. It basically creates inherent switching vectors in the hexagon by combining fixed duty ratios of surrounding switching vectors. Thus, paper [24] modifies the VSV in order to achieve balancing capabilities by considering the redundant switching vectors in110 the creation of switching vectors. This approach will be referred as mVSV in this paper. As it was mentioned for CBPWM approaches, there exists an issue in the balancing when low power factor operating conditions are given. Using only the redundant switching vector degree of freedom to achieve balancing might be not enough depending on the modulation index and the power factor value [25]. Thus, none of the cited SVPWM115 approaches [9, 14, 15, 24, 25] presents an straight solution for this issue. Comparing SVPWM with CBPWM, carrier-based approaches are usually much easier to implement than those based on Space-Vector-Modulation (SVM). That is why in [16] an analysis of the SVPWM approach is presented in order to obtain a method based on CBPWM that provides the same results. Thus, an algorithm based on several checks and120 the knowledge of the sector where the voltage vector is located within the space vector hexagon is proposed such that the zero-sequence component is determined. In this paper, a CBPWM approach is considered where the zero-sequence determination is expressed as an optimization problem based on the minimization of a piecewiselinear function of one variable. In this way, the derivation of the zero-sequence computa-125 tion algorithm is simpler and easier to follow than the previous approaches. In contrast to [12, 14, 15, 19, 22–24], the minimum amount of commutations is achieved by keeping one phase at one level while the other two commute between two adjacent levels each. For this, it suffices to evaluate the proposed cost function just in the cases when one phase stays at one level and choose the minimum of them. Therefore, a simple opti-130 mal CBPWM approach, which has led to an international patent [27], that reduces the commutations and actively solves the unbalance is presented along with its justification. Regarding unbalanced grid conditions, the proposed strategy does not rely on any balanced-grid-voltage assumption. Therefore, the strategy may be suitable for this conditions keeping its simplicity compared with other CBPWM approaches [28].135 This paper also considers an enhancement of the base algorithm to improve the balancing capabilities. This is considered for those operation points where using the zerosequence injection with one phase fixed at one level during the sampling period and the other two phases at two adjacent levels each is not enough to achieve balancing at all time. Thus, one phase is allowed to use the three levels while the other two follow140 4 Figure 1. Schematic diagram of the three-phase three-level NPC rectifier. the same principle than the base algorithm. This modification requires to compute a new expression for the cost function that still keeps the property of being piece-wise linear. In contrast to [18], no additional carrier is required, and the enhancement is only applied until the capacitors voltage difference is small enough, reducing the number of commutations at steady-state.145 On the whole, the proposed method is easier to follow and simpler to implement than the SVM-based approaches [9, 14, 15, 24, 25] as no switching vector sequencing and large duty computations are required. The zero-sequence value and the duty ratios, for both the proposed algorithm and its enhancement, can be computed straightforwardly with no added difficulty in comparison with other CBPWM approaches [16, 18, 28], at150 the same time that both look for the lowest amount of commutations while achieving capacitors voltage balancing. Besides, simulation results show its capacitors voltage balancing validity under unbalanced grid voltages scenarios, due to its inherent lack of assumption of balanced grid voltages. Furthermore, the enhancement seeks covering those operation points with power factor lower than 1, where, at some instants, the base155 algorithm fails to achieve capacitors voltage balancing. The results are further validated by experiments under different operating conditions. The outline of the paper is as follows: Section 2 presents the converter dynamical model along with its system variables and components, and the required controllers corresponding to the stage previous to the modulation; Section 3 introduces the modu-160 lation stage where this paper focuses on and where the main contribution is presented, in addition to the advantages with respect to other methods; besides, an enhancement is introduced in order to improve the voltage balancing capabilities under lower power factor operating conditions; Section 4 depicts the experimental results and comparisons with mVSV [24]; and Section 5 draws some final conclusions.165 5 2. Model and Control of the System As it has been said before, this paper focuses on grid-connected three-phase, threelevel NPC converters working as rectifier with a resistive load in the dc side (Fig. 1). The system should handle the active power to match the one absorbed by the load such that the dc-side voltage is equal to its reference, which is specified by170 the user. The system should also track the specified reactive power according to the power factor conditions required by the application. With reference to Fig. 1, points {a, b, c}are the outputs of the converter whose voltage levels are set by switching signals {Si 1, Si 2}for i={a, b, c}. The grid voltages are denoted by vsi, for i={a, b, c}, while phase currents are ii. Inductive filters are considered {L1, L2, L3}175 whose inductances are assumed to have the same value L. Two capacitors constitute the dc-link side {C1, C2}with the same capacitance value Cand whose voltages are expressed by variables {vc1, vc2}. To express the unbalance, variable vdis defined as vc1−vc2. The three connection points of the dc-link are referred to as {p, o, n}and the resistive load R is connected in parallel to it. In this way, dc-link voltage vdc is equal to vc1+vc2.180 Based on [29], a model for this converter in αβγ coordinates—obtained by transforming the abc variables using the power-invariant Clarke transformation—is obtained. An averaged model over a switching period is considered by using duty ratios dkj for k={α, β, γ}and level j={p, o, n}—i.e. this duty ratios express the amount of time in a switching period that output of component kis connected to level j. In this way, Ldiα dt =vsα −(dαp −dαn)vdc 2−(dαp +dαn)vd 2(1) Ldiβ dt =vsβ −(dβp −dβn)vdc 2−(dβp +dβn)vd 2(2) Cdvdc dt = (dαp −dαn)iα+ (dβp −dβn)iβ−2vdc R(3) Cdvd dt = (dαp +dαn)iα+ (dβp +dβn)iβ. (4) The objective in the following sections will be to present a control algorithm which provides the values of dkj for k={α, β, γ}as a function of the measured variables vsi, ii, vc1 and vc2. Notice that dij in abc can be computed directly from dkj by applying the inverse power-invariant Clarke transformation. Notice also that duty ratios of component γdo not appear in (1)–(4), and therefore their values can be considered as degrees of freedom that can be used for other control objectives. Similarly, duty ratios dko do not appear in the model but they can be computed from the rest of duty ratios in abc frame according to the constraints X j={p,o,n} dij = 1, dij ∈[0,1]; i={a, b, c}.(5) To introduce the controller design, and inspired by (1)–(2), three control variables 6 are defined uα=dαp −dαn (6) uβ=dβp −dβn (7) uγ=dγp −dγn, (8) where uγis directly related to the homopolar component of the dij variables for i= {a, b, c}. By introducing these variables into the current dynamics (1)–(2) and assuming that variable vdis small enough to be neglected, a simplified model is obtained Ldiα dt =vsα −uα vdc 2(9) Ldiβ dt =vsβ −uβ vdc 2.(10) Notice that these equations recall the current dynamics of a simple two-level converter with uαand uβas control inputs. Moreover, variable uγdoes not appear in the current dynamics and therefore, it is left as a degree of freedom. At this point, the converter requires a control algorithm to handle the power taking into account the model dynamics. In this regard, two cascaded185 controllers are usually used [30]: an outer loop to compute the power required prto keep vdc towards its reference vr dc; and an inner faster loop in charge to drive the active and reactive powers p, q close to the previous reference and the desired reactive power qr, respectively. In spite of the fact that these stages are not the aim of this paper, the algorithms used in the simulation190 and experiments are presented here for the sake of completeness. 2.1. Dc-link Voltage Regulation Loop The total capacitors voltage of the dc-link (vdc) should reach its reference (vr dc) at steady state. To achieve so, a PI controller is used to compute the required amount of power (pr)[30], pr=kdc p(vr dc 2−v2 dc) + kdc iZt 0 (vr dc 2−v2 dc)dτ, (11) where {kdc p, kdc i}are control parameters to be tuned, which can be done using any approach existing on literature [30, 31]. After this, the references for the current control {ir α, ir β}are obtained by applying the instantaneous power theory to {pr, qr},195 where qris the user-defined reactive power reference. 2.2. Current Controller Once {ir α, ir β}are computed, a current controller stage is implemented such as to reduce the current tracking error {e iα,e iβ}={ir α−iα, ir β−iβ}as much as possible. In 7 this way, considering (9)-(10),a non-ideal proportional-resonant controller [32] tuned at the grid frequency is implemented. GP Rω(s) = kp+2krωcs s2+ 2ωcs+ω2(12) uα uβ=2 vdc −GP Rωge iα e iβ+vsα vsβ ,(13) where {kp, kr}are, respectively, the proportional and resonant control gains; ωcis the cut-off frequency of the low-pass filter implemented into the resonant part; ωis the resonant frequency—in this case, tuned at the grid one (ωg= 2πfgrid)—; and {vsα, vsβ}200 are the grid voltages in the αβγ reference frame. Bear in mind that this paper does not focus on this stage and that any other existing controller in the literature (e.g. [21, 33]) could be used instead as long as it provides the modulator with the values of uαand uβ. 3. Modulation Stage with Voltage Balance Capabilities205 This section presents the main contributions of this paper by providing an algorithm that computes the duty ratios dij such that the results of the current controller, namely {uα, uβ}, are implemented optimizing the number of commutations at the same time that the capacitors voltage are balanced. In the following subsections the base algorithm, its evaluation under unbalanced grid conditions and210 an enhancement to improve its balancing capabilites are shown. 3.1. Zero-sequence Component Computation As it has been said in the previous section, the output of the current controller is the value of uαand uβ. In order to convert them to abc coordinates there is a remaining degree of freedom, namely the homopolar component uγ. For simplicity, in the following,215 variable xis introduced as x˙= uγ/√3. In this way,   ua ub uc =r2 3   1 0 1 √2 −1 2 √3 2 1 √2 −1 2−√3 2 1 √2     uα uβ uγ =    q2 3uα+x −q1 6uα+1 √2uβ+x −q1 6uα−1 √2uβ+x     ˙=   ηa+x ηb+x ηc+x , (14) where variables ηa, ηb, ηchave been defined. These variables are known once uαand uβ are computed by the current controller. Notice that the maximum and minimum values for xare imposed by the constraint ui∈[−1,1] for i={a, b, c}—obtained from (5)220 and ui=dip −din—in conjunction with (14) resulting in x∈[−1−min(ηa, ηb, ηc),1− max(ηa, ηb, ηc)] ˙=[xmin, xmax]. Moreover, it can be seen that the feasibility condition xmin ≤xmax is equivalent to the requirement that vector (uα, uβ) is inside the SVM hexagon. Equation (14) can be interpreted with the help of Fig. 2 [34]. To put things in225 context, in the left graph of this figure a reference vector is shown in the usual space 8 vector hexagon. This reference vector corresponds to particular values of uα, uβthat, with the approach used in this paper, are given by (13). This reference vector moves as time moves on. In the same way, variables ηa, ηb, ηcimplicitly defined in (14) depend on time. In steady state, they describe a sinusoidal wave as shown in the central graph of230 Fig. 2 where t=t1corresponds to the same instant than the reference vector shown in the left graph. The right graph corresponds to this time instant. In it, the actual discrete levels for the three-level converter are represented by the values {−1,0,1}and the leaning lines depict the values of ua(x), ub(x), uc(x) as a function of the value of xto be chosen. The dashed vertical lines represent the boundaries xmin ≤x≤xmax. Notice also that235 for x= 0, ui=ηi. As time advances, these three lines move according to the movement of ηiin the central graph. One advantage of the approach can be spotted on the right graph where the degree of freedom associated with the homopolar component uγ(or, analogously x) is explicit, while it is not so evident in the space vector representation of the left graph. The black dots in the right graph will have an important relevance below.240 An animation of the time evolution of the three lines of the right graph of Fig. 2 and its relationship with ηa, ηband ηcand the space vector hexagon can be observed in the following link: http://grupo.us.es/tep102/lines_animation.mp4. Figure 2. Left graph: a reference vector in the Space Vector representation. Central graph: evolution of ηi(t), i =a, b, c; the vertical line corresponds to the same time instant t=t1than the left graph. Right graph: Representation of equation (14) at t=t1. Back to the capacitors voltage unbalance dynamic formulation (4), it can also be transformed to abc, resulting in245 Cdvd dt =ia(dap +dan) + ib(dbp +dbn) + ic(dcp +dcn).(15) 9 The proposed enhanced algorithm coincides with the base one when at least one value of fcost for the cases of Table 1 is negative. In the case when no points gets negative values, the enhancement is implemented to decrease it. The voltage balance365 capabilities are improved but at the cost of increasing the number of levels used and, therefore, the number of commutations and the switching losses. To avoid this, in contrast to [18], and considering that it is not necessary that vdgoes to zero but it suffices that it is small enough, a band of value ζis defined such that only when the value of |vd|is outside of it, the enhancement is applied. Consequently, the370 increased number of commutations occurs only during the transient period when vdis large and, thus, the base algorithm is used at steady state. A brief flow chart with the enhancement implementation is plotted in Fig. 8. Figure 8. Flow chart of the implementation of the algorithm enhancement 4. Experimental Verification This section aims to show the behaviour of the proposed algorithms in an experimental375 prototype of 12 kVA (Fig. 9). The circuit and control parameters of the converter are shown in Table 4, whereas the parameters that change along the experiment are given in Table 3 together with the time interval where they take place. The system consists of a grid-connected three-level converter controlled by a real-time target machine. The system power rate and all components have been designed according380 to the limits of the available infrastructure. The system acts as a rectifier capable of injecting or subtracting reactive power from the grid. Besides, the resistor connected to the dc-link uses a chopper circuit to demand different power rates which allows to emulate different resistance values. Considering this, the system is suitable for evaluating the algorithm proposed in this385 paper. Several operating points are emulated by modifying user-input variables: vr dc,qr; and circuit parameter: R. Unless otherwise stated, qris assumed to be zero to achieve unity power factor. Furthermore, to provide a comparison with other published approaches, the results of the experiments using a modified version of SVPWM approach with balancing390 capabilities [24] are also included in the figures— referred as modified virtual-space-vector (mVSV) from now on. In the experiments, both dc-link and current controllers are kept the same for the mVSV approach and the proposed ones. 16 Figure 9. Experimental prototype of the threelevel NPC rectifier. Table 3. Experiment Parameters Variation Time Interval R vr dc 0→0.8s120 Ω 700 V 0.8→1.5s60 Ω 700 V 1.5→2.2s60 Ω 700 →800 V 2.2→3.8s60 Ω 800 V 3.8→4.5s120 Ω 800 V The phase currents, instantaneous active power and switching states of phase aare plotted in Fig. 10 for both the base algorithm and the mVSV approach. It can be seen395 that the base algorithm shows a very similar behaviour compared with mVSV except for the number of commutations. Considering the results presented in Fig. 10, the base algorithm yields 265 commutations—number of 1-level transitions— per grid period, while the mVSV algorithm yields 375. Regarding the current distortion, Fig. 11 depicts the harmonic spectrum and the total400 harmonic distortion (THD) value for the currents of Fig. 10 for the base algorithm and the mVSV one. It can be seen that the proposed algorithms and the mVSV have very similar current distortion, therefore this proposal does not worsen the current quality Table 4. Experiment Parameters Parameter Value Parameter Value Grid frequency fgrid 50 Hz Sampling frequency (fs) 10 kHz Grid Voltage vsa, vsb, vsc 230 VRMS Switching frequency (fsw) 10 kHz Filter Inductance L2 mH Current control P gain kp5 Capacitance C3300 µF Current control R gain kr100 dc voltage control P gain kdc p0.05 dc voltage control I gain kdc i1 Enhancement parameter 0.1 Current control resonant cut-off frequency ωc1 rad/s Enhancement band ζ10 V 17 Figure 10. Experimental results at steady state with vdc = 800 Vand R= 60 Ω: (top) base algorithm, (bottom) mVSV algorithm: (left) three phase currents at steady state with vdc = 800 Vand R= 60 Ω; (center) evolution of system power (p) and power reference (pr) along different operating points; (right) switching state of phase aoutput when compared with other space-vector-based algorithm. In summary, at steady state the base algorithm presents less number of commutations, and thus it generates less405 losses, with similar current distortion when compared with the mVSV approach [24]. In terms of balancing capabilities, two experimental tests starting from an unbalanced situation with different operation points are considered as depicted in Fig. 12: a) unity power factor, and b) zero power factor. Figure 12a) shows a comparison of the balancing performance between the proposed algorithm and the mVSV, once the current controller410 is at steady state, with vdc = 700 V,R= 120 Ω and unity power factor. It can be seen that the balanced situation is achieved almost at the same time for both approaches, making the proposed algorithm suitable for balancing purposes when compared with other existing solution. On the other hand, in order to exhibit the relevance of the enhanced algorithm, Fig. 12b) is depicted for power factor equal to zero. It shows415 how, under this condition, the balancing capability of the base algorithm is slowered, increasing the time it takes to reach the balanced condition. Similarly, the mVSV algorithm presents much slower behaviour in terms of balancing capabilities. On the contrary, by implementing the enhanced algorithm, the balancing capability is considerably improved whenever |vd|> ζ. In this way, a suitable approach for balancing420 purposes under different operating points is proposed. Notice that at steady state, the base and the enhanced algorithm show similar behaviour as the differences between them 18 Figure 11. Experimental results: Harmonic spectrum of currents of phase ashown in Fig. 10 and corresponding THD value for the proposed algorithms and the mVSV one only appear when |vd|> ζ. Nevertheless, this modification entails an increment in the amount of commutations as depicted in Fig. 13. This increase is due to the occasional use of a third level during a transient period where |vd|> ζ and the operating conditions yield425 fcost >0 for the base algorithm. In this regard, during this transient stage, the enhanced algorithm yields 627 commutations per grid period according to Fig. 13. Nevertheless, this increased number only occurs during a short transient (less than 0.1 seconds in Fig. 12b) until variable vdis within the band |ζ|. 5. Concluding Remarks430 In this paper, the capacitors voltage balance for grid-connected three-level NPC converters has been addressed as an optimisation problem based on a cost function directly related to the balance dynamic equation. The proposed strategy minimizes the number of commutations at the same time that the voltage balance is tackled. Furthermore, given that the proposal only depends on435 the normalised output voltage, it can be implemented with any kind of current/power control. Besides, an enhancement in the algorithm assists in the capacitors voltage balancing when the previous approach could yield large balancing times. In this way, the capacitors voltage balance is improved for different operation points.440 The validity of the proposal has been tested in an experimental setup and compared with a modified version of virtual space vector modulation with voltage balance capabilities (mVSV). This comparison shows that the proposed approach and 19 Figure 12. Experimental results: Evolution of the capacitors voltage starting from an unbalanced situation: a) Base algorithm compared with mVSV with vdc = 700 Vand R= 120 Ω; b) Base algorithm compared with the enhanced one and mVSV with vdc = 700 V,R= inf Ω and ζ= 10 V. Figure 13. Experimental results: Switching state of phase aat steady state for the base algorithm with vdc = 800 Vand R= 120 Ω (left) and the enhanced one during a transient state where vd> ζ with vdc = 800 Vand R= inf Ω (right). its enhancement achieve similar balancing capabilities for a wider range of power factor values, with no deterioration of the current distortion (4.4%445 THD for mVSV and the proposed algorithm) but without the added diffi- 20 culty of implementing space vector modulation. Indeed, the implementation complexity is as simple as those of carrier-based. Besides, the number of commutations is reduced by 30% at steady-state in comparison with mVSV. Therefore, a valid approach for interfacing NPC rectifiers with the grid is presented. In450 addition, the extension of this approach to three-level NPC inverters is straightforward considering just the corresponding change of the current control and the direction of the currents. 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