Performance study of synthetic AER generation on CPUs for Real-Time Video based on Spikes

Abs ac — Add ess-E en -Rep esen a ion (AER) is a neu omo phic in e chip communica ion p o ocol ha allows o eal- ime i ual massi e connec i i y be ween huge numbe neu ons loca ed on di e en chips. When building mul i-chip mu i-laye ed AER sys ems i is absolu ely necessa y o ha e a compu e in e ace ha allows (a) o ead AER in e chip a ic in o he compu e and isualize i on sc een, and (b) con e con en ional ame-based ideo s eam in he compu e in o AER and injec i a some poin o he AER s uc u e. This is necessa y o es and debugging o complex AER sys ems. P e ious wo k p esen ed se e al so wa e me hods o con e ing digi al ames in o AER o ma . Those me hods we e no easible o eal- ime con e sion hose days because he p ocesso pe o mance was insu icien . Nowadays, Mul i-co e p ocesso a chi ec u es and cache hie a chies ha e e ol ed and he pe o mance is much be e han Pen ium 4 Mobile o hose yea s. In his pape we s udy ame- o-AER me hods o eal- ime ideo applica ions (40ms pe ame) using mode n p ocesso a chi ec u es, compile s, and p ocesso s o ien ed o s and-alone applica ions (mini-PC p ocesso s) Index Te ms—AER, neu o-inspi ed, mul ico e, HT- Technology, Co e Solo, Co e 2 Duo, Co e 2 Quad, A om, Via C7- M, eal- ime ision, spiking sys ems. I. INTRODUCTION ODAY, he e isn’ any ha dwa e compa able o he mos powe ul ‘compu e ’ in biology, he human b ain, wi h millions o ela i ely slow componen s (neu ons) wo king oge he in pa allel, wi h a o al powe consump ion o 20W pe day in a e age [1]. Fo ision p ocessing, he human b ain is much mo e powe ul, smalle and wi h e y low powe consump ion, compa ed o any compu e . P ima e b ains a e s uc u ed in laye s o neu ons, in which he neu ons in a laye connec o a e y la ge numbe (~104) o neu ons in he ollowing laye [2]. Many imes he connec i i y includes pa hs be ween non-consecu i e laye s, and e en eedback connec ions a e p esen . A i icial bio- inspi ed so wa e models based on such connec i i y models ha e o e whelmed he specialized li e a u e p esen ing many ways o pe o ming bio-inspi ed p ocessing sys ems ha Manusc ip ecei ed Ma ch 31, 2009. This wo k has been suppo ed by he ollowing p ojec s: Spanish Science and Educa ion Minis y Resea ch P ojec s TEC2006-11730-C03-02 (SAMANTA 2) and TIN2006-15617-C03-03 (AmbienNe ), Andalussian Council g an s P06-TIC-01417 (B ainSys em) and P06-TIC-02298. Au ho s a e wi h he Robo ics and Compu e s Technology g oup o he Uni e si y o Se ille, ETSI In o má ica, A . Reina Me cedes s/n, 41012, Se ille, SPAIN. Phone: +34954556145, Email: {mdominguez, pinigo, alina es, gaji, ci i , se i}@a c.us.es ou pe o m mo e con en ionally enginee ed machines [3][4]. Since hese models a e so wa e based, hey ope a e a ex emely low speeds, because o he massi e connec i i y hey emula e. Fo eal- ime solu ions di ec ha dwa e implemen a ions a e equi ed. Howe e , ha dwa e enginee s ace a e y s ong ba ie when ying o mimic he bio- inspi ed hie a chically laye ed s uc u e: he massi e connec i i y. In p esen day s a e-o - he-a e y la ge scale in eg a ed (VLSI) ci cui echnologies i is plausible o ab ica e on a single chip many housands (e en millions) o a i icial neu ons o simple p ocessing cells. Howe e , i is no iable o connec physically each o hem o e en a ew hund eds o o he neu ons. The p oblem is g ea e o mul i- chip mul i-laye hie a chically s uc u ed bio-inspi ed sys ems. AER is an incipien bio-inspi ed spike-based echnique capable o p o iding a ha dwa e solu ion o he in e -chip massi e connec i i y p oblem. Figu e 1 explains he p inciple behind he AER basics. The emi e chip con ains an a ay o cells (like, o example, a came a o a i icial e ina chip) whe e each pixel shows a con inuously a ying ime dependen s a e ha change wi h a slow ime cons an (in he o de o milliseconds). Each cell o pixel includes a local oscilla o ha gene a es digi al pulses o minimum wid h (a ew nanoseconds). The densi y o pulses is p opo ional o he s a e o in ensi y o he pixel. Each ime a pixel gene a es a pulse (which is called "e en "), i communica es wi h he a ay pe iphe y and a digi al wo d ep esen ing i s code o add ess is placed on he ex e nal in e - chip digi al bus ( he AER bus). Addi ional handshaking lines (Acknowledge and Reques ) a e also used o comple ing he asynch onous communica ion. Figu e 1. AER in e -chip communica ion scheme. Pe o mance s udy o syn he ic AER gene a ion on CPUs o Real-Time Video based on Spikes M.J. Domínguez-Mo ales, P. Iñigo-Blasco, A. Lina es-Ba anco, G. Jimenez, A.Ci i -Balcells, J.L. Se illano T In he ecei e chip he pulses a e di ec ed o he pixels o cells whose code o add ess was on he bus. This way, pixels wi h he same code o add ess in he emi e and ecei e chips will "see" he same pulse s eam. The ecei e cell in eg a es he pulses and econs uc s he o iginal low equency con inuous- ime wa e o m. Pixels ha a e mo e ac i e a e accessing he bus mo e equen ly han hose less ac i e. The e is a communi y o AER p o ocol use s o bio-inspi ed applica ions in ision and audi ion sys ems, as demons a ed by he success in he las yea s o he AER g oup a he Neu omo phic Enginee ing Wo kshop se ies [3]. One o he goals o his communi y is o build la ge mul i-chip and mul i- laye hie a chically s uc u ed sys ems capable o pe o ming complica ed a ay da a p ocessing in eal ime. The powe ul o hese sys ems can be used in compu e based sys ems unde co p ocessing. This pu pose s ongly depends on he a ailabili y o obus and e icien AER in e aces [10]. One such ool is a PCI-AER in e ace ha allows no only eading an AER s eam in o a compu e memo y and displaying i on sc een in eal- ime, bu also he opposi e: om images a ailable in he compu e 's memo y, gene a e a syn he ic AER s eam in a simila manne as would do a dedica ed VLSI AER emi e chip [6][7]. In his pape we e alua e ame- o-AER con e sion me hods p oposed in [8] o Real-Time ideo applica ions by compiling wi h ad anced echniques o mode n p ocesso s wi h powe ul a chi ec u al ad ances like mul i-co e and hype h eading, bu we also e alua e hem o mini-PC (8,9” lap ops) p ocesso s in o de o allow s and alone neu o- inspi ed applica ions, e.g. o mobile obo s. Nex sec ion b ie ly explains he so wa e me hods o con e ing digi al ames in o AER o ma in he compu e ’s memo y. Sec ion III e iews mode n powe ul p ocesso mic o-a chi ec u es and cu en mini-PC p ocesso s a chi ec u es. Then in sec ion IV we e alua e execu ion ime o he me hods o di e en pla o ms and compila ion echniques. In sec ion V we conclude. II. SOFTWARE SYNTHETIC AER GENERATION One can hink o many so wa e algo i hms o ans o m a bi map image (s o ed in a compu e ’s memo y) in o an AER s eam o pixel add esses [8][9]. In all o hem he equency o appea ance o he add ess o a gi en pixel mus be p opo ional o he in ensi y o ha pixel. No e ha he p ecise loca ion o he add ess pulses is no c i ical. The pulses can be sligh ly shi ed om hei nominal posi ions; he AER ecei e s will in eg a e hem o eco e he o iginal pixel wa e o m. Wha e e algo i hm is used, i will gene a e a ec o o add esses ha will be sen o an AER ecei e chip ia an AER bus. Le us call his ec o he “ ame ec o ”. The ame ec o has a ixed numbe o ime slo s o be illed wi h e en add esses. The numbe o ime slo s depends on he ime assigned o a ame ( o example T ame=40ms) and he ime equi ed o ansmi a single e en ( o example Tpulse=10ns). I we ha e an image o NxM pixels and each pixel can ha e a g ey le el alue om 0 o K, one possibili y is o place each pixel add ess in he ame ec o as many imes as he alue o i s in ensi y, and dis ibu e i wi h equidis an posi ions. In he wo s case (all pixels wi h maximum alue K), he ame ec o would be illed wi h NxMxK add esses. No e ha his numbe should be less han he o al numbe o ime slo s in he ame ec o . Depending on he o al in ensi y o he image he e will be mo e o less emp y slo s in he ame ec o T ame/Tpulse. Each algo i hm would implemen a pa icula way o dis ibu ing hese add ess e en s, and will equi e a ce ain ime. A. The Scan Me hod In his me hod a ame is scanned many imes. Fo each scan, e e y ime a non-ze o pixel is eached i s add ess is pu on he ame ec o in he i s a ailable slo , and he pixel alue is dec emen ed by one. I a pixel alue is ze o, a blank slo is le in he ame ec o . This me hod is gene a ing he pe iod a ay one by one, so execu ion ime should no depend on he numbe o e en s p oduced. Since he pe iod a ay is accessed in o de , cache memo ies policies and a chi ec u es should ake ad an ages. B. The Uni o m me hod In his me hod, he objec i e is o dis ibu e equidis an ly he e en s o one pixel along he ame ec o . The image is scanned pixel by pixel only once. Fo each pixel, he gene a ed pulses mus be dis ibu ed a equal dis ances. As he ame ec o is ge ing illed, he algo i hm may wan o place add esses in slo s ha a e al eady occupied. This si ua ion is called a 'collision'. In his case, we will pu he e en in he nea es emp y slo o he ame ec o . This me hod, appa en ly, will make mo e mis akes a he end o he p ocess han a he beginning and he execu ion ime g ows due o he collisions a he end o he p ocess, consuming mo e ime o be esol ed. Di iding i in o h eads co esponding o di e en pe iod a ay sec ions by he compile can op imize he algo i hm. Howe e since he ame ec o is a sha ed esou ce, collisions will dec ease he pe o mance because he p obabili y o in e e ence be ween di e en h eads g ows wi h he numbe o collisions. C. The Random me hod This me hod places he add ess e en s in he slo s ob ained by a pseudo- andom numbe gene a o based on Linea Feedback Shi Regis e s (LFSR) [12]. Due o he p ope ies o he LFSR used, each slo posi ion is gene a ed only once, excep posi ion ze o, and no collisions appea . I a pixel in he image has in ensi y p, hen he me hod will ake p alues om he pseudo- andom numbe gene a o and places he pixel add ess in he co esponding p slo s o he ame ec o . They will no be equidis an bu will appea along he comple e add ess sequence andomly. This me hod is as e han any o he Uni o m me hods. No e ha by using an LFSR i would be possible o ob ain wo e y close add esses in a ew calls. This can be a oided using an n-bi coun e o he mos signi ican bi s o he add ess. Figu e 2 ( op) shows he LFSR s uc u e wi h a 2-bi coun e o a 128x128 ame wi h 256 g ay le els. The so wa e has o call a and unc ion, whose esul is used o selec a posi ion in he ame ec o , bu i is also used by he same unc ion as an inpu pa ame e o wa an y he co ec pseudo- andom dis ibu ion o e en s. Thus, his unc ion supposes a c i ical sec ion o di iding he p ocess in o h eads. Fu he mo e, since he access o he ame ec o is andom, he me hod canno ex ac he bes esul s om cache memo y hie a chy. Figu e 2. Random me hod s uc u e on he op and Random-Squa e on he bo om. D. The Random-Squa e me hod Fo he Random me hod wi h a ixed size coun e , he e en dis ibu ion is poo o low ac i i y pixels. The dis ibu ion can be imp o ed subs i u ing he coun e by ano he LFSR. Fo a 128x128 ame wi h maximum g ay le el o 255, an 8-bi LFSR (LFSR-8) is used o selec ing 255 slices o 128x128 slo s, and ano he 14-bi LFSR (LFSR-14) selec s he posi ion inside he slice. The image is scanned only once. Fo each pixel a 14-bi numbe is gene a ed by he LFSR-14, which is used o selec a slo in a slice. Then, he LFSR-8 is called as many imes as he in ensi y le el o he pixel indica es, ha is used o selec ing he slices o place he e en s. Figu e 2 (bo om) shows he LFSR s uc u e used. This me hod has he same beha io as he p e ious one om he poin o iew o h ead di ision, bu o cache access, i is supposed o ob ain be e esul s since he ame ec o is di ided in o slices. E. The Random-Ha dwa e me hod The wo p e ious LFSR-based me hods a e e y a ac i e o a ha dwa e implemen a ion because o he simplici y and e iciency o he LFSR me hods. Howe e , in bo h cases he comple e ame ec o has o be gene a ed and s o ed be o e s a ing he ansmission. This me hod uses an LFSR o as many bi s as necessa y o gene a e NxMxK numbe s, as be o e. Fo example, i N=M=128 and K=256, hen 22-bi s a e needed. The 22-bi LFSR is called 222 imes, p o iding andom numbe s. Fo each numbe , a pixel is selec ed in he image using he log2(N)+log2(M) less signi ican bi s o he pseudo andom numbe . Wi h he log2(K) o he bi s, he algo i hm decides i he e en has o be sen o no . I he log2(K) mo e signi ican bi s ep esen a numbe la ge han he alue o he pixel, hen an e en is sen wi h he log2(N)+log2(M) less signi ican bi s o he pseudo andom numbe as he add ess. In he o he case, he pseudo andom numbe is igno ed and a pause equi alen o one e en is gene a ed. Consequen ly, he algo i hm gene a es he pseudo andom numbe s, and decides whe he o no he esul ing e en is sen in eal ime. The e o e, no pe iod is needed. F om he poin o iew o h eads ex ac ion and he cache op imiza ion, he ame ec o is accessed sequen ially, wha is a bene i o he cache hie a chy. Bu , as he me hod equi es a call o a andom unc ion ha always depends on i sel , he me hod canno be di ided in h eads. F. The Exhaus i e me hod This algo i hm also di ides he add ess e en sequence in o K slices o NxM posi ions o a ame o NxM pixels wi h a maximum g ay le el o K. Fo each slice (k), an e en o pixel (i,j) is sen on ime i he ollowing condi ion is asse ed: KPKPk jiji ≥+⋅ ,, mod)( and jMikMN =+⋅−+−⋅⋅ )1()1( whe e Pi,j is he in ensi y alue o he pixel (i,j). The Exhaus i e me hod ies o imp o e he Random-Squa e one by dis ibu ing he e en s o each pixel in equidis an slices. In his me hod, he ame ec o is accessed slice by slice. Since each slice is longe han he L1 cache, he me hod will no ex ac bene i s om i . In con as , di ision in o se e al h eads could be possible i he ame ec o access sequences suppo i . III. CPU ARCHITECTURES FOR SW REAL-TIME AER GENERATION In [9] hese AER so wa e me hods we e e alua ed in CPU pe o mance o one o he mos powe ul p ocesso o mobile applica ions, he In el Pen ium 4 Mobile (2002). In hose da es, he execu ion o hese so wa e me hods o con e ing digi al ideo ames in o AER o eal- ime spiking based ideo p ocessing was insu icien . The nex wo ks in his line [10] implemen ed he ame o AER con e sion in o ha dwa e by de eloping special ha dwa e in VHDL o FPGAs able o con e small esolu ion ame ideo in o AER (64x64). Nowadays, CPU’s a chi ec u es and pe o mance ha e e ol ed, so i is wo h o make a s udy o he pe o mance o hese me hods in cu en a chi ec u es wi h new p og amming echniques o aking ad an age o new a chi ec u al imp o emen s. In his sec ion we commen di e en cu en gene a ion CPU a chi ec u es. We ha e e alua ed he so wa e me hods desc ibed in he p e ious sec ion in hese p ocesso s o s udy i eal- ime ideo can be con e ed in o AER o s imula ing a ideo p ocessing AER sys em. Resul s a e p esen ed in nex sec ion. We ha e selec ed o his s udy wo mobile p ocesso s o small sys ems (In el A om and Via C7-M), and h ee mains eam p ocesso s (In el Co e Solo, In el Co e 2 Duo, and Co e 2 Quad) The In el Pen ium M p ocesso in oduced a powe -e icien mic o-a chi ec u e wi h balanced pe o mance, based on In el P6 mic o-a chi ec u e. In el Co e Solo, In el Co e Duo and o he s p ocesso s inco po a e enhanced Pen ium M p ocesso mic o-a chi ec u e. The In el Co e 2, In el Co e 2 Quad p ocesso and o he s a e based on he high-pe o mance and powe -e icien In el Co e mic o-a chi ec u e. On he o he side, o mobile applica ions he In el A om is based on he A om mic o-a chi ec u e and he Via C7-M has a simila mic o-a chi ec u e [10]. A. In el Pen ium 4M mic o-a chi ec u e. The mobile In el Pen ium 4-M is based on he In el(R) Ne Bu s (TM) Mic o-A chi ec u e, consis ing o : a 400 MHz p ocesso sys em bus, Hype Pipelined Technology, an Execu ion T ace Cache, Rapid Execu ion Engine, and S eaming SIMD ins uc ions (SSE2). I also includes a 512k L2 cache. I ope a es a low ol age, allowing i o consume less powe and uses he SpeedS ep echnology, which au oma ically swi ches be ween Maximum Pe o mance and Ba e y Op imized Modes based on he applica ion demand. B. Enhanced Pen ium M mic oa chi ec u e (Pen ium Co e Solo, Co e Duo) The pipeline o he In el Pen ium M (o iginal Cen ino) p ocesso mic o-a chi ec u e con ains h ee sec ions: in-o de issue on end, ou -o -o de supe scala execu ion co e and in- o de e i emen uni . I suppo s a high-speed sys em bus (up o 533 MHz) wi h 64-by e line size. I was designed o lowe powe consump ion. The e a e many a eas o he Pen ium M p ocesso mic o-a chi ec u e ha di e om he p e ious Ne Bu s mic o-a chi ec u e ( amily=F), bu Pen ium M is based on an e olu ion o he P6 mic oa chi ec u e used by Pen ium-III p ocesso s ( amily=6). The In el Pen ium M p ocesso uses a sho e pipeline dep h han Ne bu s ha enables high pe o mance and low powe consump ion. The e ch and decode uni includes a ha dwa e ins uc ion p e e che and h ee decode s ha enable pa allelism. I also p o ides a 32-KBy e ins uc ion cache ha s o es un-decoded bina y ins uc ions. The p e e che is designed o e ch e icien ly om an aligned 16-by e block. The h ee decode s decode ins uc ions and b eak hem down in o μops. In each clock cycle, he i s decode is capable o decoding an ins uc ion wi h ou o ewe μops. The emaining wo decode s each decode a one μop ins uc ion in each clock cycle. The on end can issue mul iple μops pe cycle, in o iginal p og am o de , o he ou -o -o de co e. In his sense, he Pen ium M mic o-a chi ec u e is a supe scala p ocesso able o manage up o 3 ins uc ions pe clock cycle. The In el Pen ium M p ocesso inco po a es sophis ica ed b anch p edic ion ha dwa e o suppo he ou -o -o de co e. The b anch p edic ion ha dwa e includes dynamic p edic ion, and b anch a ge bu e s. The p ocesso co e dynamically execu es μops independen o p og am o de . The co e is designed o acili a e pa allel execu ion by employing many bu e s, issue po s, and pa allel execu ion uni s. The ou -o - o de co e bu e s μops in a Rese a ion S a ion (RS) un il hei ope ands a e eady and esou ces a e a ailable. Each cycle, he co e may dispa ch up o i e μops h ough he issue po s. The e i emen uni in he Pen ium M p ocesso bu e s comple ed μops is he eo de bu e (ROB). The ROB upda es he a chi ec u al s a e in o de . Up o h ee μops may be e i ed pe cycle. MMX, SSE and SSE2 ins uc ion se s a e suppo ed o SIMD ins uc ions (single-ins uc ion mul iple-da a) ha enhance he pe o mance pa allelizing so wa e loops. In el Co e Solo and Co e Duo p ocesso s ha e an a chi ec u e simila o he Pen ium M, bu wi h enhancemen s o pe o mance and powe e iciency. These include: •In el Sma Cache. This second le el cache is sha ed be ween wo co es in an In el Co e Duo p ocesso o minimize bus a ic be ween wo co es accessing a single- copy o cached da a. I allows an In el Co e Solo p ocesso (o when one o he wo co es in an In el Co e Duo p ocesso is idle) o access i s ull capaci y. •S eam SIMD Ex ensions 3. These ex ensions a e suppo ed in In el Co e Solo and In el Co e Duo p ocesso s. •Decode imp o emen . Imp o emen in decode and μop usion allows he on end o see mos ins uc ions as single μops. This inc eases he h oughpu o he h ee decode s in he on end. This a chi ec u e also decodes 3 ins uc ions pe cycle, including 3 SSE ins uc ions decoding pe cycle. In Pen ium 4-M a chi ec u e SSE ins uc ions canno be decoded by any o he h ee decode s. Now, SSE and SSE2 ins uc ions can be decoded in pa allel wi h one SSE3 ins uc ion. •Imp o ed execu ion co e. Th oughpu o SIMD ins uc ions is imp o ed and he ou -o -o de engine is mo e obus in handling sequences o equen ly-used ins uc ions. Enhanced in e nal bu e ing and p e e ch mechanisms also imp o e da a bandwid h o execu ion. •Powe -op imized bus. The sys em bus is op imized o powe e iciency; inc eased bus speed suppo s 667 MHz. •Da a P e e ch. In el Co e Solo and In el Co e Duo p ocesso s implemen imp o ed ha dwa e p e e ch mechanisms ha can look ahead and p e e ch da a in o L1 om L2. These p ocesso s also p o ide enhanced ha dwa e p e e che s simila o hose o he Pen ium M p ocesso . C. In el Co e mic o-a chi ec u e. In el Co e mic oa chi ec u e in oduces he ollowing ea u es ha enable high pe o mance and powe -e icien pe o mance o single- h eaded as well as mul i h eaded wo kloads: •In el® Wide Dynamic Execu ion enables each p ocesso co e o e ch, dispa ch, execu e wi h high bandwid hs and e i e up o ou ins uc ions pe cycle. Some ea u es o he a chi ec u e a e: ou een-s age pipeline, h ee a i hme ic logical uni s, ou decode s o decode up o ou ins uc ions pe cycle, mac o- usion and mic o- usion o imp o e on -end h oughpu , peak issue a e o dispa ching up o six μops pe cycle, peak e i emen bandwid h o up o ou μops pe cycle, ad anced b anch p edic ion and s ack poin e acke o imp o e e iciency o execu ing unc ion/p ocedu e en ies and exi s. •In el® Ad anced Sma Cache deli e s highe bandwid h om he second le el cache o he co e, op imal pe o mance and lexibili y o single- h eaded and mul i- h eaded applica ions. Fea u es include: op imized o mul ico e and single- h eaded execu ion en i onmen s, 256 bi in e nal da a pa h o imp o e bandwid h om L2 o i s -le el da a cache, uni ied, sha ed second-le el cache o 4 Mby e, 16 way (o 2 MBy e, 8 way). •In el® Sma Memo y Access p e e ches da a om memo y in esponse o da a access pa e ns and educes cache- miss exposu e o ou -o -o de execu ion. Fea u es include: ha dwa e p e e che s o educe e ec i e la ency o second- le el cache misses, memo y disambigua ion o imp o e e iciency o specula i e execu ion engine. •In el Ad anced Digi al Media Boos imp o es mos 128- bi SIMD ins uc ions wi h single-cycle h oughpu and loa ing-poin ope a ions. Fea u es include: single-cycle h oughpu o mos 128-bi SIMD ins uc ions (excep 128-bi shu le, pack, unpack ope a ions), up o eigh loa ing-poin ope a ions pe cycle, h ee issue po s a ailable o dispa ching SIMD ins uc ions o execu ion. D. Hype -Th eading Technology This echnology enables so wa e o ake ad an age o ask- le el, o h ead-le el pa allelism by p o iding mul iple logical p ocesso s wi hin a physical p ocesso package. The wo logical p ocesso s each ha e a comple e se o a chi ec u al egis e s while sha ing one single physical p ocesso 's esou ces. By main aining he a chi ec u e s a e o wo p ocesso s, an HT Technology capable p ocesso looks like wo p ocesso s o so wa e, including ope a ing sys em and applica ion code. Each logical p ocesso can execu e a so wa e h ead, allowing a maximum o wo so wa e h eads o execu e simul aneously on one physical p ocesso . The wo so wa e h eads execu e simul aneously, meaning ha in he same clock cycle an “add” ope a ion om logical p ocesso 0 and ano he “add” ope a ion and load om logical p ocesso 1 can be execu ed simul aneously by he execu ion engine. The po en ial pe o mance imp o emen o HT Technology is due o: •The ac ha ope a ing sys ems and use p og ams can schedule p ocesses o h eads o execu e simul aneously on he logical p ocesso s in each physical p ocesso • The abili y o use on-chip execu ion esou ces a a highe le el han when only a single h ead is consuming he execu ion esou ces; highe le el o esou ce u iliza ion can lead o highe sys em h oughpu E. Mul ico e p ocesso s. These p ocesso s enhance ha dwa e suppo o mul i h eading by p o iding wo p ocesso co es in each physical p ocesso package. In el Co e Duo p ocesso p o ides wo p ocesso co es in a physical package. The mul ico e opology o In el Co e 2 Duo p ocesso s is simila o hose o In el Co e Duo p ocesso , which p o ides wo logical p ocesso s in a physical package. Each logical p ocesso has a sepa a e execu ion co e (including i s -le el cache) and a sma second-le el cache. The second-le el cache is sha ed be ween wo logical p ocesso s and op imized o educe bus a ic when he same copy o cached da a is used by wo logical p ocesso s. The ull capaci y o he second-le el cache can be used by one logical p ocesso i he o he logical p ocesso is inac i e. The In el Co e 2 Quad p ocesso consis s o wo eplicas o he dual-co e modules. F. In el A om mic o-a chi ec u e. The key ea u es o In el A om p ocesso s include: •Enhanced In el SpeedS ep® Technology enables ope a ing sys em (OS) o p og am a p ocesso o ansi ion o lowe equency and/o ol age le els while execu ing a wo kload. •Suppo deep powe down echnology o educe s a ic powe consump ion by u ning o powe o cache and o he sub-sys ems in he p ocesso . •In el Hype -Th eading Technology p o ides wo logical p ocesso s o mul i asking and mul i- h eading wo kloads op imiza ion. •Suppo Single-Ins uc ion Mul iple-Da a ex ensions up o SSE3 and SSSE3. •Suppo o In el 64 and IA-32 a chi ec u e. A om mic o-a chi ec u e has a wo-issue wide, in-o de pipeline ha suppo s hype - h eading echnology. The in- o de pipeline di e s om ou -o -o de pipelines by ea ing an IA-32 ins uc ion wi h a memo y ope and as a single pipeline ope a ion ins ead o mul iple mic o-ope a ions. The on end consis s o a powe -op imized pipeline, including 32KB, 8-way se associa i e, i s -le el ins uc ion cache, b anch p edic ion uni s and ITLB, wo ins uc ion decode s, each can decode up o one ins uc ion pe cycle. I can deli e up o wo ins uc ions pe cycle o he ins uc ion queue o scheduling. The schedule can issue up o wo TABLE I: PROCESSOR ARCHITECTURE FEATURES P ocesso Mic o-a chi ec u e L1 and L2 Cache Pen ium 4M 1,7GHz Pen ium M, MMX, SSE, SSE2. One co e, One Th ead. 130nm. L1 T ace: 12Kuops, 8-way L1 Da a: 8KB, 4-way, 64B/line L2: 512KB, 8-way, 64B/line Pen ium Co e Solo 1,86GHz Enhanced Pen ium M, MMX, SSE, SSE2, SSE3, One Co e, One Th ead/co e, 65nm. L1 Ins uc: 32KB, 8-way, 64B/line L1 Da a: 32KB, 4-way, 64B/line L2: 2MB, 8-way, 64B/line Pen ium Dual- Co e Co e, MMX, SSE, SSE2, SSE3, SSSE3, EM64T, Two Co es, one Th ead/co e. 65nm L1 Ins uc: 2x32KB, 8-way, 64B/line L1 Da a: 2x32KB, 4-way, 64B/line L2: 1MB, 4-way, 64B/line Pen ium Co e 2 Duo Co e T7200, MMX, SSE, SSE2, SSE3, SSSE3, EM64T, Two Co es, one Th ead/co e. 65nm L1 Ins uc: 2x32KB, 8-way, 64B/line L1 Da a: 2x32KB, 8-way, 64B/line L2: 4MB, 16-way, 64B/line Pen ium Co e 2 Quad, 2,4GHz Co e Q6600, MMX, SSE, SSE2, SSE3, SSSE3, EM64T, Fou Co es, one Th ead/co e. 65nm L1 Ins uc: 4x32KB, 8-way, 64B/line L1 Da a: 4x32KB, 4-way, 64B/line L2: 4MB, 16-way, 64B/line In el A om N270, 1,6GHz A om, MMX, SSE, SSE2, SSE3, SSSE3, One Co es, Two Th eads/co e. 45nm L1 Ins uc: 32KB, 8-way, 64B/line L1 Da a: 24KB, 6-way, 64B/line L2: 512KB, 8-way, 64B/line VIA C7- M, 1,6GHz Ou -o -o de - execu ion, 16 s ages pipeline. One co e, one h ead a chi ec u e. MMX, SSE, SSE2, SSE3. One Co e, One Th ead/co e. 90nm L1 Ins uc: 64KB, 4-way, 64B/line L1 Da a: 64KB, 4-way, 64B/line L2: 128KB, 32-way, 64B/line ins uc ions pe cycle o he in ege o SIMD/FP execu ion clus e s ia wo issue po s. Each o he wo issue po s can dispa ch an ins uc ion pe cycle o he in ege clus e o he SIMD/FP clus e o execu e. The memo y execu ion sub-sys em (MEU) can suppo 48- bi linea add ess o In el 64 A chi ec u e, ei he 32-bi o 36- bi physical add essing modes. The MEU p o ides: 24KB i s le el da a cache, ha dwa e p e e ching o L1 da a cache, s o e- o wa ding suppo o in ege ope a ions, 8 w i e combining bu e s. The bus logic sub-sys em p o ides 512KB, 8-way se associa i e, uni ied L2 cache, ha dwa e p e e ching o L2 and in e ace logic o he on side bus. G. Via C7-M mic o-a chi ec u e. The VIA C7-M p ocesso akes ad an age o he six een pipeline s ages oge he wi h ad anced b anch p edic ion ha p edic s and ga he s da a needed o op imally un applica ions while sa ing CPU cycles and educing powe consump ion. This is complemen ed by an e iciency-enhanced 128KB ull- speed exclusi e L2 cache wi h 32-way associabili y o memo y op imiza ion and enhanced digi al media s eaming. To ensu e he VIA C7-M p ocesso is cons an ly supplied wi h da a, i in eg a es he VIA V4 bus o ope a ion o up o 800MHz o communica ion o sys em memo y, s o age, and pe iphe al de ices. O he pe o mance ea u es include suppo o SSE2 and SSE3 mul imedia ins uc ions as well as MMX ins uc ions, and a ull-speed Floa ing Poin Uni (FPU) ha ensu es pe o mance o digi al media applica ions. The inclusion o SSE2 is mos impo an because he C7-M e ains a simple, in- o de , scala pipeline. Wi hou an ou -o -o de , supe scala design, dense, high la ency FPU ins uc ion s eams languish as each ins uc ion blocks he p og ess o he nex one o se e al clock cycles. Al hough mixing in ege ins uc ions be ween each FPU ins uc ion can mi iga e his p oblem, his is ne e heless an Achilles’ heel o he C7-M p ocesso . IV. REAL-TIME VIDEO PERFORMANCE In his sec ion we p esen a pe o mance s udy o execu ion ime o me hods explained in sec ion 2, wi h a se o inpu images ha imply di e en cha ges in he AER bus. The ame- o-AER con e sion is done in Real-Time i he inpu ideo sequence suppo s 25 ps ( ames pe second) o mo e, which implies 40ms o less pe each ame. Thus he 40ms on ie has been ma ked in all he igu es. F ame- o-AER me hods ha e been execu ed in se e al p ocesso s, s a ing om he Pen ium 4 Mobile, used in [9], and in se e al mode n p ocesso s, based on supe scala a chi ec u es, wi h SIMD ex ensions, complex ins uc ion and wo-le el da a caches and, in some cases, mul i-co e and hype - h eading a chi ec u es. Finally, we ha e e alua ed mini-PC lap op p ocesso s o s and-alone iabili y. These a e he In el A om and he Via C7-M ha a e cu en ly compe ing o he mini-PCs ma ke . Since he ame- o-AER con e sion o Video applica ions in Real-Time is usually used o mobile obo s de eloped a ound neu o-inspi ed AER chips, a small and po able mini-PC seems o be he bes choice. Ins ead o using an example ideo, we ha e es ed he me hods by using andomly gene a ed images wi h a Gaussian his og am. These images ha e been gene a ed o imply di e en AER bus loads ( om 10 o 90%, 95, 97 and 99%). Figu e 3 shows used images. Le ’s call his se o images TIS. So wa e me hods ha e been codi ied in C++ using In el Pa allel s udio, wi h di e en compila ion s a egies o he p ocesso mic o-a chi ec u es. SIMD ex ension, mul i-co e and hype - h eading ha e been used o gene a e bina y execu able es . This so wa e es uns each me hod o di e en AER loads 25 imes, measu ing he ime consump ion jus o he execu ion o he me hod, a oiding any o he ins uc ion o eading iles, p epa ing he pe iod ec o , e c, e c. The minimum ime has been used o he g aphs shown in Figu e 4 o Figu e 6. This minimum ime is ob ained a e se e al i e a ions, which implies ha we ha e he cache hie a chy wi h use ul da a. Fo mobile p ocesso s, i implies also ha we ha e he highes clock a e. P ocesso a chi ec u es p esen ed in he p e ious sec ion di e in many ea u es (ins uc ions pe cycle, s a ic o dynamic scheduling, h eads pa alleliza ion). The mos impo an di e ence be ween hem is he memo y hie a chy (L1 and L2 cache). Mini-PC p ocesso s (A om and Via C7-M) a e based in simple pipeline a chi ec u es wi h s a ic scheduling, bu combined wi h mode n solu ions o enhance he pe o mance wi hou excessi e powe consump ion. On he o he hand, desk op p ocesso s analyzed in his wo k, exploi he mul i-co e and hype - h eading ea u es p esen nowadays in gene al pu pose mains eam p ocesso s. Me hods o ame o AER con e sion gene a e a 4Mb bu e wi h he e en s o one ame. Then a PC o an AER in e ace, like he PCI-AER, sends his bu e . In his wo k we ha e no aken in o accoun he possible limi a ions o he AER ools, hus he ideal assump ion has been made: he ime o send he 4 Mb bu e o e en s is lowe han he minimum ime equi ed o any me hod in con e ing one ame. Bu no all he me hods access he pe iod o he ame in he same way hus, om he poin o iew o he cache, each me hod implies di e en miss a es when accessing L1 and L2. Since hese caches ha e di e en pa ame e s (associabili y, capaci y, numbe and sha ing be ween co es, e c), i is also aluable o s udy he bes so wa e me hod in ime consump ion ega ding o di e en cache hie a chies. Figu e 4 ( op) shows he execu ion ime o TIS images in an In el Pen ium Co e 2 Quad p ocesso . I can be seen ha he Uni o m me hod eaches he bes execu ion ime, being possible o handle eal- ime ame o AER con e sion o any AER bus load. In con as , Figu e 4 (cen e ) shows he same execu ion ime o a mini-pc p ocesso , he A om. In his case, he Uni o m me hod has also he bes esul s, bu o eal- ime ideo applica ions (40 ms pe ame), no all me hods o all AER bus cha ges a e easible. These esul s a e equi alen o hose ob ained wi h he Pen ium 4 Mobile pla o m used in [9]. Figu e 4 (bo om) shows ha execu ion ime. Figu e 3. TIS gene a ed andomly o ha e Gaussian his og am. Resul ing images (10% load uppe le , 90% load lowe igh ). Focusing he s udy in he Uni o m me hod, which is bes o aking ad an age o cache hie a chies, we ha e execu ed his me hod in se e al p ocesso s. Figu e 5 shows a compa ison g aph. Mul i-co e p ocesso s on desk op compu e s p o ide he bes esul s, because hey can pe o m mo e ins uc ions pe cycle and u he mo e hey exploi in ege SIMD ins uc ions. F om he cache poin o iew, o one co e in mul i-co e p ocesso s, he Via C7-M p ocesso has he mos powe ul cache hie a chy wi h a 32-way L2 cache o 512KB. Thanks o his cache, while miss a e is low, he p ocesso ou pe o ms i s compe i o , he In el A om. Thus, o low AER bus loads, he Via C7-M p ocesso is as e , bu when miss a e g ows, he A om a chi ec u e ou pe o ms he Via C7-M. Fo mul i-co e p ocesso s an open s anda d (OpenMP) is a ailable o pa allelizing execu ion in o h eads o op imize he execu ion imes. OpenMP p o ides a use ul way o op imize o mul i- h ead and mul i-co e p ocesso s. The con enience comes a a cos ; OpenMP can ha e a high s a up cos , aking hund eds o housands o icks. Tha 's why OpenMP's e iciency depends hugely on he p og am size; he la ge a p og am is, he mo e speed can be ob ained. Ano he d awback comes om c i ical egions: a c i ical egion p o okes absence o pa allelism a his poin . Thus, o sho p og ams wi h high a e o c i ical egions, OpenMP doesn' op imize speed. Figu e 5 and Figu e 6 show he execu ion ime esul s o Uni o m and Random Ha dwa e me hod compa ing a bina y compiled wi h OpenMP di ec i es and wi hou hem. Uni o m is a h ead di ision o ien ed me hod, while Random Hw is no because he and unc ion is a c i ical sha ing esou ce be ween i e a ions. Fu he mo e, Uni o m bene i s om cache hie a chies. OpenMP di ec i es a e no inc easing he pe o mance due o i s o e head and he es ic ions o he me hods. V. CONCLUSION This pape has s udied mode n mic o-a chi ec u e p ocesso s o desk op (mul i-co e) and lap op (low powe , s a ic scheduling and cache hie a chy), o use hem in ame- o-AER con e sions based on p e iously p esen ed so wa e me hods. Se e al compile echniques ha e been applied o each mic o-a chi ec u e in o de o ob ain he bes execu ion ime esul s. Images selec ed o es ing he p ocesso s a e andomly gene a ed o ep esen di e en AER bus wo kloads wi h Gaussian his og ams. Uni o m me hod is known o be bes om he poin o iew o e en dis ibu ion in ime. P e ious wo k s a ed ha so wa e con e sion o ame o AER was no easible o eal- ime applica ions. This wo k demons a es ha cu en p ocesso s, wi h adequa e compila ion echniques can ex ac eal- ime ideo con e sion o desk op p ocesso s and o ne book p ocesso s o AER wo kloads bellow 80%, which is e y high o ac ual AER sys ems. REFERENCES [1] D ubach, Daniel. The B ain Explained. New Je sey: P en ice-Hall, 2000. [2] G. M. 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IEEE T ansac ion on Neu al Ne wo ks. May-2006. [9] A. Lina es-Ba anco, R. Senhadji-Na a o, I. Ga cía-Va gas, F. Gómez- Rod íguez, G. Jimenez and A. Ci i . “Syn he ic Gene a ion o Add ess- E en o Real-Time Image P ocessing”. ETFA 2003, Lisbon, Sep embe . P oceedings, Vol. 2, pp. 462-467. [10] R. Paz, F. Gomez-Rod iguez, M. A. Rod iguez, A. Lina es-Ba anco, G. Jimenez, A. Ci i . Tes In as uc u e o Add ess-E en -Rep esen a ion Communica ions. IWANN 2005. LNCS 3512. pp 518-526. Sp inge . [11] In el® 64 and IA-32 A chi ec u es Op imiza ion Re e ence Manual. O de Numbe : 248966-017. Decembe 2008. h p://www.in el.com [12] Linea Feedback Shi Regis e V2.0. Xilinx Inc. Oc obe 4, 2001. h p://www.xilinx.com/ipcen e . Figu e 4. F ame- o-AER me hods execu ion imes o TIS images a In el Co e 2 Quad p ocesso ( op), In el A om (cen e ) and Pen ium 4 Mobile (bo om). Figu e 5. Uni o m me hod execu ion ime o TIS images a di e en p ocesso s. Figu e 6. Scan me hod execu ion ime o TIS images a di e en p ocesso s wi hou OpenMP di ec i es ( op) and wi h hem (bo om)