High-order cascade multibit /spl Sigma//spl Delta/ modulators for xDSL applications

ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland HIGH-ORDER CASCADE MULTIBIT CA MODULATORS FOR xDSL APPLICATIONS R. del Rio, E Medeiro, B. Pe'rez-VerdLi, and A. Rodriguez-Vrizquez Instituto de Microelectrdnica de Sevilla - CNM-CSIC Edificio CICA-CNM, C/Tarfia s/n, 41012- Sevilla, SPAIN Phone: +34 95 5056666. Fax: +34 95 5056686, E-mail: [email protected] ABSTRACT This paper explores the use of CA modulators for AD conversion in xDSL applications. Two high-order multibit architectures, the 2-I-lm0 modulator [7] and anovel2-1-1-lmb cascade (MASH), are proposed to achieve 14bit dynamic range @ 4.4MSls using low oversampling ratio. They show very low sensitivity to the intemal DAC linearity error, with no calibration required. Simulations show this performance can be achieved in presence of circuit imperfections, using submicron digital CMOS processes. 1. INTRODUCTION CAModulators (CAMs) have been successfully employed in the past for IOW-, medium-frequency AD conversion [l]. The use of oversampling and noise-shaping techniques in these converters avoids the need of extremely accurate analog building blocks, what makes them very suitable in the context of poor-analog-performance submicron CMOS processes. Such advantages have encouraged designers to widen the bandwidth of EA converters up to the data acquisition and communication ranges [2]-[SI, demanding high-res- olution and high-speed operation. Considering only quantization noise, the dynamic range DR of a CAM can be roughly estimated as follows: L IC J where L stands for the modulator order, M for its oversampling ratio, and B for the internal quantizer resolution in bits. In high-speed applications, increasing the signal bandwidth f, while maintaining an achievable sampling frequency f, implies the use of a moderate M, since M = fs/(2fx). In this scenario, the natural way to increase DR in order to cope with high-resolution specifications is to resort to high-order (increasing L), multibit (increasing B) CAMs. However, two important drawbacks arise: On the one hand, unlike 1st- and 2nd-order loops, high-order loops are not unconditionally stable. On the other, the linearity of the multibit CAM is ultimately limited by that of the multibit DAC in the feedback path. Both problems have been partially overcome; actually, high-order ZAMs have been stabilized through several techniques [I]: i.e., proper choice of the scaling factors, use of multipath feedforward structures, or resetting of the internal variables if unstable operation is detected. On the other hand, a common strategy to palliate the strong dependence on the internal DAC linearity is using calibration either in the analog or in the digital domain [I]. Nevertheless, cascade multibit architectures overcome these performing the high-order filtering by cascading low-order (1 st- and 2nd-) CAMs to guarantee unconditional stability, and using multibit quantization only at the last stage of the cascade to attenuate the influence of the DAC non-linearity [2]. This paper explores the use of such architectures to obtain [email protected]/s - specifications in the range of xDSL requirements. In Section 2, two cascade multibit architectures are considered: a 4th-order 3-stage cascade (with the structure 2-1-1) and a 5th-order 4-stage cascade (2-1 -1 -l), both including multibit quantization. Section 3 is dedicated to analyze the impact of circuit imperfections degrading the modulators performance. problems with neither calibration nor resetting required by: 2. CASCADE MULTIBIT XAMs Fig.1 shows a generic Lth-order N-stage cascade multibit CAM. It includes single-bit quantizers in all stages except the last one which has a multibit quantizer. In cascade CAMs, the quantization error induced in each stage is remodulated by the following one in the cascade. Once in the digital domain, by properly combining the outputs of the stages, it is possible to cancel out the quantization error in all stages except that in the last one, which appears at the modulator output attenuated by a shaping function of order equal to the summation of the order of all stages. Thus, ideally, the following is obtained for the Z-domain output: IL -1 W-L,) Y(z)=z-LX(z)+d(l -z- ) EN(Z)--d(l --z ) E,(z) (2) where X(z) is the Z-transform of the modulator input, d is an scalar larger than unity resulting from proper scaling of the transferred signal to prevent overloading of the stages, E$z) is the last-stage quantization error, E,(z) is the error induced in the last-stage DAC, Fig. 1: Generic Lth-order N-stage cascade multibit CAM. (*) This work has been partially supported by the ESPRIT Project 29261 MIXMODEST, and the CICYT Project TIC 97-0580 0-7803-5482-6/99/$10.00 02000 IEEE 11-37 and L = L, + . . . + L,. Note that ED(z) is (L - L,)th -order shaped, what significantly relaxes the DAC linearity specifications, with neither correction nor calibration required. Several cascade multibit CAMS have been reported: a 3rd-order 2-1 cascade (2-lmb) [2], a 4th-order 2-2 cascade (2-2mb) [3], and a 4th-order 2-1-1 cascade (2-12mb) [7]. According to eq.(2), DAC-induced error is 2nd-order shaped in the first two modulators and 3rd-order shaped in the last one. Thus, while in the 2-lmb and 2-2mb architectures the in-band power of such error is attenuated by M5, it is attenuated by M7 in the 2-12mb. This considerably reduces the sensitivity of the latter to the DAC ZNL, simplifying therefore its design. Fig.2 illustrates the 2-12mb cascade CAM. A 5th-order 4-stage 2-1-1-1 cascade using multibit quantization in the last stage (2-13mb), Fig.3, has been developed as an extension of the former to one more order, while preserving its properties. Ideally, the following Z-domain output is obtained for both modulators: Digital HI(?) = z-' where it has been assumed that the relationships among digital and analog coefficients and the values of the digital filters H&z), k = 1, ,.., 6 are those in Table 1 and 2, respectively. Therefore, the in-band error power at both modulator outputs is Digital/Analog Analog _I d - 1 -- &?I' = g, 831 O- s,g,g, (4) where cri = [A/(28- 1)12/12 is the power of the last-stage quantization error (A stands for the last-stage quantizer full+ale) and cri represents the DAC-induced error power. Note that this error is attenuated by M9 in the 2-13mb. 2.1 Integrator weight optimization Whatever set of coefficients (integrator weights in Fig.2 and 3) fulfilling the relationships in Table 1 and 2 leads to the expressions in eq.(3). Nevertheless, the following considerations must be taken into account in actual implementations: The level of the signal transferred from one stage to the next in the cascade must be low enough to avoid overloading the latter. I * Cancellation Logic Fig. 2: 4th-order 2-1-1 cascade multibit CAM (2-12mb). ' Cancellation Logic Fig. 3: 5th-order 2-1-1-1 cascade multibit ZAM (2-13mb). TABLE 1: Digital transfer functions and relationships for the 2-1' ZAM. I Digital I Digital/Analog I Analog I H2(z) =(1 -z-1)2 d, = - g,' =2g,'g2 s,gzg3 U d2 = 0 g,' = s3"g4 H3(Z) = 2-1 TABLE 2: Digital transfer functions and relationships for the 2-1'' CAM. . I~_ , I 82' = 2g,'g, H,(z) = z-1 d, = 0 I The output swing required for the integrators, which depends on their weights as well as on the input level, must be physically achievable. In SC implementations this limit is determined by the supply voltages. Digital coefficients d, and d, , which amplify the last-stage quantization error in eq.(3), should be as small as possible. Additional considerations in order to simplify the design are: Digital coefficients should be 0, t1 or multiple of 2. Multibit quantizer gain must be such that the loop gain of the last stage equals unity. Moreover, it should not be too large in order 11-38 to simplify the design of the multibit quantizer. Table 3 presents good selections of the integrator weights of the 2-I2mb and 2-13mb, for which the output swing requirement is reduced to only the reference voltages. In addition, in both cases the last-stage quantization error is amplified only by 2, d, = d, = 2 in eq.(3). This means a systematic loss of resolution of 6dB (Ibit) respect to the ideal case given in eq.(l). However, this loss is small when compared to that caused by stabilization and non-linearity correction mechanisms used in other approaches [ 13. Another 5th-order multibit cascade we initially considered, a 2-2-lmb CAM, was discarded at this point because the set of coefficients required to avoid overloading lead to d, = 8 (3bit systematic loss). TABLE 3: Analog and digital coefficients in Fig.2 and 3. Shaded cells correspond to the 2-13,nb modulator These coefficients present two additional advantages: Because the largest weight in all three-weight integrators can be easily obtained as a combination of the others, an SC implementation will only require two-branch integrators. Note that only one branch is needed for the first integrator. The total number of unitary capacitors is only 16 for the 2-12mb and 19 for the 2-13mb modulator, smaller than in other cascade ZAMs - 29 unitaries in [5] and [8], and 44 in [6]. 3. CIRCUIT NON-IDEALITIES Except for the DAC-induced errors, the architectural study in Section 2 assumes ideal conditions. Nevertheless, circuit imperfections degrading the CAM performance must be taken into account in practice. These non-idealities can be grouped in two categories: those affecting the quantization noise transfer function, whose effect strongly depends on the architecture considered, for instance integrator leakage and weight mismatching, and those that can be modeled as an error source at the first integrator; such approximation is justified by the fact that the contribution of remaining integrators is attenuated by increasing powers of the oversampling ratio. This is the case of thermal noise, defective settling in integrators, etc. 3.1 Integrator leakage and weight mismatching The ideal study developed in Section 2 assumes that the relationships of Table 1 and 2 are fulfilled and that the transfer function of the integrators is exactly z-'/( 1 - t-l) . However, these assumptions are not valid in practice: On the one hand, actual values of integrator weights differ from nominal ones due to mismatch in capacitors ratios. On the other, the integrator transfer function above is modified by the finite DC-gain of the amplifiers. 0 1 2 3 4 5 81 s (a) B (bit) 2 3 4 5 B (bit) Fig. 4: Modulator resolution vs. last-quantizer resolution for: (a) 2-1 ,mb CAM and (b) 2- 1 3mb CAM. (A, = 2500, weight mismatch (r = 0.1 %, and DAC INL = 0.4% FS) Both non-idealities result in an incomplete cancellation of the quantization error of the former stages and degrade the modulator DR [9]. Analysis shows that the extra in-band error power due to these non-idealities is: where A, stands for the opamp DC-gain, refers to mismatching in weights g,, g,, g3and g,", and cr: = A2/12 is the quantization error power of a single-bit quantizer. Note that these extra error contributions can in practice mask those in eq.(4), since they are only attenuated by M3 and M5 . Fig.4 shows simulation results for the effective resolution of the 2-12mb and 2-1 3mb modulators when varying the last-stage quantizer resolution B, with M acting as a parameter (depicted over each curve). Note that curves saturate in the presence of these non-idealities, leading to a practical limit for the use of multibit quantization - grossly estimated by the thick solid line. Increasing B over this limit would not further improve the modulator DR. Nevertheless, resolutions below this limit arc enough to significantly relax the circuit requirements with respect to single-bit approaches. 3.2 Other circuits imperfections Different [M, B] pairs can be a priori selected from Fig.4 for the 2-I2mb and the 2-13mb modulators, in order to fulfil specifications of [email protected]/s. Nevertheless, as operation frequencies increase 11-39 in ZAMs, the defective settling of SC integrators becomes one of the dominant errors limiting the modulators performance. Thus, the final choice among possible [M, B] pairs must be done in practice considering the opamp dynamic requirements involved. Table 4 shows an estimation of the required opamp bandwidth (GBW) for the different [M, B] pairs obtaining >13bit for both modulators. M = 16, B = 4 for the 2-I2m6 modulator and M = 14, B = 3 for the 2-13mb are the less demanding pairs for 14bit resolution. Note that multibit quantization significantly relaxes the dynamic requirements with respect to a single-bit approach. For instance, a 2-12 modulator with single-bit quantization would require M = 22 to obtain 14bit resolution. This higher M would lead to an increase of -35% on the power consumption per opamp. TABLE 4: Estimated opamp GBWfor operation at 4.4MS/s. 2-1~~0 14 61.6 +I 0.5 0.5 0.1 25 20 0.2 68 20% 2.25 0.9 +1/%2’ 20 3 0.4%FS 86.4dB (14.1 bit) -91.5dB -95.5dB 102.4dB .IOl.ldB / The overall influence of circuit imperfections on the modulator performance has been evaluated using SDOF’T [9], a sizing tool for SC CAMS. This tool combines accurate analytical expressions for each error contribution and statistical optimization, what allows us to find optimized, non-oversized specifications for the building blocks. Table 5 summarizes the circuit requirements providing [email protected]/s for both architectures, taking into account the different error contributions (e.g., quantization and thermal noise, settling error, capacitor mismatching, finite opamp DC-gain). Fig.5 shows behavioral simulation results using ASIDES [9] for the signal-to-(noise+distortion) ratio SNDR of both modulators in the presence of the circuits imperfections in Table 5. The maximum SNDR, obtained for a -5dB input level, is 80.5dB for the 2-I2m6 and 79dB for the 2-13mb. The DR is 86dB and 84.5dB, respectively. These results present both architectures as good candidates to obtain high-resolution, high-speed operation in xDSL applications, with a moderate power consumption. In fact, with the explored modulators, DAC non-linearities up to 0.4%FS can be tolerated with moderate requirements for the building blocks. - Unit - Mllz \‘ pF pF 9’0 pprn/L 46 kQ dB \r-2 mA/\ nL4 v niV bit - - - - - 80 70 - 60 s 50 M e 9 40 ‘ 30 20 10 CONVERTER (Non-linearity (INL) 5 Iynamic range Input level (dB) Fig. 5: SNDR as a function of the input level. 0.4%FS 87.7dB TABLE 5: Modulator sizing results Unitary capacitor 0.5 Capacitor non-linearity _i Sigma [NTEGRATORS DC-gain 2 DC-gain non-linearity 5 Maximum output current Differential output swing :OMPARATORslHysteresiS 5 I 20 A/D/A ]Resolution I4 ’henna1 noise -95.9dB ncomplete settling noise -102.3dB *. Only third integrator needs +2V output swing 4. REFERENCES [I] S. R. Norsworthy, R. Schereier and G. C. Temes (Editors):: “Delta-Sigma Data Converters: Theory, Design and Simulation”, IEEE Press, 1996. [2] B. Brandt and B. A. Wooley: “A 50-MHz Multibit CA Modulator for 12-b 2-MHz AD Conversion”, IEEE J. ofSolirf-State, Circuits, vol. 26, pp. 1746-1756, Dec. 1991. [3] N. Tan and S. Eriksson: “Fourth-Order Two-Stage Delta-Sigma Modulator Using Both 1 Bit and Multibit Quantizers”, Eleci tronics Letters, vol. 29, pp. 937-938, May 1993. [4] G. M. Yin and W. Sansen: “A High-Frequency and High-Reso- lution Fourth-Order CA A/D Converter in BICMOS Technology”, in Proc. of European Solid-State Circuit Cont, pp. 1-4, Sept. 1993. [5] A. Marques, et al.: “A 15-b Resolution 2-MHz Nyquist Rate AZ ADC in a 1 -pm CMOS Technology”. IEEE J. of Soli&Stare Circuits, vol. 33, n. 7, pp. 1065-1075, July 1998. [6] A. Feldman, et al.: “A 13-Bit, 1.4-MSIs Sigma-Delta Modulator for RF Baseband Channel Applications”. IEEE J. of Solid-State Circuits, vol. 33, n. 10, pp. 1462-1469, Oct. 1998. [7] E Medeiro, et al.: “A 13-bit, 2.2-MS/s, 55-mW Multibit Cas: cade CA Modulator in CMOS 0.7-pm Single-Poly Techno$- ogy”. IEEE J. of Solid-State Circuits, vol. 34, n. 6, pp. 748-760, June 1999. [8] Y. Geerts, et al.: “A 3.3-V, 15-bit, Delta-Sigma ADC with aSignal Bandwidth of 1.1 MHz for ADSL Applications”. IEEE J. $ Solid-State Circuits, vol. 34, n. 7, pp. 927-936, July 1999. [9] .F. Medeiro, B. PCrez-Verdli and A. Rodriguez-Vizquez: “Top-Down Design of High-Performance Sigma-Delta Modulators”, Kluwer Academic Publishers, Boston, 1998. 11-40