A fuzzy controller using switched-capacitor techniques

AFUZZY CONTROLLER USING SWITCHED-CAPACITOR TECHNIQUES J. L. Hue as, S. Sánchez Solano, A. Ba iga, I. Ba u one Ins i u o de Mic oelec ónica de Se illa - Cen o Nacional de Mic oelec ónica A da. Reina Me cedes s/n, (Edi . CICA) E-41012, Se illa, Spain Second IEEE In e na ional Con e ence on Fuzzy Sys ems (FUZZ-IEEE’93) Vol. 1, pp. 516-520, San F ancisco - Cali o nia, Ma ch 28 - Ap il 1, 1993. © 1993 IEEE. Pe sonal use o his ma e ial is pe mi ed. Howe e , pe mission o ep in / epublish his ma e ial o ad e - ising o p omo ional pu poses o o c ea ing new collec i e wo ks o esale o edis ibu ion o se e s o lis s, o o euse any copy igh ed componen o his wo k in o he wo ks mus be ob ained om he IEEE. This ma e ial is p esen ed o ensu e imely dissemina ion o schola ly and echnical wo k. Copy igh and all igh s he ein a e e ained by au ho s o by o he copy igh holde s. All pe sons copying his in o ma ion a e expec ed o adhe e o he e ms and cons ain s in oked by each au ho ’s copy igh . In mos cases, hese wo ks may no be epos ed wi hou he explici pe - mission o he copy igh holde . Abs ac The use o Swi ched-Capaci o echniques o build a uzzy con olle is discussed in his con ibu ion. Using a sequen ial a chi ec u e, he equi ed building blocks a e in oduced and i s ealiza ion is desc ibed. The p oposed sys em can be conside ed as a s a ing poin o explo ing he u u e capabili ies o e ed by SC ne wo ks o he ha dwa e implemen a ions o uzzy sys ems. 1. INTRODUCTION Fuzzy logic, al hough in oduced many yea s ago [1], has no become un il ecen ly a p ac ical al e na i e o con en ional compu e s o pe o ming in e ence ope a ions. Many applica- ions claiming he use o uzzy concep s ha e ecen ly appea ed in he ma ke place om japanese companies, bu mos o hese p oduc s a e based on a so o so wa e simula ion o uzziness using small wo dleng h con en ional mic ocon olle s. Besides hese esul s ob ained om pu ely digi al app oaches, i has been ecognized [2, 3] he need o de eloping ac ual ci cui s pe o ming he basic ope a ions equi ed o a uzzy sys em o eally ake ad an age o he ull la o o he uzzy pa adigm. Since a ew yea s ago, a en ion is being paid o he de elopmen o ci cui implemen a ions o uzzy logic, because ac ual uzzy ci cui s migh be he only way o ex end he applicabili y o uzzy logic o mo e demanding applica ion a eas. Then, ha dwa e implemen a ions ha e become a c i ical issue o adop ing uzzy solu ions a a sys em le el. The expec ed gains in e ms o a ea educ ion, ope a ion speed (bo h a ci cui and sys- em le els), and unc ional lexibili y u n ou in e es ing o explo e he possibili ies o e ed by analog echniques, especially in hose echnologies ully compa ible wi h digi al ci cui s. Ana- log design echniques seem o be e y appealing o he imple- men a ion o uzzy ci cui s and sys ems. In pa icula , he e exis a well- ounded body o heo e ical knowledge and p ac ical expe- ience ela ed o linea (especially il e s) and nonlinea swi ched- capaci o (SC) ne wo ks ha can be applied o he ealiza ion o uzzy con olle s [4,5]. This communica ion add esses he design and implemen a- ion o a sequen ial mic ocon olle based on SC ci cui s. This is ca ied ou a wo le els: a chi ec u e, and cell design. A he i s le el, he bo lenecks o epo ed ci cui s a e conside ed. In pa - icula , we will ocus on Yamakawa’s [6] since, al hough his a chi ec u e is a alid solu ion in many p ac ical cases, i seems in e es ing o look o modi ica ions able o handle he design o sys ems wi h many ules in jus one chip. A way o do ha may be based on ading speed and in e connec ion complexi y by eso - ing o he use o a sampled da a app oach. An addi ional ad an- age o his app oach is he compa ibili y wi h sound analog echniques ha can help in he design o he de uzzi ie . The basic building blocks o he app oach will be discussed as well as hei use wi hin he mic ocon olle . This sys em is concei ed as a chip ha can be ope a ing embedded in o a s anda d mic op ocesso en i onmen . 2. SEQUENTIAL ARCHITECTURE DESCRIPTION An a chi ec u e is p oposed o deal wi h sys ems handling many ules. The new a chi ec u e employs essen ially he same basic blocks p oposed by Yamakawa, bu he numbe o ules pe chip can be signi ican ly inc eased, and bo h he uzzi ie and he de uzzi ie can be included in he same chip. An o e all iew o he new a chi ec u e is shown in Figu e 1, whe e i s main blocks a e de ailed. This a chi ec u e is an adap ed e sion o he one p oposed in [7] o a cu en -mode uzzy p ocesso . Essen ial o his echnique is he de ini ion o an ope a ion cycle (de ined in e ms o N cycles o a undamen al clock, Ck) whose du a ion will depend mainly on he p ecision we y o a ain and he numbe o ules we conside . Such ope a ion cycle will impose a limi a ion o he inpu signal bandwid h. Each Con ol Rule is implemen ed by an analog ROM, some Membe - ship Func ion Ci cui s (MFC) and MAX/MIN ga es. S a ed an ope a ion cycle, he analog ROM will p o ide e e y clock cycle one alue o ol age o unca ing he alues coming om he MFCs. Hence, he ROM pe o ms as a se ial Membe ship Func- ion Gene a o (MFG) ins ead o wo king in pa allel (as p oposed by Yamakawa). This means ha he M bus lines used by Yamakawa as a uzzy wo d a e eplaced by a single wi e ha ca - ies M successi e samples ep esen ing such a wo d. The ou pu s om e e y Con ol Rule a e p ocessed by a MAX ga e and ed he de uzzi ie , which implemen s a cen e o g a i y me hod. The i s s age o his consis s o wo i e a i e summe s p epa ing he nume a o and he denomina o o a disc e e di ide . A e N clock cycles he di ide will gi e he inal ou pu . Basically, we di ide an ope a ion cycle in o h ee phases. Phase 1 is de o ed o sampling and holding he inpu a iables as well as o p e-p ocessing hem ough he MFCs. Phase 2 is aimed o ca y ou he in e ence p ocess by pe o ming MIN-MAX ope - a ions on he inpu a iables and he MFG ou pu s. Finally, in phase 3 he de uzzi ying p ocess is pe o med. Fo he sake o cla i y we will call Nj he numbe o undamen al clock cycles equi ed o he j- h phase. In o de o unde s and he o e all s uc u e, we will gi e in wha ollows a unc ional desc ip ion o he blocks in Figu e 1, de ailing hei ci cui implemen a ion and es ima ing he alue o Nj a e e y ope a ion phase. A FUZZY CONTROLLER USING SWITCHED-CAPACITOR TECHNIQUES J. L. Hue as, S. Sánchez-Solano, A. Ba iga, I. Ba u one Dep . o Design o Analog Ci cui s. Cen o Nacional de Mic oelec ónica, Edi icio CICA, A da. Reina Me cedes s/n, 41012-Se illa (Spain) Key wo ds: uzzy logic, disc e e- ime echniques, SC ne wo ks, CMOS in eg a ed ci cui s. FSM B B X 1(s3+s4) 1s2 1s2 1s4 1 s1 2 2+1s3 mC C s1s2s3s4 om he Analog ROM2 om he Analog ROM1 Ou pu (b) mX Ou pu V1V2V3V4 m Ck (a) MFG MFC MIN MAX ∑ j Vj ∑ Vj ÷ Xi Xj Ck Ope a ion Cycle Z MIN Analog ROM (M elemen s) N1N2N3 MFC F om o he an eceden s (A) F om o he con ol ules (R) 3. BASIC MFC The basic elemen o uzzy logic is a one-inpu ope a o pe o ming a classi ica ion o i s inpu a iable acco ding o a gi en membe ship unc ion. Gene ally speaking, he unc ional ans o ma ion ca ied ou by his ope a o is a nonlinea mapping (called a pe enence unc ion), bu in mos common cases his ans o ma ion can be app oxima ed by a symme ic piecewise- linea unc ion o he shape shown in Figu e 2-a, whe e he ou pa ame e s equi ed o iden i y he b eakpoin s a e depic ed. To implemen any ans o ma ion o his o m, a possible solu ion is he ci cui in Figu e 2-b. The uppe pa o his ci cui pe o ms a piecewise-linea ans o ma ion unde he con ol o he lowe pa . The inpu a iable X is sampled and held sequen ially o be compa ed wi h ou ol age alues de ining he apezoid b eak- poin s. The analog ROM1 in Figu e 2-b p o ides such b eak- poin s. The esul s o he compa ison a e p ocessed by a Fini e Sequen ial Machine (FSM) ha con ols he swi ches o he uppe ci cui . The la e , depending on he esul s o ed by he FSM, ans o ms he inpu in acco dance wi h one o he i e pieces o i s piecewise-linea ans o ma ion. The Analog ROM2 supplies he equi ed coe icien s o his ans o ma ion. As shown by i s ope a ion desc ip ion, his ci cui is ac i e du ing phase 1 and mus hold i s ou pu alue whils phases 2 and 3. The o al ime in es ed by his ci cui o pe o m he desc ibed ope a ion is 4 cycles o ca ying ou he compa ison and 1 cycle o he nonlinea ans o ma ion, hus N1=5. A way o gene a e he ol ages ep esen ing he b eakpoin s is shown in Figu e 3-a [8]. Since cu en lowing ou o he ci cui o he compa a o is neglec ible, an almos ideal ope a ion can be assumed. The o m a ios o he di e en ansis o s will ix he compa ison ol ages. Since he ou pu ol ages a e dec easingly o de ed om op o bo om, a swi ching scheme successi ely add essing he di e en ou pu ol ages in inc easing o de is used. Typically, a claimed d awback o he ci cui a angemen in Figu e 3-a is i s dependence on he powe supply; howe e , since in ou case he discou se uni e se is ixed by he bias ol ages, his Fig. 1: P oposed a chi ec u e o a Swi ched-Capaci o uzzy con olle . Fig. 2: (a) Symme ic apezoid ep esen ing a membe ship unc- ion. (b) Ci cui schema ic o a MFC. is no a p oblem any mo e. Ano he solu ion o implemen a membe ship unc ion can be ob ained om he o me ci cui jus eplacing he lowe pa by ou compa a o s. A simple combina o ial logic con ols he swi ches so ha he membe ship alue is calcula ed in only one cycle and he ROM2 would no be needed. The ou b eakpoin s a e gi en in pa allel by an analog ROM simila o ha desc ibed, bu he coun e is no necessa y now. 4. RULE EVALUATION CIRCUITRY As was poin ed ou abo e, a good solu ion o a oid a la ge silicon a ea when many ules a e conside ed, is achie ed by he use o a se ial MFG. Like MFCs, MFGs usually exhibi some symme y, since hey gene a e membe ship unc ions o uzzy se s. The e o e, he numbe o membe ship alues o be p o ided can be educed so ha he a ea occupa ion is s ill smalle . The ci cui in Figu e 3-b has been used as he MFGs. The only di e ence wi h he ci cui o Figu e 3-a is due o he swi ch- ing scheme. Fo he o me a FSM mus s o e he o de in which he swi ches ha e o be closed. The e is a p ac ical limi o he numbe o ansis o s o be s acked up, oughly speaking his numbe is gi en by VDD/VT. In p ac ice, i is p e e able o de i e he di e en ol age le els om se e al ansis o poles. This is mo e lexible and a oids di icul ade-o s. Since he MFGs exhibi some symme y, hus educing he numbe o di e en ol age le els, he a ea occupa ion is no la ge. Besides he MFG, MAX and MIN mul i-inpu ope a o s a e equi ed. A ypical 4-inpu MIN ga e is shown in Figu e 4. In his igu e, he ou inpu s a e sequen ially compa ed wi h he ol age p e iously s o ed by capaci o C. When he s o ed ol age is highe han an inpu ol age, he la e eplaces he o me since he co esponding swi ch is ON. O he wise, he s o ed ol age does no change. Then, a e ou clock pulses we ha e he mini- mum o he ou inpu signals. Ei he inc easing he numbe o inpu s o ob aining he MAX unc ion is s aigh o wa d. Taking in o accoun i s iming, he i s le el o MIN (in gen- e al MAX-MIN) ope a o s will ake a numbe o clock cycles ha depends on he numbe o an eceden s wi hin e e y ule. Then, we mus wai o a ime equal o he slowes ope a ion, which is equi alen o say a numbe o cycles equal o he highes numbe o an eceden s in any ule. Fo he MFG ope a ion, a wo-inpu MIN is equi ed, which means only a compa ison and can be pe - o med in jus one cycle. Finally, o he las MAX s age, he ime du a ion is equal o he numbe o ules imes he clock cycle. Since hese wo-inpu MIN and mul iple-inpu MAX ope a ions ha e o be done o e e y elemen o he MFG: N2 = max(Aj) + M (1 + R) whe e Aj applies o he numbe o an eceden s wi hin he j- h ule, M is he numbe o elemen s in he MFG, and R is he num- be o ules. 5. DEFUZZIFIER The inal s age o he uzzy con olle is implemen ed by wo summe s ollowed by a SC di ide , as is illus a ed in he block diag am o Figu e 5-a. The ci cui in Figu e 5-b shows a ci - cui ealiza ion wi h a educed numbe o elemen s; e e y ime a Coun e Ck B B FSM Ck (a) (b) Fig. 3: (a) Analog ROM o he MFCs. (b) Analog ROM o he MFGs. C Ou pu FSM Ck V1 V2 V3 V4 Coun e Ck Rese Fig. 4: Fou -inpu MIN ope a o . (a) (b) Fig. 6: Al e na i e de uzzi ie wi h cascaded summe s: (a) Block diag am. (b) Ci cui schema ic. 2 1CD 12S1CD 2S1CD 1S1212(S1+CD) B B 2 21 21 2(S1+CD) 1(S1+CD) 1CD Vk Ou pu 2CD 1 12 1CD Vk (ΣVk) (ΣkVk) Σ ΣΣA=1 Ou pu MAX ou pu (Vk) is alida ed, wo pa ial sums (ΣVk and ΣkVk) a e s o ed in capaci o s C1 and C2, espec i ely. In hese capaci- o s, we a e inc emen ally adding he ol ages un il he las alue o a MFG is gene a ed and p ocessed. Then, a disc e e- ime di ide (as can be seen in Figu e 5) p o ides he inal sys em ou - pu . The coun e in Figu e 5-b is de o ed o con olling a capac- i o a ay which gi es he weigh k o he sum ΣkVk. This ype o a ays a e equen ly used in SC ci cui s bu we can elimina e i and sa e on a ea by using wo cascaded summe s as is shown in he block diag am o Figu e 6-a. Figu e 6-b illus a es he esul - ing ci cui . In any case, he ime equi ed o he summe ope a ion is 2 clock cycles o e e y MFG alue, bu since i can be done while he p e ious s age is p ocessing, his alue only accoun s o he las s ep. The di ide equi es D pulses o ope a e, which gi es o N3 a alue o N3 = D+2. 6. PIPELINING Because o he way we a e implemen ing he di e en blocks, once he las alue o a MFG cycle has been p oduced, we can s a a new ope a ion cycle (o e lapping phase 3 wi h phase 1 and phase 2). I means a educ ion on he o e all ope a ion cycle o D+2, he ope a ion cycle can be exp essed as: N = b + 1 + max(Aj) + M (R+1), whe e b is he numbe o b eakpoin s in he MFC (no mally 3 o 4). The main limi a ion in his a chi ec u e is due o he sequen- ial ope a ion o he MAX ci cui , which in oduces he ac o MR in he exp ession abo e. This is a consequence o ha ing used only one MAX block in he mic ocon olle in o de o minimize i s a ea. Howe e , i q MAX blocks a e used he pipelining can be inc eased, di iding he ac o MR by q. Hence, depending on he 2 1CD 12CR 2CR 1CRCD212(CR+CD) 212CRCD B B 2 21 21 2CD1 1CRCD 1(CR+CD) Vk Ou pu Coun e 2CD 1 12 1CRCD (a) (b) Fig. 5: (a) Block diag am o a de uzzi ie . (b) Ci cui schema ic. Σ Σ Vk (ΣVk) (ΣkVk)ΣA=1 Ou pu applica ions, a comp omise mus be done be ween he numbe o MAX blocks (a ea) and he logic in e ence speed. 7. CONCLUDING REMARKS In p inciple his a chi ec u e is slowe han a pa allel coun- e pa . Howe e , since he a ea equi ed o a pa allel implemen- a ion is eno mous (mainly because o he numbe o bus lines), solu ions epo ed a e based on connec ing se e al (o e en many) chips ins ead o a one-chip al e na i e. Then, he ex e nal in e - connec ion delays b ing o h a p oblem associa ed wi h highe delay ime as compa ed wi h he ideal implemen a ion in jus one chip. The aim o he p oposed app oach is o es ablish a ade-o be ween ope a ional speed and silicon a ea occupa ion, bu aking in o accoun he alue o ac ual delays when se e al chips mus be connec ed. Thus, we can sac i ice a pa o he in e nal speed ( h oughou a sequen ial ope a ion) o be su e ha many mo e ules can be implemen ed on-chip, his a oiding ex e nal connec- ions o he han I/O pins. On he o he hand, aking in o accoun ha SC ci cui s can ope a e a high ecuencies, he p oposed mic ocon olle can be eally compe i i e compa ed wi h digi al implemen a ions. In his sense, he main ad an age o ou sys em is i s abili y o deal wi h analog signals making possible he di ec p ocessing o membe - ship alues (wha esul s in he elimina ion o A/D, D/A con e - e s). REFERENCES [1] L. A. Zadeh. "Fuzzy Se s", In o m. and Con ol, 1965. [2] T. Yamakawa, T. Miki and F. Ueno, “The design and ab ica ion o he cu en mode uzzy logic semi-cus om IC in he s anda d CMOS IC echnology”, P oc. 15 h IEEE In . Symp. Mul iple-Valued Logic, pp. 76-82, May 1985. [3] T. Yamakawa and H. Kabuo, “A P og amable Fuzzi ie In eg a ed Ci cui : Syn hesis, Design and Fab ica ion”, Else ie Science Pub. Comp. Inc., 1988. [4] J. L. Hue as, A. Rod íguez-Vázquez, A. Rueda and L. O. Chua, “Nonlinea Swi ched-Capaci o s Ne wo ks: Basic P inciples and Piecewise-Linea Design”, IEEE T ans. Ci cui s and Sys ems, V. CAS-32, pp 305-319, 1985. [5] A. Rod íguez-Vázquez, J. L. Hue as, A. Rueda, B. Pé ez- Ve dú and L. O. Chua, “Chaos in Swi ched-Capaci o s: Disc e e Maps” P oc. o he IEEE Vol. 75, pp 1090-1107, 1987. [6] T. Yamakawa, “High-Speed Fuzzy Con olle Ha dwa e Sys em:The Mega FIPS Machine”, Else ie Science Pub. Comp. Inc., 1988. [7] J. L. Hue as, S. Sánchez-Solano, A. Ba iga, I. Ba u one, “Se ial A chi ec u e Fo Fuzzy Con olle s: Ha dwa e Implemen a ion Using Analog/ Digi al VLSI Techniques”, 2nd. In e na ional Con e ence on Fuzzy Logic and Neu al Ne wo ks, Iizuka, 1992. [8] R. G ego ian and G. C. Temes, “Analog MOS In eg a ed Ci cui s o Signal P ocessing”, Wiley-In e science Pub, 1986.