Controller design for a single-phase two-cell multilevel cascade H-bridge converter

Controller Design for a Single-Phase Two-Cell Multilevel Cascade H-Bridge Converter S. Vazquez; J.I. Leon; J.M. Carrasco; L.G. Franquelo; E. Galvan; J.A. Sanchez; E. Domínguez Avda. De los descubrimientos s/n; Escuela Superior de Ingenieros; University of Seville; Seville 41092; SPAIN Email: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected] Abstract- In this paper is studied the single-phase two-cell multilevel cascade H-bridge power converter connected to the grid, acting as a synchronous rectifier. The power exchange process between the cells of the converter and the grid is analyzed. Based on this analysis and on the power converter model the stages of the controller design process are shown. A new controller for the cascade power converter is proposed, achieving the regulation of each DC-Link capacitor voltage towards its reference. The proposed controller includes a repetitive scheme in the current tracking loop, providing low current harmonic content and almost unity power factor. Simulation results have been carried out in a 10 kVA single-phase two-cell multilevel cascade H-bridge power converter model to illustrate the good performance of the proposed controller. Index Terms— Multilevel converter, power quality, non-linear control. I. INTRODUCTION Multilevel cascade converters, also named cascaded H- bridge converters, were first presented in 1988 [1]. Since then they have been a focus of researchers because they present several advantages compared with other multilevel converter topologies in terms of modularity, simplicity and number of levels with minimum number of power semiconductors [2]-[4]. Different applications have been developed using the multilevel cascade converter: Synchronous rectifiers [5], renewable energy integration systems [6], inverters [7], Statcoms [8] and active filters [9]. For each application, specific control strategies have been designed, being the DC- Link voltages control the most important challenge in this power converter topology. The DC-Link voltages control problem is not a trivial issue in the cascaded multilevel topology. As in other multilevel converters, the voltages control task can be approached through modulation or as a part of the system controller. When the modulation is used to control the output voltages, the redundant output states of the converter are used. In [10] this fact is used to regulate the outputs voltages to the same reference value. When the control approach is used, a specific control has to be designed to carry out the voltages control task. Due to this multiple signals are needed, one for each H- bridge, making the controller design more complex. However the advantage is that the output voltage references can be set independently. Several strategies to achieve the voltage balance can be found in the literature such as a passivity control strategy [11], non-linear control strategy [12], and strategies based on PI controllers [13]. In this paper the controller approach will be considered. To develop the controller design the power exchange process between the cells of the cascade converter and the grid is analyzed. From this analysis, the power flow limits as a function of the output voltage values will be pointed out, and finally the controller expression is derived. II. SYSTEM DESCRIPTION A single-phase two-cell multilevel cascade H-bridge power converter (CHB) is depicted in Fig. 1. The system is connected to the grid through a smoothing inductor L, and it is assumed that pure resistive loads R1 and R2 are connected to each DC- Link capacitor C1 and C2 respectively. The system parameters and variables are described in TABLE I, where the continuous control signals d1 and d2, which represent the switching functions have been defined. 1 S 1 S 2 S 2 S 4 S 4 S 3 S 3 S Fig. 1 Single-phase two cell multilevel cascade H-Bridge converter TABLE I SYSTEM PARAMETERS Parameter Description L Inductance C1; C2 Capacitances R1; R2 Resistive loads is(t) Grid current vs(t) Grid voltage iR1; iR2 Load currents Vdc1; Vdc2 Capacitor voltages d1;d2 ò [−1, 1] Control signals The equations that describe the CHB behavior are well known and they have been reported in several previous works [14], these equations are m11dc1 vV =d (1) m22dc2 vV =d (2) s sm1m2 di vLvv dt =++ (3) 22 dc1dc1 m1s1 1 2 VV d viC dtR æö =+ ç÷ èø (4) 22 dc2dc2 m2s1 2 2 VV d viC dtR æö =+ ç÷ èø (5) In these equations the control signals vm1 and vm2 defined in (1) and (2) have been introduced. These signals represent the voltages that are modulated in each cell. The equation that represents the input current dynamic is (3) and the output capacitor DC voltages dynamics are (4) and (5). To analyze the controller design stages, the power exchange between the cells of a cascade converter and the grid has to be studied. For this purpose the power converter representation of Fig. 2 is used. In this representation the cells have been replaced by voltage sources with values equal to the instantaneous voltages modulated by the cells, vm1 and vm2 respectively. The active and reactive power consumed or injected by each cell depend on the shift angle between the current is, and the modulated voltage in the cell (vmi). This can be analyzed using the phasorial diagram of the cascade power converter represented in Fig. 3. Now the following assumptions are made: (i) The voltages vdc1 and vdc2 are lower than the peak value of vs (ii) Cell 1 and cell 2 consume active power, and no reactive power is drawn from the grid. Fig. 2 CHB representation through voltage sources Fig. 3 CHB phasorial diagram of voltages and current For a given power consumption p1 and p2 in each DC-Link, the theoretical reference voltages for each H-bridge can be determined. The total amount of active power that has to be drawn from the grid is T1212 ;0;0 ppppp =+>> (6) The necessary grid current and the associated inductor drop (vL) can be then calculated and therefore the voltage that should be modulated between the points ab of the converter can be determined. T ss 2 sRMS p iv v = (7) s L dt di vL= (8) absL vvv =- (9) The voltage vab is composed by the sum of the output voltage of the cells, vm1 and vm2. For this reason, the DC-Link capacitor voltage values are constraints that should be considered when the load is applied, because only certain phasors compositions are allowed. Fig. 4 shows the phasors of all voltages involved. The set of points that can be reached for a given DC-Link capacitor voltage values is represented using a market region. An example of valid point is shown in Fig. 4a. Any point outside of this region would make the system unstable because the reference voltage of one cell or both can not be modulated with the actual values of the DC-Link capacitor voltages as is shown in Fig. 4b. 1 > 0 ; 2>0 s s ab dc1 dc2 m1 m2 ds d s s ab dc1 dc2 m1 m2 ds d a b Fig. 4 Reference voltage between points ab. a) Solution inside the reachable region b) Solution outside the reachable region For a given total amount of power pT, the values of power that can be consumed in each cell can not be chosen freely. Fig. 5a and Fig. 5b show the minimum value of active power that should be consumed in cell 1 and cell 2 respectively, to maintain the system stability. Among the possible solutions, only those points where the active power consumed by each cell corresponds with p1 and p2 respectively are valid solutions for the system. For instance, from p1 it is possible to calculate the projection of vm1 over is as 1 m1p s RMS p vi = (10) 1 > 0 ; 2>0 s s ab dc1 dc2 m1p m2p ds d s s ab dc1 dc2 m1p m2p ds d a b Fig. 5 Minimum values of active power must be consumed by the cells for a consumed total amount of active power pT. a) Minimum value of p1. b) Minimum value of p2 This fact leads to calculate the value of the projection of vm2 over is, and to determine the possible points to obtain a valid solution. These points are located over the line orthogonal to vs placed a distance vm1p from the origin. The valid solutions are the points which simultaneously belong to that line and are inside the set of points that can be reached with the DC voltage values in cell 1 and 2. Fig. 6 shows the set of possible solutions for power consumption p1 and p2, which are located between the points MN. m1p m2p M N 1>0 ; 2>0 ds d ab s s dc1 dc2 Fig. 6 Set of possible solutions for p1 and p2 It is worth pointing out that there is not a single solution for the system. The only restriction is that the solution has to be located between points MN, and therefore there is one degree of freedom which can be used to optimize the converter behavior and design. Fig. 7 shows two possible solutions for the system. Both solutions lead to the same result drawing active power p1 and p2. The only difference is the reactive power value delivered or consumed by each cell. III. CONTROLLER DESIGN To design the controller two facts must be considered, the total voltage regulation and the voltages ratio. The total voltage regulation is related with the sum of the DC-link capacitor voltages, and the voltages ratio is defined as the ratio between the DC-link capacitor voltages of the cells of the converter, meaning for instance that if DC voltage ratio is k:1 in a twocell CHB, then vdc1=k·vdc2. 1 > 0 ; 2>0 s s ab dc1 dc2 m1p m2p m1 m2 ds d s s ab dc1 dc2 m1p m2p m1 m2 ds d a b Fig. 7 Two possible solutions to achieve the same active power consumption p1 and p2 in each cell respectively. For the control law design, it is assumed that the switching frequency is high enough to consider the control signal as a continuous signal. Due to this fact the averaged model of the system can be used to develop the controller. Also it is assumed that the current dynamic is faster than the voltage regulation and ratio dynamics of a CHB converter. Finally the control design is split in three stages: (i) Voltage regulation control loop, which ensures capacitor voltage regulation towards its reference. The output of this loop is the current reference. (ii) Current control loop, which ensures inductor current tracking towards its reference. The output of this controller is the control signal u=vm1+vm2. (iii) Voltage ratio control loop, which ensures capacitor voltage ratio towards its reference. The output of this controller are the control signals vm1 and vm2. The control objectives are: (i) Regulate the capacitor voltages to the desire values V* dc1 and V* dc2 (ii) Achieve inductor current with high quality harmonic content and maintain the power factor as close to unity as possible. A. Voltage regulation control loop The averaged part of equations (4) and (5) can be used to obtain the necessary input active power to regulate the DC- Link voltages. 2 dc1 1 2 dc2 2 2 2 V z V z = = (11) Introducing the variables z1 and z2, equations (4) and (5) are transformed in 11 11 1 2 dzz pC dtR =+ (12) 22 22 2 2 dzz pC dtR =+ (13) Equations (12) and (13) are well-known LTI systems, thus the values of p1 and p2 can be calculated through a PI controller as in [15], yielding to the following expressions p1 i1 111 s1 kk pzz ss =+ +t %% (14) p2 i2 222 s2 kk pzz ss =+ +t %% (15) Controllers (14) and (15) include a low pass filter in the proportional term to reduce the high frequency noise, the parameters kp1, t1, ki1, kp2, t2 and ki2 are design positive nonzero constants and the error and the references values are calculated as ( ) ( ) 1 2 * 111 * 222 2 * dc1 * 2 * dc2 * 2 2 zzz zzz V z V z =- =- = = % % (16) The total amount of active power that the voltage source should provide is the sum of p1 and p2, and then the current reference can be calculated as ( ) 12 * RMS RMS ** s RMS RMS pp iv v iiv + = = (17) B. Current control loop Equation (3) represents the inductor current dynamic, to simplify the control design process the control signal u is defined as m1m2 uvv =+ (18) Thus the inductor current dynamic is transformed in s s di vLu dt =+ (19) Equation (19) is equal than the current dynamic equation for the single-phase H-Bridge converter and the three-phase twolevel power converter. Several linear and non-linear controllers have been proposed to achieve the current tracking in those power converters, in [16]-[17] a repetitive control scheme is proposed for the current tracking process, and in this work the same solution is adopted. spcsrs 1 1 s s Ke uvkiki Ke p - w p - w æö -× ç÷ =+×+ ç÷ ç÷ +× èø %% (20) * sss iii =- % (21) The parameters kpc, kr and K are positive non-zero design constants. Equation (20) is the expression for the control signal u and (21) is the current error definition. In (20) the proportional term adds damping to the controller to ensure stability and the repetitive term represents an estimation of v* L. * * L s di vL dt = (22) C. Voltage ratio control loop As it is shown in section II, the voltage modulated by each cell (vmi) together with the grid current must provide the active power and the reactive power demanded by the cell. The active power demand is satisfied when the projection of vm1 and vm2 over is are defined respectively as s 1 m1p * RMS RMS v p vv i =× (23) s 2 m2p * RMS RMS v p vvi =× (24) Besides, to achieve unity power factor the reactive power delivered by the cells must be equal to the reactive power demanded by the smoothing inductor. In addition, to ensure current tracking (20) must be satisfied. To carry out all these constraints the reference voltages in each cell are defined as m1m1ppc1s1rs 1 1 s s Ke vvkikki Ke p - w p - w æö -× ç÷ =+×+ ç÷ ç÷ +× èø %% (25) m2m2ppc2s2rs 1 1 s s Ke vvkikki Ke p - w p - w æö -× ç÷ =+×+ ç÷ ç÷ +× èø %% (26) where the following restriction must be satisfied 12 1 kk += (27) pc1pc2pc kkk += (28) where the parameters kpc1, k pc2, k1 and k2 are positive nonzero design constants. The constans k1 and k2 represent how the reactive power is shared between the cells. IV. SIMULATION RESULTS In this section simulation results are shown in order to test the proposed controller using a prototype. For this purpose the single-phase two-cell multilevel cascade H-bridge power converter has been considered. The experiment consists of a load step from no-load to full load, including different capacitor voltages reference. To modulate the reference voltage a phase-shifted PWM strategy has been used. To assess the controller performance, measurements of DC-Link capacitor voltages, grid voltage and currents are represented. TABLE II shows the electrical parameters of the power converter, switching and sampling frequencies that have been used in the model. Fig. 8 shows the obtained results for the complete experiment period. The experiment has three steps. In the first step, the DC-Link capacitor voltage references are set to 200V in both cells. Once the reference is achieved, a load step is introduced connecting a 20W resistor in each DC-Link. TABLE II ELECTRICAL PARAMETERS OF THE SYSTEM Grid Voltage 230 V Grid frequency 50 Hz Smoothing inductance 1 mH DC-Link capacitor C1 4700 µF DC-Link capacitor C2 4700 µF Switching frequency 10 KHz Sampling frequency fm 10 kHz The second step is carried out when the steady state is reached, and then the DC-Link capacitor voltage reference of the cell 1 is set to 300V. Finally, the third step is introduced when cell 1 achieves its reference, in this moment the DC-Link capacitor voltage reference of cell 2 is set to 100V. As it can be seen in Fig. 8 the proposed control strategy is capable to regulate each DC-Link capacitor voltages to the desired values, and to control the grid current. From Fig. 9 and Fig. 10 it is demonstrated that the proposed controller has good performance in transient and steady state conditions when a load step is applied. When a reference DC voltage step is applied in any cell the same good behavior is obtained as is shown in Fig. 11 and Fig. 12. Fig. 9a shows the DC-Link capacitor voltages transient response when the loads are connected and the voltage references are 200V. Fig. 9b shows the corresponding grid current and voltage. Fig. 10a shows the DC-Link capacitor voltages in steady state. It can be noticed that the references are achieved, the 100 Hz ripple in the voltages is due to the active power consumption. Fig. 10b shows the grid voltage and current in steady state. It can be observed that the grid current has high quality and is almost in phase with the grid voltage. Fig. 11a shows the DC-Link capacitor voltages transient response when the reference for cell 1 is changed from 200V to 300V and the reference for cell 2 is maintained in 200V. It can be noticed that in a few grid cycles the reference is achieved, and the voltage in cell 2 is almost not affected by the reference change in cell 1. In Fig. 11b it can be observed that the grid current increases until the DC-Link capacitor voltage is stabilized in the new reference value. Fig. 12 shows similar result compared with Fig. 11 when the reference for the cell 2 is changed from 200V to 100V and the reference for the cell 1 is maintained in 300V. V. CONCLUSIONS In this paper a single-phase two-cell multilevel cascade H- bridge power converter connected to the grid, acting as a synchronous rectifier is studied. From the analysis of the power exchange process between the cells of the converter and the grid, it is demonstrated that for a given total active power consumption the active power sharing between the cells can not be chosen freely. The controller design stages are shown, and following these stages a controller is proposed, using in the current tracking loop a repetitive control scheme. Simulation results have been developed and it has been verified that the proposed controller provides DC-Link capacitor voltages regulation and ratio control. Besides the proposed repetitive scheme provides current with low harmonic content and also it is capable to achieve almost unity power factor, providing a very good performance of the overall system. Fig. 8 Curves for the complete experiment period. a) vdc1 and vdc2 b) is Fig. 9 Capacitor voltages and grid current transients with DC voltage references equal to 200V for both cells. a) vdc1 and vdc2 b) vs, and is Fig. 10 Capacitor voltages and grid current details in steady state, with DC voltage references equal to 200 V for both cells. a) vdc1 and vdc2 b) vs, and is Fig. 11 Capacitor voltages and grid current transients with DC voltage references equal to 300V for cell 1 and 200 V for cell 2. a) vdc1 and vdc2 b) vs, and is Fig. 12 Capacitor voltages and grid current transients with DC voltage references equal to 300V for cell 1 and 100 V for cell 2. a) vdc1 and vdc2 b) vs, and is ACKNOWLEDGMENT This work has been developed thanks to the financial support of Spanish Government within the researching project TEC2006-03863. REFERENCES [1] M. Marchesoni, M. Mazzucchelli and S. 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