A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

Citation: Palomeque-Mangut, D.; Rodríguez-Vázquez, Á.; Delgado-Restituto, M. A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process. Sensors 2022,22, 6429. https://doi.org/10.3390/s22176429 Academic Editor: Dimitrios A. Patikas Received: 20 June 2022 Accepted: 24 August 2022 Published: 26 August 2022 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). sensors Article A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process David Palomeque-Mangut * , Ángel Rodríguez-Vázquez and Manuel Delgado-Restituto * Seville Institute of Microelectronics (CSIC-US), 41092 Sevilla, Spain *Correspondence: [email protected] (D.P.-M.); [email protected] (M.D.-R.) Abstract: This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2V with 4 bits resolution. The solution was designed and fabricated in a standard 180nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34mm2 . Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current. Keywords: neural stimulator; neuromodulation; neural implant; high voltage compliance; DC-DC converter; charge pump; CMOS; stacked transistors; dynamic gate biasing 1. Introduction Neural implants for the treatment of disorders such as Parkinson’s disease, essential tremor, dystonia, epilepsy, chrohin pain, and others [ 1 – 4 ] generally comprise two main functionalities: neural stimulation and neural recording [ 5 , 6 ]. As an illustration, Figure 1 shows the simplified block diagram of a wirelessly powered neural implant that is being developed in our research team [ 7 – 9 ]. Besides the recording and stimulation modules, it also features a controller for closed-loop operation [ 5 , 10 , 11 ], and an inductive link based Wireless Power and Data Transfer (WPDT) unit for power delivery and information transfer to/from the implant [ 12 – 19 ]. This unit includes an AC/DC converter, a signal modulation/demodulation stage, and a power management unit to provide regulated biasing voltages to the circuit elements of the implant. An external headstage wirelessly connects the implanted device to a computer hub for data acquisition, system monitoring, and parameters configuration [ 20 ]. Photovoltaic cells and rechargeable batteries are considered for supplying the headstage [ 21 – 24 ]. Within this architecture, this paper focuses on the stimulation section. In most cases, neural stimulation uses current mode techniques to force a flow of charge through the extracellular fluid of some excitable nervous system tissue accessed with microelectrodes [ 5 , 6 ]. Electrical stimulation typically consists of as a series of biphasic current pulses. The amplitude and duration of both phases, called anodic and cathodic, are conveniently adjusted to result in an overall zero net charge in the tissue. Important factors in the design of neural stimulators are the characteristics of the electrode–tissue interface (ETI), which depends on the geometry and materials of the electrodes and can change throughout the life cycle of the implant, the physiological parameters of the tissue, and the degree of electrical contact at the stimulation zone [25]. Sensors 2022,22, 6429. https://doi.org/10.3390/s22176429 https://www.mdpi.com/journal/sensors Sensors 2022,22, 6429 2 of 17 Neuromodulator Core WPDT Neural Stimulator Closed-loop controller Neural Recorder AC-DC Power Power & Data Uplink data Downlink data Voltage regulator Skin/Air Neural tissue Demodulator & Modulator Demodulator & Modulator WPDT’s external unit SoC Power sources DC-DC Power Amplifier Solar cell Battery BLE transceiver Implanted sideExternal side Figure 1. Simplified block diagram of the wirelessly powered neural implant, including power sources, a Bluetooth Low-Energy (BLE) transceiver, Wireless Power and Data Transfer (WPDT) external and internal units, and neuromodulation System on Chip (SoC). The circuit presented in this work is drawn in red. With stimulation currents ranging in practice from a few tens of µA to a few mA and considering the wide range of ETI load impedances, the voltage compliance required by a neural stimulator can vary from a few volts to more than 10 V [ 26 – 29 ]. This requires programmable structures in which both the current-driving capabilities and supply voltage can be adjusted to minimize power losses at the stimulation node. This is particularly compelling in implanted devices that are supplied by remote powering techniques, as in the example of Figure 1. In this work, a high-compliance, programmable fully on-chip neural stimulator is proposed. Instead of using an HV CMOS node [ 30 , 31 ], the whole system is designed in a standard 1.8 V/3.3 V 0.18µm CMOS process to enable the implementation of a single SoC implant, along with other elements already designed in this technology [ 9 ]. To do so, circuit solutions are implemented to ensure voltage drops across devices are below breakdown limits, even with compliance voltages well above the technology’s nominal supply. Previous contributions have also addressed the design of a HV neural stimulator in a LV CMOS process [ 28 , 29 , 32 , 33 ]. However, these solutions present some drawbacks such as limited power supply range and moderate current mismatch [ 33 ], low efficiency [ 28 ], lack of control in the stimulation charge [ 32 ], and fixed power supply [ 29 ]. These aspects are addressed in this work, where the proposed neural stimulator can handle voltage supplies up to 4 × higher than the technology’s nominal supply and stimulation currents up to 2mA; the residual charge is below 0.12% for the whole stimulation range, achieving 48% power efficiency at a maximum stimulation current. The paper is organised as follows. In Section 2, the operation of a current-controlled biphasic stimulator is described, with emphasis on the analysis of the compliance voltage and power efficiency. The architecture, components, and operation modes of the proposed neural stimulator are described in Section 3. In Section 4, experimental results are presented and discussed. Finally, Section 5concludes the paper with some remarks. 2. Current-Mode Biphasic Stimulation: Compliance Voltage and Power Efficiency Figure 2a,b show the simplified schematics of a monopolar neural stimulator and a bipolar neural stimulator, respectively. They essentially work in two alternating phases. First, an anodic phase of Tan duration is established to inject charge immediately around the stimulation electrode A. Then, a cathodic phase of Tca duration is set to restore the charge balance in the tissue prior to the stimulation. This is done to prevent charge accumulations that can lead to the generation of toxic chemicals or the corrosion of the electrodes [ 25 ]. Hence, if Istim,an and Istim,ca are the currents flowing through the ETI during the anodic and cathodic phases, the charges Qan =RTan 0Istim,an dt and Qca =RTca 0Istim,ca dt , injected and extracted from the tissue, respectively, should have the same magnitude but a different sign. Generally, the stimulation currents during the anodic and cathodic phases may have different waveforms and a duration as long as |Qan|=|Qca| ; however, in this work we consider a typical case in which such currents are pulses of the same duration, Tan =Tca , and the same magnitude, |Istim,an|=|Istim,ca|=Idrv. Sensors 2022,22, 6429 3 of 17 Tissue I 0 + - drv Cdl Rct Rct Rs Cdl Idrv -Idrv VDDH VA VB Istim Tan Tint Tca Tdis (b) (d) (c) V VA VDDH VA VB VB stim Istim Tissue I + - drv Idrv (a) V VDDH stim I φan φan φan φca φdis φca φca stim Cdl,eq Rct,eq Rs VA VB VCdl,eq,an Vdrop Figure 2. ( a , b ) Simplified schematics of unipolar and bipolar electrical neural stimulators. ( c ) Current and voltage stimulation waveforms. (d) Electrical model of the ETI and lumped model. It has been experimentally demonstrated that the use of a cathodic phase to reverse the electrochemical process occurring in the anodic phase may eventually preclude the generation of action potentials [ 25 ]. To prevent this suppressing effect, an interphase delay, Tint , of around 100µs is typically introduced in the biphasic stimulation. Considering this delay, the complete stimulation waveform is illustrated in Figure 2c. The stimulation mechanism differs depending on the circuit topology. In the monopolar case, two different current sources are used to inject and sink a charge from a single stimulation node A, while in the bipolar case a single current source is used for both purposes at the expense of using two electrodes, A and B. In this latter case, the anodic current flows from node A to B, while in the cathodic phase, the current flows in the reverse direction, from B to A. In both circuits, the interphase delay is simply implemented by opening all the switches between the anodic and cathodic phases. In this state, there is no current flow, the electrical potential across the ETI is constant, and the electrode voltages take values between the power supply of the neural stimulator, VDDH , and ground. These values are determined by voltage division according to the impedance of the switches in the same circuit branch. Due to the non-stationary nature of the ETI, its nonlinear characteristics, and the fact that some electrochemical reactions are not reversible, circuit techniques to guarantee the desired charge balance between the anodic and cathodic phases are needed to improve the safety of the stimulator. In the case of monopolar stimulation, charge balancing is even more difficult due to the potential mismatch between the current sources used for injecting and retrieving charge from the tissue. In contrast, the bipolar topology is intrinsically tolerant to matching problems because it uses only one current source. A simple approach, suitable both for monopolar and bipolar structures, to force |Qan|=|Qca| even in the case of perfectly matched current sources, is to trigger a post-stimulation blanking period in which the electrodes are short-circuited to ground for a time Tdis [ 25 ]. As shown in Figure 2a, this requires an extra switch in the monopolar topology, while in the bipolar scheme the bottom switches in Figure 2b can be reused for the discharge phase. Figure 2c also shows this blanking phase. In this work, a high-precision bipolar stimulator with discharging phase is designed. Figure 2d shows a simplified model of the equivalent impedance, ZL , between the stimulation nodes A and B in the schematics of Figure 2b [ 25 , 34 ]. Such impedance is given by ZL(s) = Rs+Rct,eq 1+s·Rct,eq·Cdl,eq , (1) where Rs models the spreading resistance of the neural tissue, Cdl,eq =Cdl/ 2 takes into account the electrical double-layer capacitance at the ETI, and Rct,eq = 2 Rct is an equivalent charge transfer resistance that models the faradaic electrochemical reactions at the electrode Sensors 2022,22, 6429 4 of 17 surface [ 25 ]. The voltage between the electrodes A and B, Vstim(t) = |VA(t)−VB(t)| , during the anodic phase (a similar analysis can be done for the cathodic phase) is given by Vstim(t) = Idrv·Rs+VCdl,eq (t), (2) where t∈[ 0, Tan] and VCdl,eq (t) is the voltage across the equivalent double-layer capacitance given by VCdl,eq (t) = Idrv·Rct,eq −(Idrv·Rct,eq +VCdl,eq,0 )·e−t τ, (3) where VCdl,eq,0 is the VCdl voltage stored at the beginning of the pulse and τ=Rct,eq·Cdl,eq . Assuming that the time constant of the ETI is much larger than the duration of the anodic phase, i.e., Tan τ as it occurs in practice, the peak stimulation voltage between the electrodes at the end of the anodic phase ( t=Tan ) (preserved during the interphase delay period) can be approximated as Vstim,pk ≈VCdl,eq,0 +Idrv Rs+Tan Cdl,eq !. (4) The efficiency ηstim of the neural stimulator during the anodic phase can be defined by the ratio between the energy delivered to the tissue and the energy supplied by the voltage supply, VDDH. Hence, assuming again that Tan τ, the following expression is obtained: ηstim =RTan 0Vstim(t)·Idrv·dt RTan 0VDDH·Idrv·dt ≈Idrv VDDH · Rs+Tan 2·Cdl,eq !, (5) which shows that the efficiency depends on the load impedance and the pulse characteristics. Clearly, the efficiency increases by reducing the supply voltage VDDH up to the limit imposed by the peak stimulation voltage Vstim,pk in (4). On the other hand, for a given VDDH value, the efficiency and peak of the stimulation voltage decrease both with the amplitude and width of the current pulse, and the stimulator may be forced to withstand a large voltage gap between the supply voltage and VA . These considerations are taken into account in the proposed design. 3. System Architecture and Circuit Design Figure 3shows the proposed HV electrical neural stimulator. It consists of two main blocks: a fully on-chip power management unit and a stimulator front-end. The former includes a DC-DC converter, which provides a programmable supply voltage VDDH ∈[ 4.2,13.2 ] V for the stimulation driver; a resistorless bandgap [ 35 ]; and a 25nA self-biased current reference [ 36 ] (not shown in Figure 3for simplicity). The stimulator front-end comprises a 5bits current-steering digital-to-analog converter (DAC), a current mirror that generates a current Idrv ∈[ 0.07,2.08 ] mA, a high-voltage-tolerant H-bridge biphasic stimulation interface, and an H-bridge driver. This latter includes a high-compliance voltage cell (HCVC) to protect the circuit from excessive voltage drops between the transistor’s terminals. 3.1. Switched-Capacitor DC-DC Converter As shown in Figure 3, it is based on a 4 × 4 array of individually configurable charge pump (CP) cells. The outputs of all the CPs in the same column are connected together. Active rows and columns are enabled using the ROWS ={ROWSi} , i= 1, . . . ,4, and COLS ={COLSj} , j= 1, . . . ,4, configuration words, respectively. All possible row combinations, 16 in total, are possible. However, a column can only be activated if the previous one is enabled and, therefore, only four combinations are possible. In the following, the number of activated rows (alt. columns) will be denoted as Ma(alt. Na). Sensors 2022,22, 6429 5 of 17 Programming interface LS Clock gen charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump Charge-pump array charge pump Regulation loop x0.1 VCO DAC VREF ROWS COLS 1.8 V V in Vin VDDH 1.8 V 5-bits DAC H-bridge driver H-bridge DC-DC Converter Stimulator Front-End IREF STIM DISCH Current mirror VB4 VB3 VB2 VB1 Figure 3. Block-level scheme of the proposed HV neural stimulator. The output voltage VDDH of the converter is locked by a regulation loop that sets the pumping frequency, fp , of the CP cells. This frequency ranges from approximately 5MHz to 60MHz. Under lock-in conditions, VDD,H=10 ×Vre f for Vre f ∈[0.42,1.32], and is defined as VDDH =Na·Vpump +Vin, (6) where Vin is the input voltage of the CP cells (3V in this work) and Vpump is the voltage pumped by each stage in an enabled column. This voltage is given by Vpump =Vin −RCP·IL, (7) where IL is the load current of the DC-DC converter and RCP is the equivalent resistance of the CP cell given by RCP =Na 2·Ma·fp·Cf ly , (8) where Cf ly is the flying capacitance of each charge pump cell [ 37 ]. In this design, Cf ly amounts to 12.5pF. Programming the number of active columns requires the DC-DC converter to internally generate four bias voltages VB1−B4 , which are voltage-shifted versions of the selection signals, COLS1−4 . Table 1shows the expressions for VB1−B4 in terms of Na , and Figure 4a illustrates the connection between the CP units and the distribution of the control signals ROWSi and VBj . Figure 4b shows the circuit that generates the bias voltages VBj (by construction, COLS1=VB,1 =Vin ). The blocks that slide the signals COLSj are floating level-shifters (FLS) [ 38 , 39 ]. These circuits can tolerate non-periodical input signals and shifting voltage variations and are suitable for non-HV technology processes— see [ 39 ] for more details. Table 1. DC-DC converter’s output voltage and biasing voltages, depending on the number of stages enabled. Vpump is defined in (7). Node Na=1 Na=1 Na=1Na=2 Na=2 Na=2Na=3 Na=3 Na=3Na=4 Na=4 Na=4 VDDH Vin +Vpump Vin +2·Vpump Vin +3·Vpump Vin +4·Vpump VB1Vin Vin Vin Vin VB2Vin Vin +Vpump Vin +Vpump Vin +Vpump VB3Vin Vin +Vpump Vin +2·Vpump Vin +2·Vpump VB4Vin Vin +Vpump Vin +2·Vpump Vin +3·Vpump Sensors 2022,22, 6429 6 of 17 VCP1 VB2 Floating level-shifter VB1 COLS2 Vin VB1 COLS1 VCP2 VB3 Floating level-shifter VB2 COLS3 VCP3 VB4 Floating level-shifter VB3 COLS4 CP unit ROWS1 VB1 Vin CP unit ROWS1 VB2 Vin CP unit ROWS1 VB3 Vin CP unit ROWS1 VB4 Vin Vin VDDH (a) (b) CP unit ROWS2 VB1 Vin CP unit ROWS2 VB2 Vin CP unit ROWS2 VB3 Vin CP unit ROWS2 VB4 Vin CP unit ROWS3 VB1 Vin CP unit ROWS3 VB2 Vin CP unit ROWS3 VB3 Vin CP unit ROWS3 VB4 Vin CP unit ROWS4 VB1 Vin CP unit ROWS4 VB2 Vin CP unit ROWS4 VB3 Vin CP unit ROWS4 VB4 Vin Figure 4. ( a ) Block diagram of the CP array. ( b ) Schematic of the circuit generating the voltage-shifted versions of the column selection signals, COLSi . VCPi corresponds to the output voltage if the i-th column of the CP array. Figure 5illustrates the operation of the DC-DC converter at startup for a target operation point with VDDH = 11.5V, IL= 1mA, Ma= 3, and Na= 4. As can be seen, the desired output voltage is reached after roughly 12µs. 0 2 4 6 8 10 12 14 16 18 20 Time (us) 0 2 4 6 8 10 12 14 Voltage (V) Figure 5. Simulation of the startup of the DC-DC converter. The output settles at a 11.5V output voltage in roughly 12µs. 3.2. H-Bridge Figure 6shows the proposed high-voltage-tolerant H-bridge. Each branch has one PMOS and one NMOS switch (driven by signals SPx and SNx , respectively) as well as a HCVC. This circuit consists of eight stacked transistors (shaded in green) and a dynamic gate biasing circuit [ 40 – 42 ] (shaded in blue). NMOS transistors are implemented in Deep N-Wells, whereas PMOS transistors have local N-Wells. The proposed solution follows the design principles presented in [ 42 ] but includes modifications aimed at extending the operation range. Modifications consist of two additional stacked transistors and four additional transistors in the dynamic gate biasing circuit. Moreover, the HCVC is biased with the voltages internally generated by the DC-DC converter VB,1−4 , and, hence, no Sensors 2022,22, 6429 7 of 17 additional dynamic biasing circuitry is needed. The circuit allows one to power the frontend of the stimulator with a wide range of voltages (up to 4 times the nominal voltage of the technology) while driving a wide range of ETI impedances and without damaging the 3.3V stacked transistors. P1 1 High Compliance Voltage Cell High Compliance Voltage Cell 5 6 7 8 9 10 11 12 13 14 2 3 4 P2 P3 P4 P5 P6 P7 P8 P9 P10 SN1 SP1 VB4 VB3 VB2 VB1 SN2 SP2 Idrv Istim VB4 V DDH VB4 V DDH VB3 VB2 VB1 N1 N5 N6 N7 N8 N9 N10 N2 N3 N4 Vstim RsRct,eq Cdl,eq Dynamic gate biasing Stacked transistors Vin 0 VDDH VB4 Vin 0 5 6 6 7 12 12 13 14 P 5 P 6 P 7 P 8 P P 9 10 N 5 N 6 N 7 8 N N 9 N 10 P 1 8 9 10 2 3 4 P P P N N N N Figure 6. Proposed high-voltage-tolerant H-bridge, including the HCVC. To describe the operation of the proposed high-voltage-tolerant H-bridge, two simulations are carried out. In both cases, the load is purely resistive and SP1=VB4 , SP2=VDDH , SN1= 0, and SN2=Vin . Thus, the top-left and bottom-right switches are ON, whereas the top-right and bottom-left switches are OFF. In the first simulation, the voltage supply of the neural stimulator front-end is set to 13V, Idrv = 2mA; Rs is swept from 10Ω to 5kΩ ; and Na= 4 (i.e., VB1= 3V, VB2= 5.5V, VB3= 8V, and VB4= 10.5V—see Table 1). As shown in Figure 7a, when Vstim <Vin , transistors P1−4 are saturated and equally withstand the voltage drop across the H-bridge. As Vstim increases, the voltage V4 also increases, so transistor N7 turns on, V7 approaches V6 , and transistor P4 enters in triode mode. As Vstim increases further, this behavior is sequentially repeated for voltage V3 , transistor N6 , voltage V6 , and transistor P3 , respectively, and then for voltage V2 , transistor N5 , voltage VB4 , and transistor P2 . Transistors P8 (resp. P9 ) ensure that nodes V5 (resp. V6 ) are gradually connected to VB3 . Moreover, as Vstim increases, transistor N8starts to turn on and continuously connects node 14 to VB3. On the contrary, as shown in Figure 7b, when Vstim <Vin , transistors N1−4 act as closed switches, i.e., they are biased in the deep triode region. As Vstim rises, so do V8−11 , thus switching P5−7 off. At the same time, N9−10 progressively make cause V12,13 to approach VB2,14 , respectively. Thus, N1−4 gradually increase their drain-to-source voltage to a maximum drop of roughly Vin . Finally, opposite N8 , transistor P10 starts biasing node 14 to VB2 and continuously switches off. The gate voltages of the stacked transistors, which permit proper biasing to adapt the stimulation voltage, are shown in Figure 7c. Sensors 2022,22, 6429 8 of 17 012345678910 Vstim (V) 3 6 9 12 Voltage (V) 012345678910 0 3 6 9 12 Voltage (V) 012345678910 3 6 9 12 Voltage (V) V 1V 2V 3V 4 V 8V 9V 10 V 11 (a) (b) (c) V 6V 7V 12 V 5V 13 V 14 Vstim (V) Vstim (V) (d) (e) (f) Vstim (V) Vstim (V) Vstim (V) 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 3 4.5 6 7.5 9 Voltage (V) V 1V 2V 3V 4 0 3 6 9 Voltage (V) V 8V 9V 10 V 11 2 3 4 5 6 Voltage (V) V 6V 7V 12 V 5V 13 V 14 Figure 7. Evolution of the voltages at the nodes of the HCVC, as depicted in Figure 6. ( a – c ) The load resistance, Rs , is swept from 10Ω to 5kΩ , VDDH = 13V, and Na= 4. ( d – f ) The load resistance, Rs , is swept from 0 to 3kΩ,VDDH = 8 V, and Na=2. In the second simulation, the voltage supply of the neural stimulator front-end is set to 7V, Na= 2. (i.e., VB1= 3V, VB2= 5V, VB3= 5V, and VB4= 5V), and RS= [ 0,3 ]kΩ . In this case, as shown in Figure 7d, when Vstim <Vin , transistors P1−3 are biased in deep triode region, whereas P4 is saturated. Thus, now the voltage drop in the HCVC is approximately the source-to-drain voltage of P4 , which is around 2V. As Vstim increases, P4 gradually enters in deep triode region, leading to a voltage drop across the HCVC close to zero. Figure 7e shows that transistors N1−4 are biased in the deep triode region and they sequentially enter in saturation as Vstim rises. As before, Figure 7f shows the gate voltages of the stacked transistors. The simulations in Figure 7show that the proposed H-bridge has two fundamental features. First, it withstands up to 4 ×VDD voltage differences between input output nodes. Second, it acts as an H-bridge with low on resistance. Both behaviors manifest depending on the stimulation current, the supply voltage VDDH, and the load impedance. 3.3. DAC and Current Mirror Figure 8shows the schematics of the DAC and current mirror represented in Figure 3. The DAC uses a 5-bit thermometric current-steering topology and is supplied at 1.8V. A MUX-based 5-to-32 thermometer decoder [ 43 ] is used for converting the binary input to thermometric. The output impedance of the DAC is enhanced by means of a regulated cascode topology with a current-mirror OTA. The DAC output current can reach up to 15.6µA at 0.5µA steps. The current mirror is supplied at VDDH , it has a gain of 128; and it implements a regulated cascode current mirror topology that achieves good output impedance, a fast transient response, and uses no operational amplifiers [ 44 ]. Two MOS capacitors of approximately 110fF are added to reduce overshoots in the output current during the anodic and cathodic phases. Two HCVC cells connect the DAC output and the biasing current of the regulated cascode circuit to the current mirror. Sensors 2022,22, 6429 9 of 17 250 nA S[0] S[0:31] IN[0:4] S[0] 1:2 1:128 ref ref ref S[1] S[1] S[31] S[31] 5-to-32 Thermometer Encoder 1.8 V X Y Z OS 100 nA M VDDH Idrv 1 2 3 M M5 M6 M M4 High Compliance Voltage Cell VB4 VB3 VB2 VB1 High Compliance Voltage Cell VB4 VB3 VB2 VB1 1.8 V 1.8 V Figure 8. Schematic of the 5bits current-steering DAC, current mirror, and two HCVCs for interfacing LV and HV circuits. Biasing currents are copies of an on-chip 25nA self-biased current source [36]. 3.4. H-Bridge Driver The H-bridge driver converts the input signals STIM and DISCH to the four signals driving the H-bridge— SP,1−2 and SN,1−2 —and to the signal reducing the current overshoot, OS. Figure 9shows a timing diagram of these signals. It consists of a Mealy’s finite state machine and level shifters for adapting the signals to the adequate voltage level. The level shifters driving the PMOS switches of the H-bridge are implemented as FLS. 0 (a) (b) STIM=`1´ STIM=`0´STIM=`1´ STIM=`0´ 2 STIM STATE 0 WAIT/DISCH ANODIC DELAY CATHODIC STATE 1 STATE 2 STATE 3 STATE 0 DISCH SP1 Tan Tint Tca Tdis SP2 SN1 SN2 OS 1 3 Figure 9. ( a ) Mealy’s state machine implemented for driving the H-bridge. ( b ) Timing diagram of signals generated by the H-bridge driver. 4. Experimental Results Figure 10 shows a micro-photograph of the proposed neural stimulator, fabricated in a standard 0.18µm 1.8 V/3.3 V CMOS process. The circuit occupies an active area of 2.34mm2 , including the on-chip switched-capacitor DC-DC converter ( 2.1mm2 ), the stimulator front-end 0.15mm2 ), the internal serial peripheral interface (SPI) module for communication, and other test circuitry. No external components are needed. Sensors 2022,22, 6429 16 of 17 19. Palomeque-Mangut, D.; Schmid, A.; Rodríguez-Vázquez, Á.; Delgado-Restitute, M. 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